HK1247441A1 - 不具有裸片附接墊的引線載體結構和由此形成的封裝 - Google Patents

不具有裸片附接墊的引線載體結構和由此形成的封裝

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Publication number
HK1247441A1
HK1247441A1 HK18106943.5A HK18106943A HK1247441A1 HK 1247441 A1 HK1247441 A1 HK 1247441A1 HK 18106943 A HK18106943 A HK 18106943A HK 1247441 A1 HK1247441 A1 HK 1247441A1
Authority
HK
Hong Kong
Prior art keywords
die attach
carrier structure
formed therefrom
attach pads
packages formed
Prior art date
Application number
HK18106943.5A
Other languages
English (en)
Inventor
菲利普‧E‧羅杰
Original Assignee
由普萊克斯有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 由普萊克斯有限公司 filed Critical 由普萊克斯有限公司
Publication of HK1247441A1 publication Critical patent/HK1247441A1/zh

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    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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    • H01L2224/85498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/85598—Fillers
    • H01L2224/85599—Base material
    • H01L2224/85695—Base material with a principal constituent of the material being a gas not provided for in groups H01L2224/856 - H01L2224/85691
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/386—Wire effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
HK18106943.5A 2015-05-04 2018-05-28 不具有裸片附接墊的引線載體結構和由此形成的封裝 HK1247441A1 (zh)

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US201562156983P 2015-05-05 2015-05-05
PCT/US2016/030775 WO2016179278A1 (en) 2015-05-04 2016-05-04 Lead carrier structure and packages formed therefrom without die attach pads

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DE102016112289B4 (de) * 2016-07-05 2020-07-30 Danfoss Silicon Power Gmbh Leiterrahmen und Verfahren zur Herstellung desselben
US10577130B1 (en) * 2016-12-07 2020-03-03 Space Systems/Loral, Llc Flexible radio frequency converters for digital payloads
US9978613B1 (en) * 2017-03-07 2018-05-22 Texas Instruments Incorporated Method for making lead frames for integrated circuit packages
TWI718947B (zh) * 2020-05-13 2021-02-11 強茂股份有限公司 半導體封裝元件及其製造方法
US11562947B2 (en) 2020-07-06 2023-01-24 Panjit International Inc. Semiconductor package having a conductive pad with an anchor flange
CN112908862A (zh) * 2021-01-22 2021-06-04 山东盛品电子技术有限公司 一种无上片胶固定的芯片背面裸露封装方法及芯片

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JP3668101B2 (ja) * 2000-07-05 2005-07-06 三洋電機株式会社 半導体装置
KR100987376B1 (ko) * 2003-08-27 2010-10-12 삼성에스디아이 주식회사 리튬전지용 결합제와 전극 및 이를 채용한 리튬전지
US7205178B2 (en) * 2004-03-24 2007-04-17 Freescale Semiconductor, Inc. Land grid array packaged device and method of forming same
US9324672B2 (en) * 2009-08-21 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package
US7883991B1 (en) * 2010-02-18 2011-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Temporary carrier bonding and detaching processes
US8643165B2 (en) * 2011-02-23 2014-02-04 Texas Instruments Incorporated Semiconductor device having agglomerate terminals
WO2013022477A2 (en) * 2011-08-11 2013-02-14 Eoplex Limited Lead carrier with multi-material print formed package components
EP2657963B1 (en) * 2012-04-24 2017-09-06 Shin-Etsu Chemical Co., Ltd. Wafer-trilayer adhesive layer-support composite, wafer support with trilayer adhesive layer for use in wafer processing, trilayer adhesive layer for use in wafer processing, method of manufacturing said composite and method of manufacturing a thin wafer using said composite
WO2014037815A2 (en) * 2012-09-07 2014-03-13 Eoplex Limited Lead carrier with print-formed terminal pads
US9269623B2 (en) * 2012-10-25 2016-02-23 Rohm And Haas Electronic Materials Llc Ephemeral bonding
JP6033734B2 (ja) * 2013-04-30 2016-11-30 日東電工株式会社 フィルム状接着剤、ダイシングテープ一体型フィルム状接着剤、及び、半導体装置の製造方法

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US20180047588A1 (en) 2018-02-15
KR20180002812A (ko) 2018-01-08
WO2016179278A1 (en) 2016-11-10

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