HK1011454A1 - Resistor fabrication - Google Patents

Resistor fabrication

Info

Publication number
HK1011454A1
HK1011454A1 HK98112558A HK98112558A HK1011454A1 HK 1011454 A1 HK1011454 A1 HK 1011454A1 HK 98112558 A HK98112558 A HK 98112558A HK 98112558 A HK98112558 A HK 98112558A HK 1011454 A1 HK1011454 A1 HK 1011454A1
Authority
HK
Hong Kong
Prior art keywords
resistor fabrication
fabrication
resistor
Prior art date
Application number
HK98112558A
Other languages
English (en)
Inventor
John G Richards
Hector Flores
Original Assignee
Chipscale Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipscale Inc filed Critical Chipscale Inc
Publication of HK1011454A1 publication Critical patent/HK1011454A1/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
HK98112558A 1994-06-09 1998-11-30 Resistor fabrication HK1011454A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25772694A 1994-06-09 1994-06-09
PCT/US1995/006929 WO1995034083A1 (en) 1994-06-09 1995-06-01 Resistor fabrication

Publications (1)

Publication Number Publication Date
HK1011454A1 true HK1011454A1 (en) 1999-07-09

Family

ID=22977494

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98112558A HK1011454A1 (en) 1994-06-09 1998-11-30 Resistor fabrication

Country Status (8)

Country Link
US (1) US6121119A (de)
JP (1) JPH10508430A (de)
KR (1) KR100358446B1 (de)
AU (1) AU2659995A (de)
DE (1) DE19580604T1 (de)
GB (1) GB2302452B (de)
HK (1) HK1011454A1 (de)
WO (1) WO1995034083A1 (de)

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US6448153B2 (en) * 1996-10-29 2002-09-10 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US5904496A (en) * 1997-01-24 1999-05-18 Chipscale, Inc. Wafer fabrication of inside-wrapped contacts for electronic devices
US5910687A (en) * 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
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US20090032871A1 (en) * 2007-08-01 2009-02-05 Louis Vervoort Integrated circuit with interconnected frontside contact and backside contact
DE102010055935B4 (de) 2010-12-23 2014-05-15 Epcos Ag Verfahren zum Verbinden mehrerer ungehäuster Substrate
DE102011109007A1 (de) 2011-07-29 2013-01-31 Epcos Ag Verfahren zum Herstellen eines elektrischen Bauelements und elektrisches Bauelement
US9620473B1 (en) 2013-01-18 2017-04-11 University Of Notre Dame Du Lac Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment
JP6302644B2 (ja) * 2013-11-11 2018-03-28 株式会社ディスコ ウェーハの加工方法
EP3499552A1 (de) * 2017-12-14 2019-06-19 Nexperia B.V. Halbleiterbauelement und verfahren zur herstellung
US10770432B2 (en) * 2018-03-13 2020-09-08 Stmicroelectronics S.R.L. ASICS face to face self assembly
CN109659104B (zh) * 2018-12-28 2021-06-08 广东爱晟电子科技有限公司 一种高可靠双面异质复合电极热敏芯片

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Also Published As

Publication number Publication date
JPH10508430A (ja) 1998-08-18
GB2302452B (en) 1998-11-18
DE19580604T1 (de) 1997-05-07
GB9623265D0 (en) 1997-01-08
AU2659995A (en) 1996-01-04
GB2302452A (en) 1997-01-15
KR100358446B1 (ko) 2003-01-29
US6121119A (en) 2000-09-19
WO1995034083A1 (en) 1995-12-14

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20130601