GB2289372A - Method of manufacturing ohmic contact - Google Patents
Method of manufacturing ohmic contact Download PDFInfo
- Publication number
- GB2289372A GB2289372A GB9509196A GB9509196A GB2289372A GB 2289372 A GB2289372 A GB 2289372A GB 9509196 A GB9509196 A GB 9509196A GB 9509196 A GB9509196 A GB 9509196A GB 2289372 A GB2289372 A GB 2289372A
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- GB
- United Kingdom
- Prior art keywords
- forming
- semiconductor
- region
- substrate
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
Description
2289372 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE The present invention
relates to a method of manufacturing semiconductor devices, and particularly, to a method of manufacturing high-yield, high- performance semiconductor devices having electrodes that realize good ohmic contact characteristics. These semiconductor devices have a high breakdown voltage and may serve as power devices.
A prior art of forming an ohmic electrode of a semiconductor device having a high breakdown voltage or of a semiconductor power device will be explained. A semiconductor substrate is prepared. An active region including a diffusion layer, an oxide film, and metal wiring is formed in a given area on the substrate. The bottom surface of the substrate is mechanically ground and/or polished to a required thickness, and a metal film serving as an electrode is formed on the bottom surface. If the impurity concentration of the bottom surface where the metal electrode is formed is not sufficiently high, a Schottky barrier will be produced between the metal film and the substrate, to prevent good ohmic contact.
If the bottom surface of the substrate contains n-type impurities of about 1.0 x 1018/cm3, the Schottky barrier will be produced as shown in Fig. 1. The Schottky barrier forms Schottky-contact current-voltage characteristics as shown in Fig. 2 and never provides ohmic contact, to thereby deteriorate the performance of the device. Figure 3 shows a relationship between the impurity concentration NP (cm-') of a surface of a substrate where a metal film is formed and contact resistance Rc between the metal film and the substrate. As the impurity concentration ND increases, the contact resistance Rc decreases.- To realize lowresistance ohmic contact on the bottom surface of a semiconductor substrate, one prior art increases the impurity concentration of the bottom surface, to cause a tunnel effect as shown in Fig. 4 and pass tunneling carriers through a Schottky barrier formed between a metal film and the substrate. This prior art forms an active region including a diffusion layer and an oxide film on the substrate, mechanically grinds or polishes the bottom surface of the substrate to a required thickness, implants impurity ions such as 31P+ ions of 5 x 1015 CM-2 having the same conduction type as the substrate to the bottom surface, anneals the substrate in a nitrogen atmosphere at 950 degrees centigrade for 20 minutes, to form an n'-type diffusion layer of 5 x 1020 cm-3 in impurity concentration on the bottom surface, and forms a metal film serving as an ohmic electrode on the n±type diffusion layer. Figure 5 shows the current-voltage characteristics of the device thus formed.
This prior art grinds the bottom surface of a substrate to a required thickness. The grinding may cause cracks and warp the same during a heat treatment. The mechanical grinding or polishing and metal film deposition process may contaminate, stain,and damage the bottom surface of the substrate, to achieve a poor yield.
It would be desirable to be able to provide a method of manufacturing high-yield, high-performance semiconductor devices which are free from the problems of the prior art, have improved ohmic electrodes, show a high breakdown voltage, and may serve as power devices with high speed and low on voltage characteristics.
It would also be desirable to be able to provide a method of manufacturing semiconductor devices that realize good ohmic contact without a diffusion region of 5 high impurity concentration.
Accordingly, the present invention provides a method of forming semiconductor devices, including the steps of:
(a) forming a first thin film 24 such as a plasma oxide film containing charges on a semiconductor region 19 of a semiconductor substrate as shown in Fig. 6D; (b) removing the first thin film 24 as shown in Fig. 7A; (c) forming a second thin film 25 containing charges on the semiconductor region 19 as shown in Fig. 7B; and (d) forming metal films 26, 27, and 28 such as Ti, Ni, and Ag films on the second thin film 25, to thereby form an ohmic electrode for the semiconductor region 19 as shown in Fig. 7C.
The steps (a) and (b) remove contaminants from the surface of the semiconductor region 19 and may be omitted if the surface of the semiconductor region 19 is pure enough. Suitable films 24 and 25 containing charges are not only plasma oxide films but also plasma nitride films, oxide films formed by a UV-ozone process, or oxide films formed by oxidization with H2S04+H202 or HCl+H202. In Figs. 6 and 7, the metal films 26, 27, and 28 form an ohmic metal electrode on the bottom surface of the substrate. The ohmic metal electrode may be formed in an active region on the top surface of the substrate as shown in Figs. 10 and 11. For example, the present invention is applicable to form ohmic contact electrodes in given regions such as emitter, base, and collector regions, or source, drain, and gate regions of a discrete device having a planar structure or to the electrode in an integrated circuit (IC). The integrated circuit may contain a Power IC or a SMART Power IC. The present invention forms low-resistance ohmic contact without a diffusion layer of high impurity concentration, thereby simplifying manufacturing processes of discrete devices and ICs and providing these devices 5 with low ON resistance and a high operation speed.
Optional and preferred features of the present invention will become obvious upon an understanding of illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows an energy band diagram in metal-to semiconductor contact according to a prior art;
Fig. 2 shows the current-voltage characteristics of the contact of Fig. 1; Fig. 3 shows a relationship between the contact resistance Rc of metal-to-semiconductor contact and the impurity concentration ND of a semiconductor substrate; Fig. 4 shows an energy band diagram in metal-to semiconductor contact passing a tunnel current; Fig. 5 shows the current-voltage characteristics of the contact of Fig. 4; Figs. 6A to 6D and 7A to 7C show a method of manufacturing a bipolar transistor according to a first embodiment of the present invention; Fig. 8 shows an energy band diagram in metal-to semiconductor contact involving a thin film containing charges according to the present invention; Fig. 9 shows the current-voltage characteristics of the contact of Fig. 8; Figs. 10A to 10E and 11A to 11C show a method of manufacturing a planar diode according to a second -5 embodiment of the present invention; Fig. 12 shows a power MOSFET based on the first embodiment of the present invention; and Fig. 13 shows an IGBT based on-the first embodiment of 5 the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
Figures GA to 6D and 7A to 7C are sectional views showing a method of manufacturing a bipolar transistor according to the first embodiment of the present invention.
In Fig. 6A, an n-type semiconductor substrate 19 has an impurity concentration of 1 x 1016 cm-3. In Fig. 6B, an active region is formed on the substrate 19. The active region consists of a p-type diffusion layer 21, an n-type diffusion layer 22, an oxide film 20. a metal base electrode 81, and a metal emitter electrode 82. The substrate 19 serves as a collector region of the bipolar transistor, the diffusion layer 21 serves as a base region thereof, and the diffusion layer 22 serves as an emitter region thereof. In Fig. 6C, the bottom surface of the substrate 19 is ground or polished to a required thickness. In Fig. 6D, a plasma oxidation process is carried out to form a first plasma oxide film 24 of 3 to 5 nm thick on the bottom surface of the substrate 19. The film 24 may be formed in an Oz gas of 133 Pa and with a plasma power of 400 W applied for about 5 minutes. In Fig. 7A, the film 24 is removed by etching with hydrofluoric acid. At this time, contaminants are removed together with the film 24 from the bottom surface of the substrate 19. In Fig. 7B, a second plasma oxide film 25 of 3 to 5 rim thick is formed on the bottom surface of the substrate 19. In Fig. 7C. a metal collector electrode is formed on the oxide film 25 with metals selected from a group including titanium (Ti),chromium (Cr), aluminum (A1), vanadium (V), nickel (Ni), gold (Au), silver (Ag), etc. In this embodiment, the metal collector electrode is a three-layer collector electrode composed of a Ti layer 26, an Ni layer 27, and an Ag layer 28.
The first embodiment is characterized by forming the first and second plasma oxide films (silicon oxide films) 24, 25. In particular, the first embodiment is characterized by forming the second plasma oxide film 25 as an interface between metal electrode layers 26, 27, 28 and a semiconductor substrate 19. Generally, a silicon semiconductor substrate forms a silicon oxide film when the surface of the substrate is oxidized and deteriorates the ohmic contact characteristics. This silicon oxide film is an insulation film, and therefore, it has been assumed to provide large resistance if it is interposed between the semiconductor substrate and a metal electrode layer like the first embodiment of the present invention. The first embodiment, however, greatly reduces-the contact resistance of the ohmic contact structure having a silicon oxide film by grinding or polishing one surface of the substrate, employing the oxygen plasma process to form the silicon oxide film over the surface damaged by the grinding, and fabricating the metal electrode layer on the silicon oxide film.
The reason why the present invention is capable of reducing the contact resistance of the ohmic electrode having an interface oxide film is because the oxide film containing charges narrows the width of a depletion layer as shown in Fig. 8 and causes a tunneling effect to pass carriers through the Interface oxide film. In addition, the oxide film on the damaged silicon surface may partly directly connect the substrate to the metal electrode, to improve the performance of the electrode. Figure 9 shows the current-voltage characteristics of the metal electrode according to the first embodiment of the present invention.
As explained above, the first embodiment of the present invention forms a thin film containing charges on the bottom surface of a semiconductor substrate, and fabricates a metal layer on the thin film, to realize ohmic contact between the semiconductor substrate and the metal layer without using a contact region of high impurity concentration. Namely, without implanting a large dose of ions, which may deteriorate yield of semiconductor devices. after a polishing or grinding process of adjusting the thickness of a substrate, the first embodiment simply forms an electrode of low contact resistance. Accordingly, the first embodiment is capable of manufacturing highyield. high-performance semiconductor devices.
The first plasma oxide film 24 is formed and etched off, to remove contaminants from the bottom surface of the substrate 19. The oxide film 24 may be omitted, and only the second plasma oxide film 25 may be formed. Even the film 25 alone is capable of greatly reducing resistance between the metal electrode layers 26 to 28 and the semiconductor substrate 19. The plasma oxide films 24 and 25 may be plasma nitride films or oxi-nitride (SiON) films. The plasma nitride films and plasma SiON films also contain charges to greatly reduce resistance between the metal electrode layers 26 to 28 and the semiconductor substrate 19. The oxide thin films 24 and 25 containing charges may be formed by oxidation with HF, H202, H2S04+H202, or HCl+H20a or by UV- ozone process, to reduce resistance between the metal electrode layers 26 to 28 and semiconductor substrate 19.
Figures 10A to 10E and 11A to 11C are sectional views showing a method of manufacturing a planar diode according to the second embodiment of the present invention. The first embodiment of the present invention forms an ohmic collector electrode over the bottom surface of a substrate. The second embodiment applies the method of the present invention to an active region of a semiconductor substrate. The diode shown in Figs. 10A to 10E and 11A to 11C is a part of an IC, a power IC having FETs or IGBTs (insulated gate bipolar transistors) on the same chip, or a part of a discrete device.
In Fig. 10A, an n-type semiconductor substrate 29 is prepared. In Fig. 10B, a p-type diffusion layer 30 and an oxide film 31 are formed on the substrate 29. In Fig. 10C, contact holes 32 are formed through the oxide film 31 up to the substrate 29 serving as a cathode region and the diffusion layer 30 serving as an anode region. In Fig. 10D, a plasma oxidation process is employed to form a first plasma oxide film 24 of 3 to 5 rim thick in an active region on the substrate 29. The oxide film 24 may be formed with a plasma resist asher, an 02 gas of 133 Pa controlled by a mass-flow controller. and a plasma power of 400 W applied for five minutes. In Fig. 10E, the oxide film 24 is removed by etching with hydrofluoric acid. In Fig. 11A, the plasma oxidation process is again employed to form a second plasma oxide film 25 of 3 to 5 nm thick on the active region. In Fig. 11B, a titanium film 35 of 200 nm thick is deposited by EB deposition or spattering, and an aluminum film 34 of 1000 nm thick is formed, to provide metal wiring. In Fig. 11C, an anode electrode 91 and a cathode electrode 92 are formed by photolithography.
Unlike the prior art that must form an W1'-type contact region of high impurity concentration region diffused in a relatively low impurity concentration n-type semiconductor substrate before forming a metal layer on the substrate, the present invention is capable of forming the ohmic cathode electrode 92 of low resistance without the n-type contact region.
Similarly, the present invention is capable of forming -p the ohmic anode electrode 91 without a p±type contact region of high impurity concentration. Since the present invention involves no processes of forming the n± and p+type contact regions, it improves productivity, increases the degree of freedom in designing an active region of a semiconductor device, and minimizes the space for the active region.
Although the present invention has been explained with reference to the bipolar transistor and planar diode, the present invention is not limited to these devices. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure, without departing from the scope thereof. For example. the method of the present invention is applicable to manufacturing MOSFETs, IGBTs, SITs (static induction transistors), GTO (gate turn-off) thyristors, SITHs (static induction thyristors), MCTs (MOS-controlled thyristors), ESTs (emitter switched thyristors), etc.
Figure 12 is a sectional view showing a power MOS transistor based on the first embodiment of the present invention. An n- type silicon semiconductor substrate 38 has a (100) plane and serves as a high-resistance n--type drift region 38 of low impurity concentration. An n-type drain region 44 of 1 x 1010 cm-3 in impurity concentration is formed on the bottom surface of the substrate 38. A ptype base region 46 is formed along the top surface of the drift region 38. An n'"-type source region 45 is formed along the surface of the base region 46. A thin gate insulation film such as an SiO2 film 49 is formed on the base region 46, and a polysilicon gate 42 is formed on the gate insulation film 49. The gate 42 may be made of not only polysilicon but also refractory metal such as W, Ti, or Mo, a silicide of the refractory metal, or a polycide of the refractory metal. The gate 42 extends over the base region 46. Namely, the gate 42 extends from one source region 45 to another source region 45 over the drift region 38. The source region 45 is short-circuited with the base region 46 through a metal source electrode 41 made of Al or Al-Si. A metal gate electrode (not shown) made of, for example, Al is connected to the gate 42. A plasma oxide film 25 is formed on the drain region 44, and a metal drain electrode 43 is formed on the oxide film 25. Namely, the drain electrode 43 is connected to the drain region 44 through the oxide film 25. The drain electrode 43 may be made of Ti, Ni, and Ag layers, to provide good ohmic characters like Fig. 9. The ON resistance of the power MOSFET of Fig. 12 is very small. Similar to the second embodiment, the active region, i.e., the source electrode 41 may be formed on a thin plasma oxide film, plasma nitride film, or plasma oxi-nitride film.
Figure 13 is a sectional view showing a unit cell of an IGBT based on the first embodiment of the present invention. The upper part of the unit cell of the WBT has a MOSFET structure and the lower part thereof has a bipolar transistor structure. A p-type collector region 54 is 1 x 10 em in impurity concentration. An n-type buffer layer 58 is formed on the collector region 54. A highresistance n-type base region 48 of low impurity concentration is formed on the buffer layer 58. The n-type buffer layer 58 is formed to realized high breakdown voltage with a relatively thin layer of n-type base region 48. Hence, the n-type buffer layer may be omitted in some cases. A p-type base region 56 is formed along the top surface of the base region 48. An n±type emitter region 55 Is formed along the surface of the base region 56. A thin gate insulation film 49 made of, for example, SiO2 is formed on the base region 56, and a polysilicon gate electrode 52 is formed on the insulation film 49. The gate electrode 52 extends over the base region 56. Namely, the gate electrode 52 extends from one emitter region 55 to another emitter region 55 over the base region 48. The emitter region 55 is short-circuited with the base region v 56 through a metal emitter electrode 51. A metal gate electrode (not shown) is connected to the gate electrode 52. A plasma oxide film 25 of 3 to 5 nm thick is formed on the bottom surface of the collector region 54. A collector electrode 53 made of Ti, Ni, and Ag layers, or A1 and W layers is formed on the oxide film 25, to provide good ohmic contact like Fig. 9. The device of Fig. 13 has low ON resistance, a small conduction loss, and high conversion efficiency. Similar to the second embodiment of the present invention, the emitter electrode 51 may be formed on a thin plasma oxide film containing charges.
As explained above in detail, the method of manufacturing a semiconductor device as described herein includes the steps of forming a first thin film such as a plasma oxide film containing charges on a semiconductor substrate, removing the first thin film, forming a second thin film such as a plasma oxide film a plasma nitride film or a plasma SiON film containing charges on the substrate, and forming a metal electrode on the second thin film. This method is capable of forming an ohmic metal electrode which achieves low ohmic contact resistance Rc, without requiring a high impurity concentration contact region formation process even on a semiconductor region involving relatively low impurity concentration, thereby reducing the number of manufacturing processes. Hence, this method can improve the yield of semiconductor devices, increase the degree of freedom in designing the devices, minimize the size of the devices, lower the on-resistance of the devices, and improve the high-frequency characteristics and conduction loss characteristics of the devices.
-M-
Claims (14)
1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a thin film containing charges on a predetermined semiconductor region of a semiconductor substrate; and (b) forming a metal film on the thin film, to form an ohmic electrode for the semiconductor region.
2. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a first thin film containing charges on a predetermined semiconductor region of a semiconductor substrate; (b) removing the first thin film; (c) forming a second thin film containing charges on the semiconductor region; and (d) forming a metal film on the second thin film, to form an ohmic electrode for the semiconductor region.
3. A method as claimed in claim 1 or 2, including the step of thinning the semiconductor substrate to a required thickness before said step (a).
4. A method as claimed in any one of claims 1 to 3, including the steps of forming an impurity diffused layer on a first principal surface of the semiconductor substrate, and forming said predetermined semiconductor region on a second principal surface of the semiconductor substrate oppositely facing to the first principal surface.
5. A method as claimed in any one of claims 1 to 3, including the step of forming said predetermined semiconductor region in a part of an active region formed on a first principal surface of the semiconductor i 1 substrate.
6. A method as claimed in claim 5, including the step of forming a second semiconductor region on the first principal surface of the semiconductor substrate, the conductivity type of the second semiconductor region differing from that of said predetermined semiconductor region.
7. A method as claimed in claim 3, employing a grinder to mechanically thin the semiconductor substrate.
8. A method as claimed in any one of claims 1 to 3, employing a plasma oxidation or nitridation process when forming the thin film(s) containing charges.
9. A method as claimed in any one of claims 1 to 3, employing chemicals including H2S04 when forming the thin film(s) containing charges.
10. A method as claimed in any one of claims 1 to 3, employing a UV-ozone process when forming the thin film(s) containing charges.
11. A method of manufacturing a semiconductor device, substantially as described with reference to Figures 6A-D and 7A-C or Figures lOA-E and 11A-C of the accompanying drawings.
12. A semiconductor device manufactured by a method according to any preceding claim.
13. A semiconductor device substantially as described with reference to, and as shown in, Figure 12 or Figure 13 of the accompanying drawings.
14. An electrical circuit including a semiconductor device according to claim 12 or 13.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9632194A JPH07307306A (en) | 1994-05-10 | 1994-05-10 | Manufacture of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9509196D0 GB9509196D0 (en) | 1995-06-28 |
| GB2289372A true GB2289372A (en) | 1995-11-15 |
| GB2289372B GB2289372B (en) | 1998-08-19 |
Family
ID=14161756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9509196A Expired - Fee Related GB2289372B (en) | 1994-05-10 | 1995-05-05 | Method of manufacturing semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH07307306A (en) |
| DE (1) | DE19516998A1 (en) |
| GB (1) | GB2289372B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10084994B4 (en) * | 1999-09-02 | 2006-10-19 | Micron Technology, Inc. | A method of forming a conductive silicide layer on a silicon-containing substrate and methods of forming a conductive silicide contact |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5600985B2 (en) * | 2010-03-24 | 2014-10-08 | 三菱電機株式会社 | Method for manufacturing power semiconductor device |
| JP5721339B2 (en) * | 2010-04-01 | 2015-05-20 | 三菱電機株式会社 | Semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS513574A (en) * | 1974-06-26 | 1976-01-13 | Nippon Electric Co | IONCHUNYUSARETAKIBANNO SHORIHOHO |
| US4186410A (en) * | 1978-06-27 | 1980-01-29 | Bell Telephone Laboratories, Incorporated | Nonalloyed ohmic contacts to n-type Group III(a)-V(a) semiconductors |
| EP0029334A1 (en) * | 1979-11-15 | 1981-05-27 | The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and | Series-connected combination of two-terminal semiconductor devices and their fabrication |
| US4298403A (en) * | 1980-02-28 | 1981-11-03 | Davey John E | Ion-implanted evaporated germanium layers as n+ contacts to GaAs |
| EP0042066A2 (en) * | 1980-06-12 | 1981-12-23 | International Business Machines Corporation | Intermetallic semiconductor devices |
| EP0164720A2 (en) * | 1984-06-14 | 1985-12-18 | International Business Machines Corporation | An ohmic contact for an intermetallic compound semiconductor and a method of providing such a contact |
| WO1988005601A1 (en) * | 1987-01-16 | 1988-07-28 | The Marconi Company Limited | Contact to cadmium mercury telluride |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3755026A (en) * | 1971-04-01 | 1973-08-28 | Sprague Electric Co | Method of making a semiconductor device having tunnel oxide contacts |
| JPS59213145A (en) * | 1983-05-18 | 1984-12-03 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5229631A (en) * | 1990-08-15 | 1993-07-20 | Intel Corporation | Erase performance improvement via dual floating gate processing |
| US5102814A (en) * | 1990-11-02 | 1992-04-07 | Intel Corporation | Method for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctions |
| US5150176A (en) * | 1992-02-13 | 1992-09-22 | Motorola, Inc. | PN junction surge suppressor structure with moat |
-
1994
- 1994-05-10 JP JP9632194A patent/JPH07307306A/en active Pending
-
1995
- 1995-05-05 GB GB9509196A patent/GB2289372B/en not_active Expired - Fee Related
- 1995-05-09 DE DE1995116998 patent/DE19516998A1/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS513574A (en) * | 1974-06-26 | 1976-01-13 | Nippon Electric Co | IONCHUNYUSARETAKIBANNO SHORIHOHO |
| US4186410A (en) * | 1978-06-27 | 1980-01-29 | Bell Telephone Laboratories, Incorporated | Nonalloyed ohmic contacts to n-type Group III(a)-V(a) semiconductors |
| EP0029334A1 (en) * | 1979-11-15 | 1981-05-27 | The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and | Series-connected combination of two-terminal semiconductor devices and their fabrication |
| US4298403A (en) * | 1980-02-28 | 1981-11-03 | Davey John E | Ion-implanted evaporated germanium layers as n+ contacts to GaAs |
| EP0042066A2 (en) * | 1980-06-12 | 1981-12-23 | International Business Machines Corporation | Intermetallic semiconductor devices |
| EP0164720A2 (en) * | 1984-06-14 | 1985-12-18 | International Business Machines Corporation | An ohmic contact for an intermetallic compound semiconductor and a method of providing such a contact |
| WO1988005601A1 (en) * | 1987-01-16 | 1988-07-28 | The Marconi Company Limited | Contact to cadmium mercury telluride |
Non-Patent Citations (1)
| Title |
|---|
| WPI Abstract Accession No 76-15479X/09 & JP51003574 (NIPPON ELECTRIC) 13/1/76 (see abstract) * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10084994B4 (en) * | 1999-09-02 | 2006-10-19 | Micron Technology, Inc. | A method of forming a conductive silicide layer on a silicon-containing substrate and methods of forming a conductive silicide contact |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9509196D0 (en) | 1995-06-28 |
| GB2289372B (en) | 1998-08-19 |
| DE19516998A1 (en) | 1995-11-23 |
| JPH07307306A (en) | 1995-11-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20000507 |