FR2417139A1 - Multiplieur-sommateur perfectionne - Google Patents
Multiplieur-sommateur perfectionneInfo
- Publication number
- FR2417139A1 FR2417139A1 FR7803547A FR7803547A FR2417139A1 FR 2417139 A1 FR2417139 A1 FR 2417139A1 FR 7803547 A FR7803547 A FR 7803547A FR 7803547 A FR7803547 A FR 7803547A FR 2417139 A1 FR2417139 A1 FR 2417139A1
- Authority
- FR
- France
- Prior art keywords
- circuits
- summator
- columns
- same time
- analogue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Optimization (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Computer Hardware Design (AREA)
- Automation & Control Theory (AREA)
- Evolutionary Computation (AREA)
- Fuzzy Systems (AREA)
- Software Systems (AREA)
- Complex Calculations (AREA)
Abstract
Multiplieur matriciel comportant un circuit d'entrée destiné à effectuer les produits élémentaires des chiffres du multiplicande par les chiffres du multiplicateur, des moyens de sommation analogique des produits élémentaires obtenus et des moyens de conversion des signaux analogiques résultants en signaux numériques, caractérisé en ce que lesdits moyens de sommation analogique sont constitués par des circuits de sommation pondérée de courants dans au moins deux colonnes de produits partiels à la fois.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7803547A FR2417139A1 (fr) | 1978-02-08 | 1978-02-08 | Multiplieur-sommateur perfectionne |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7803547A FR2417139A1 (fr) | 1978-02-08 | 1978-02-08 | Multiplieur-sommateur perfectionne |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2417139A1 true FR2417139A1 (fr) | 1979-09-07 |
FR2417139B3 FR2417139B3 (fr) | 1980-04-11 |
Family
ID=9204357
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7803547A Granted FR2417139A1 (fr) | 1978-02-08 | 1978-02-08 | Multiplieur-sommateur perfectionne |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2417139A1 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2560409A1 (fr) * | 1984-02-28 | 1985-08-30 | Lardy Jean Louis | Unite arithmetique pour additionner des bits paralleles |
FR2599528A1 (fr) * | 1986-05-29 | 1987-12-04 | Centre Nat Rech Scient | Additionneur bipolaire et multiplieur binaire bipolaire comprenant au moins un tel additionneur |
-
1978
- 1978-02-08 FR FR7803547A patent/FR2417139A1/fr active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2560409A1 (fr) * | 1984-02-28 | 1985-08-30 | Lardy Jean Louis | Unite arithmetique pour additionner des bits paralleles |
FR2599528A1 (fr) * | 1986-05-29 | 1987-12-04 | Centre Nat Rech Scient | Additionneur bipolaire et multiplieur binaire bipolaire comprenant au moins un tel additionneur |
Also Published As
Publication number | Publication date |
---|---|
FR2417139B3 (fr) | 1980-04-11 |
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