JPS6478322A - Multi-input adder - Google Patents
Multi-input adderInfo
- Publication number
- JPS6478322A JPS6478322A JP23365387A JP23365387A JPS6478322A JP S6478322 A JPS6478322 A JP S6478322A JP 23365387 A JP23365387 A JP 23365387A JP 23365387 A JP23365387 A JP 23365387A JP S6478322 A JPS6478322 A JP S6478322A
- Authority
- JP
- Japan
- Prior art keywords
- adder
- train
- addition
- data
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To simplify the circuit constitution of a multi-input adder by adding in parallel and simultaneously all data stored in each digit to perform the carry processing for each digit so that the adding time is approximately constant together with the reduction of the number of stages of an adder train despite the increase of the number of digits. CONSTITUTION:The adder trains 1 and 2 are successively connected with plural stages in response to the number of pieces of addition data and an ordinary adder train 7 is connected to the final stage. Each adder train 1 contains plural 1-bit full adders in response to the bit length of the addition data. For instance, the 1-bit full adders 21-25 of the adder train 2 are all connected in parallel with each other and then connected to the corresponding 1-bit full adders 3 of the next stage. The second lower rank bit of the input data D4 corresponding to the addition output of a 1-bit full adder 12 of the preceding stage is supplied to the input of the adder 22 together with a carry CR of a corresponding 1-bit full adder 11 of the preceding stage. Therefore the carries of each adder train are added simultaneously when the adder train of the next stage adds their addition results and the next data. In such a way, the number of addition processing steps is decreased and the arithmetic time is reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23365387A JPS6478322A (en) | 1987-09-19 | 1987-09-19 | Multi-input adder |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23365387A JPS6478322A (en) | 1987-09-19 | 1987-09-19 | Multi-input adder |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6478322A true JPS6478322A (en) | 1989-03-23 |
Family
ID=16958419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23365387A Pending JPS6478322A (en) | 1987-09-19 | 1987-09-19 | Multi-input adder |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6478322A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06149542A (en) * | 1992-05-27 | 1994-05-27 | Sgs Thomson Microelettronica Spa | Chaining and adding method for adder |
JPH06314186A (en) * | 1992-05-27 | 1994-11-08 | Sgs Thomson Microelettronica Spa | Adder chain and method for addition calculation |
JPH08139613A (en) * | 1994-11-15 | 1996-05-31 | Nec Corp | Code coincidence detecting system |
-
1987
- 1987-09-19 JP JP23365387A patent/JPS6478322A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06149542A (en) * | 1992-05-27 | 1994-05-27 | Sgs Thomson Microelettronica Spa | Chaining and adding method for adder |
JPH06314186A (en) * | 1992-05-27 | 1994-11-08 | Sgs Thomson Microelettronica Spa | Adder chain and method for addition calculation |
JPH08139613A (en) * | 1994-11-15 | 1996-05-31 | Nec Corp | Code coincidence detecting system |
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