JPS5542477A - Modulator for single-side-band frequency-division multiple signal - Google Patents

Modulator for single-side-band frequency-division multiple signal

Info

Publication number
JPS5542477A
JPS5542477A JP11679878A JP11679878A JPS5542477A JP S5542477 A JPS5542477 A JP S5542477A JP 11679878 A JP11679878 A JP 11679878A JP 11679878 A JP11679878 A JP 11679878A JP S5542477 A JPS5542477 A JP S5542477A
Authority
JP
Japan
Prior art keywords
number part
outputs
division multiple
real number
offset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11679878A
Other languages
Japanese (ja)
Other versions
JPS6021497B2 (en
Inventor
Rikio Maruta
Akira Kanemasa
Tomonori Aoyama
Fumio Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11679878A priority Critical patent/JPS6021497B2/en
Publication of JPS5542477A publication Critical patent/JPS5542477A/en
Publication of JPS6021497B2 publication Critical patent/JPS6021497B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H04J1/02—Details
    • H04J1/04—Frequency-transposition arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To reduce hardware in scale by reducing a multiplication value by performing an offset discrete Fourier process as to two units by using one offset discrete Fourier processing circuit and one synthesizer circuit. CONSTITUTION:The real number part ane imaginary number part of a N-channel base band signal inputted to input terminals 101 and 102 respectively are processed by offset Fourier processing circuit 10 and their real number part output and imaginary number part output are inputted to 1/2 multipliers 21 and 22. The outputs of multipliers 21 and 22 are processed by separator circuits consisting of N-1-word shift registers 31 and 32, array conversion memories 41 and 42, -1 multiplier 50, 2-1 selectors 61 and 62, adders 71 and 72, and subtracters 81 and 82, and from output terminals 301 and 302, and 401 and 402, the real number outputs and imaginary number outputs of two independent N-channel single side-band frequency-division multiple signals are led out.
JP11679878A 1978-09-21 1978-09-21 Single sideband frequency division multiplexing signal modulator Expired JPS6021497B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11679878A JPS6021497B2 (en) 1978-09-21 1978-09-21 Single sideband frequency division multiplexing signal modulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11679878A JPS6021497B2 (en) 1978-09-21 1978-09-21 Single sideband frequency division multiplexing signal modulator

Publications (2)

Publication Number Publication Date
JPS5542477A true JPS5542477A (en) 1980-03-25
JPS6021497B2 JPS6021497B2 (en) 1985-05-28

Family

ID=14695928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11679878A Expired JPS6021497B2 (en) 1978-09-21 1978-09-21 Single sideband frequency division multiplexing signal modulator

Country Status (1)

Country Link
JP (1) JPS6021497B2 (en)

Also Published As

Publication number Publication date
JPS6021497B2 (en) 1985-05-28

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Legal Events

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A621 Written request for application examination

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Effective date: 20041018

A762 Written abandonment of application

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Effective date: 20050915