JPS5542477A - Modulator for single-side-band frequency-division multiple signal - Google Patents
Modulator for single-side-band frequency-division multiple signalInfo
- Publication number
- JPS5542477A JPS5542477A JP11679878A JP11679878A JPS5542477A JP S5542477 A JPS5542477 A JP S5542477A JP 11679878 A JP11679878 A JP 11679878A JP 11679878 A JP11679878 A JP 11679878A JP S5542477 A JPS5542477 A JP S5542477A
- Authority
- JP
- Japan
- Prior art keywords
- number part
- outputs
- division multiple
- real number
- offset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J1/00—Frequency-division multiplex systems
- H04J1/02—Details
- H04J1/04—Frequency-transposition arrangements
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
Abstract
PURPOSE:To reduce hardware in scale by reducing a multiplication value by performing an offset discrete Fourier process as to two units by using one offset discrete Fourier processing circuit and one synthesizer circuit. CONSTITUTION:The real number part ane imaginary number part of a N-channel base band signal inputted to input terminals 101 and 102 respectively are processed by offset Fourier processing circuit 10 and their real number part output and imaginary number part output are inputted to 1/2 multipliers 21 and 22. The outputs of multipliers 21 and 22 are processed by separator circuits consisting of N-1-word shift registers 31 and 32, array conversion memories 41 and 42, -1 multiplier 50, 2-1 selectors 61 and 62, adders 71 and 72, and subtracters 81 and 82, and from output terminals 301 and 302, and 401 and 402, the real number outputs and imaginary number outputs of two independent N-channel single side-band frequency-division multiple signals are led out.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11679878A JPS6021497B2 (en) | 1978-09-21 | 1978-09-21 | Single sideband frequency division multiplexing signal modulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11679878A JPS6021497B2 (en) | 1978-09-21 | 1978-09-21 | Single sideband frequency division multiplexing signal modulator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5542477A true JPS5542477A (en) | 1980-03-25 |
JPS6021497B2 JPS6021497B2 (en) | 1985-05-28 |
Family
ID=14695928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11679878A Expired JPS6021497B2 (en) | 1978-09-21 | 1978-09-21 | Single sideband frequency division multiplexing signal modulator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6021497B2 (en) |
-
1978
- 1978-09-21 JP JP11679878A patent/JPS6021497B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6021497B2 (en) | 1985-05-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20041018 |
|
A762 | Written abandonment of application |
Free format text: JAPANESE INTERMEDIATE CODE: A762 Effective date: 20050915 |