FR2348544A1 - Ensemble double de memoire associative - Google Patents

Ensemble double de memoire associative

Info

Publication number
FR2348544A1
FR2348544A1 FR7611234A FR7611234A FR2348544A1 FR 2348544 A1 FR2348544 A1 FR 2348544A1 FR 7611234 A FR7611234 A FR 7611234A FR 7611234 A FR7611234 A FR 7611234A FR 2348544 A1 FR2348544 A1 FR 2348544A1
Authority
FR
France
Prior art keywords
double
associative memory
memory set
associative
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7611234A
Other languages
English (en)
Other versions
FR2348544B1 (fr
Inventor
Daniel Rene Vinot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Societe Industrielle Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Societe Industrielle Honeywell Bull filed Critical Societe Industrielle Honeywell Bull
Priority to FR7611234A priority Critical patent/FR2348544A1/fr
Priority to US05/785,233 priority patent/US4163288A/en
Publication of FR2348544A1 publication Critical patent/FR2348544A1/fr
Application granted granted Critical
Publication of FR2348544B1 publication Critical patent/FR2348544B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR7611234A 1976-04-15 1976-04-15 Ensemble double de memoire associative Granted FR2348544A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR7611234A FR2348544A1 (fr) 1976-04-15 1976-04-15 Ensemble double de memoire associative
US05/785,233 US4163288A (en) 1976-04-15 1977-04-06 Associative memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7611234A FR2348544A1 (fr) 1976-04-15 1976-04-15 Ensemble double de memoire associative

Publications (2)

Publication Number Publication Date
FR2348544A1 true FR2348544A1 (fr) 1977-11-10
FR2348544B1 FR2348544B1 (fr) 1979-01-12

Family

ID=9171912

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7611234A Granted FR2348544A1 (fr) 1976-04-15 1976-04-15 Ensemble double de memoire associative

Country Status (2)

Country Link
US (1) US4163288A (fr)
FR (1) FR2348544A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0255186A2 (fr) * 1986-07-30 1988-02-03 Egendorf, Andrew Système et procédé de traitement parallèle avec des langages essentiellement fonctionnels

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4257110A (en) * 1977-04-19 1981-03-17 Semionics Associates, Inc. Recognition memory with multiwrite and masking
US4384343A (en) * 1979-02-12 1983-05-17 Honeywell Information Systems Inc. Firmware controlled search and verify apparatus and method for a data processing system
JPS6032254B2 (ja) * 1979-06-05 1985-07-26 松下電器産業株式会社 磁気記録再生装置
US4376974A (en) * 1980-03-31 1983-03-15 Ncr Corporation Associative memory system
JPS58102381A (ja) * 1981-12-15 1983-06-17 Nec Corp バツフアメモリ
JPS60142451A (ja) * 1983-12-29 1985-07-27 Fujitsu Ltd アドレス変換制御方式
US5485418A (en) * 1990-01-16 1996-01-16 Mitsubishi Denki Kabushiki Kaisha Associative memory
US5446686A (en) * 1994-08-02 1995-08-29 Sun Microsystems, Inc. Method and appartus for detecting multiple address matches in a content addressable memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2072038A1 (fr) * 1969-12-24 1971-09-24 Ibm

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
US3588839A (en) * 1969-01-15 1971-06-28 Ibm Hierarchical memory updating system
US3602899A (en) * 1969-06-20 1971-08-31 Ibm Associative memory system with match,no match and multiple match resolution
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
US3958225A (en) * 1974-01-28 1976-05-18 Teletype Corporation Apparatus and method for controlling a communications terminal
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2072038A1 (fr) * 1969-12-24 1971-09-24 Ibm

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PAGES 1317 ET 1318, ARTICLE: "MEMORY WITH COMPARE FUNCTION IN SENSE AMPLIFIER STAGE" BIDWELL ) *
PUBLICATION US: "IBM TECHNICAL DISCLOSURE BULLETIN", VOLUME 13, NO. 5, OCTOBRE 1970 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0255186A2 (fr) * 1986-07-30 1988-02-03 Egendorf, Andrew Système et procédé de traitement parallèle avec des langages essentiellement fonctionnels
EP0255186A3 (fr) * 1986-07-30 1990-04-18 Egendorf, Andrew Système et procédé de traitement parallèle avec des langages essentiellement fonctionnels

Also Published As

Publication number Publication date
US4163288A (en) 1979-07-31
FR2348544B1 (fr) 1979-01-12

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