US4163288A - Associative memory - Google Patents

Associative memory Download PDF

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Publication number
US4163288A
US4163288A US05/785,233 US78523377A US4163288A US 4163288 A US4163288 A US 4163288A US 78523377 A US78523377 A US 78523377A US 4163288 A US4163288 A US 4163288A
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Prior art keywords
memory
input
data
associative
multiplexer
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US05/785,233
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Daniel Vinot
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INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL Cie SA
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INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL Cie SA
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means

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  • the present invention relates to an assembly for associative memories and to a high-performance circuit intended for multiprocessor systems having two hierarchically arranged memory levels.
  • associative memories as memory masks with multiprocessors creates problems from the point of view of the software which, in order to ensure the validity of the information contained in the memories, has constantly to update a validity bit associated with each addressed location in a circuit external to the memories.
  • the problem is all the more complicated because of the numerous write operations which are performed in the auxiliary memory and which may be initiated by any processor.
  • the management involved which is the responsibility of the software, takes time.
  • each address is transmitted simultaneously to all the masks of the system and a search is made. If the search is successful, the corresponding location is indicated as requiring invalidation.
  • the frequency of the invalidating operations increases with the number of processors. If a normal search operation and an invalidating operation cannot be performed simultaneously, priority is given to the invalidating function and this inevitably reduces the performance of the computer. This problem exists in particular in cases where a plurality of processors share the same auxiliary memory via a plurality of masks. If a processor performs a write operation at location Y in the auxiliary memory and if mask O has a copy of this location Y, this copy becomes out of date and thus incorrect and needs to be invalidated.
  • the arrangement which is the subject of the present invention allows simultaneous and independent searches for a local user and for a possible invalidation. It prevents any interference between normal running and the invalidation function as used in the specification, the term "normal” is not an invalidation mode and is used to distinguish between an invalidation mode and a normal processing running mode.
  • the circuit which is the subject of the invention is characterised by the fact that it comprises two association assemblies for a single read/write memory assembly a first assembly comparing the content of the data descriptor word with the words read from the first associative memory assembly and a second assembly comparing the content of the words read from the associative memory to a data descriptor word corresponding to the memory word to be invalidated.
  • FIG. 1 is a general diagram of a double associative memory assembly according to the invention
  • FIG. 2 is a detailed diagram of an embodiment of the double associative memory.
  • the associative memory shown in FIG. 1 contains four memory levels, each level consisting of memory elements of equal capacity which are identified by the numbers 101 to 104, corresponding to the order of the levels from 0 to 3.
  • all the memory levels are addressed by the address word which has to be invalidated whereas in a normal mode, only one memory level is addressed by the address of the word which has to be written or read in said memory level.
  • the address of the word to be invalidated is represented in the Figure by the letters A2 to A6 and this address is applied to point A.
  • the address of the normal word is represented by letters B2 to B6 and is applied to point B.
  • Data description words are placed on lines I0 to IP and J0 to JP.
  • the address A0 to A6 comprises a first bit zone A0 and A1 representing the selection of one of the four memory levels, and a zone extending from A2 to A6 representing an address within a level.
  • the address B2 to B6 is applied simultaneously to all the levels.
  • the selection of the read or write mode is performed by means of the line WE which is connected to point W.
  • the items of data I0 to IP to be written in the normal mode are applied to points N on each level.
  • SA and SB are the outlet points for the memory words from each level when they are addressed by address words A2 to A6 and B2 to B6 respectively.
  • the search is made by means of address A2 to A6, which addresses all the levels simultaneously, and the words read from each level appear at outputs SA and are compared with the data word J0 to Jp to be invalidated by means of four comparators 109 to 112, whose outputs are indicated by the letters P4 to P7.
  • address A2 to A6 addresses all the levels simultaneously
  • the words read from each level appear at outputs SA and are compared with the data word J0 to Jp to be invalidated by means of four comparators 109 to 112, whose outputs are indicated by the letters P4 to P7.
  • the outputs SA from each level of the memory as well as the outputs of the comparators are multiplexed by means of a multiplexer 113, which is controlled by a signal RM applied to a multiplexer control signal input.
  • a signal RM applied to a multiplexer control signal input.
  • input A Connected to input A are two control conductors which transmit the bits A0 and A1 of the address word which select a memory level.
  • the multiplexed inputs are indicated by ⁇ , ⁇ , ⁇ , ⁇ , ⁇ .
  • Input ⁇ is connected to output SA of level 0 101
  • input ⁇ is connected to output SA of level 1 102
  • input ⁇ is connected to output SA of level 2 103
  • input ⁇ is connected to output SA of level 3 104
  • input ⁇ is connected to outputs P0 to P7 of comparators 105 to 112.
  • inputs ⁇ , ⁇ , ⁇ and ⁇ collectively may be considered a first multiplexer data input
  • input ⁇ receiving the comparator outputs P0-P7 may be considered a second multiplexer data input.
  • the actual coupling of the comparator outputs P0-P7 to the input ⁇ is via at least one AND circuit, representative AND circuits being denoted 214 and 216 in FIG. 2.
  • RM 1 and only inputs ⁇ , ⁇ , ⁇ , ⁇ are selected by the address bits A0 and A1.
  • RM assumes the 0 state and input ⁇ is selected.
  • the output of the multiplexer is indicated by 9 and transmits a word which is marked Q0 to QP.
  • An address conflict may exist when there is an invalidating order and an operating order to the same level and to the same address.
  • the conflict will be reported by the combined outputs P0 to P7 of the comparators.
  • FIG. 2 shows in detail an embodiment of a memory.
  • Unit 2O consists of memory means 202 to 205 corresponding respectively to levels 0, 1, 2 and 3 of the memory.
  • a memory mean is selected by means of outputs 1, 2, 3 and 4 of a decoder 201, which are connected respectively to the terminals 4 of memory means 202, 203, 204 and 205 and which emit signals ZS0, ZS1, ZS2 and ZS3 as dictated by the states which appear at the inputs 5 and 6 of the decoder.
  • the inputs 5 and 6 of decoder 201 are connected to the inputs A0 and A1 of the associative memory which receive the two bits (A0, A1) for addressing the memory levels in which the information has to be invalidated.
  • the inputs 1 of each memory means are connected to the five input terminals A2 to A6 of the associative memory which receive the address bits for the information to be invalidated within each level.
  • the inputs 2 of each memory means are connected to the five input terminals B2 to B6 of the double associative memory which receive the address bits for normal information.
  • the inputs 3 of each memory means are controlled by the write authorisation signal WE.
  • the inputs 5 of each memory means are connected together and receive bit I0 of the normal data descriptor.
  • the inputs 1 of the comparators 206, 208, 210 and 212 are connected together and receive bit I0 of the normal data descriptor.
  • the inputs 2 of the same comparators are connected to outputs S00, S10, S20 and S30 of memory means 202 to 205. These comparators emit from their outputs 3 signals K00, K10, K20 and K30, which thus represent a comparison on each level between bit 0 of the memory word and bit I0 of the data descriptor.
  • comparators 207, 209, 211 and 212 are connected respectively to outputs T00, T10, T20 and T30 of memory elements 202 to 205.
  • the inputs 2 of the same comparators are connected together and receive bit J0 of the descriptor for the word to be invalidated. These comparators emit from their outputs 3 signals L00, L10, L20 and L30, which thus represent a comparison on each level between bit 0 of the memory word and bit J0 of the descriptor for the data to be invalidated.
  • An AND circuit 214 receives at its inputs the signals K00, K01, . . . K08, and its output 10 emits the signal P0 when the content of the memory word on level 0 is identical with the content of the normal data descriptor.
  • the signals K01 to K08 are emitted by comparators identical to comparator 206 which are situated in memory units 21 to 2P respectively.
  • AND circuits whose operation is identical to that of AND circuit 214 are provided in the units 219, 220 and 221 shown in broken lines and emit signals P1, P2, and P3, the equations for which are:
  • And circuit 216 receives at its inputs signals L00, L01 . . . L08 and its output 10 emits signal P4 when the content of the memory word on level 0 is identical with the content of the descriptor for the data to be invalidated.
  • the signals L01 to L08 are emitted by comparators identical to comparators 207 which are situated in memory units 21 to 28 respectively.
  • AND circuits whose operation is identical to that of AND circuit 216 are provided in the units 219, 220 and 221 shown in broken lines and emit signals P5, P6 and P7 in accordance with the equations:
  • the succeeding multiplexers emit signals QI to QP.
  • the number of comparators required to recognise the normal data descriptor is equal to the number of memory levels multiplied by the number of memory units. This number is the same for the comparators for recognising the word to be invalidated.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
US05/785,233 1976-04-15 1977-04-06 Associative memory Expired - Lifetime US4163288A (en)

Applications Claiming Priority (2)

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FR7611234A FR2348544A1 (fr) 1976-04-15 1976-04-15 Ensemble double de memoire associative
FR7611234 1976-04-15

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4257110A (en) * 1977-04-19 1981-03-17 Semionics Associates, Inc. Recognition memory with multiwrite and masking
US4316225A (en) * 1979-06-05 1982-02-16 Matsushita Electric Industrial Co., Ltd. Rotary head assembly for magnetic recording and reproducing device
US4376974A (en) * 1980-03-31 1983-03-15 Ncr Corporation Associative memory system
US4384343A (en) * 1979-02-12 1983-05-17 Honeywell Information Systems Inc. Firmware controlled search and verify apparatus and method for a data processing system
EP0149389A2 (fr) * 1983-12-29 1985-07-24 Fujitsu Limited Système de commande de traduction d'adresse
US4580240A (en) * 1981-12-15 1986-04-01 Nippon Electric Co., Ltd. Memory arrangement operable as a cache and a local memory
US5446686A (en) * 1994-08-02 1995-08-29 Sun Microsystems, Inc. Method and appartus for detecting multiple address matches in a content addressable memory
US5485418A (en) * 1990-01-16 1996-01-16 Mitsubishi Denki Kabushiki Kaisha Associative memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825360A (en) * 1986-07-30 1989-04-25 Symbolics, Inc. System and method for parallel processing with mostly functional languages

Citations (8)

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US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
US3588839A (en) * 1969-01-15 1971-06-28 Ibm Hierarchical memory updating system
US3602899A (en) * 1969-06-20 1971-08-31 Ibm Associative memory system with match,no match and multiple match resolution
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
US3958225A (en) * 1974-01-28 1976-05-18 Teletype Corporation Apparatus and method for controlling a communications terminal
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3644906A (en) * 1969-12-24 1972-02-22 Ibm Hybrid associative memory

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
US3588839A (en) * 1969-01-15 1971-06-28 Ibm Hierarchical memory updating system
US3602899A (en) * 1969-06-20 1971-08-31 Ibm Associative memory system with match,no match and multiple match resolution
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
US3781808A (en) * 1972-10-17 1973-12-25 Ibm Virtual memory system
US3958225A (en) * 1974-01-28 1976-05-18 Teletype Corporation Apparatus and method for controlling a communications terminal
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4257110A (en) * 1977-04-19 1981-03-17 Semionics Associates, Inc. Recognition memory with multiwrite and masking
US4384343A (en) * 1979-02-12 1983-05-17 Honeywell Information Systems Inc. Firmware controlled search and verify apparatus and method for a data processing system
US4316225A (en) * 1979-06-05 1982-02-16 Matsushita Electric Industrial Co., Ltd. Rotary head assembly for magnetic recording and reproducing device
US4376974A (en) * 1980-03-31 1983-03-15 Ncr Corporation Associative memory system
US4580240A (en) * 1981-12-15 1986-04-01 Nippon Electric Co., Ltd. Memory arrangement operable as a cache and a local memory
EP0149389A2 (fr) * 1983-12-29 1985-07-24 Fujitsu Limited Système de commande de traduction d'adresse
EP0149389A3 (en) * 1983-12-29 1987-05-20 Fujitsu Limited Address translation control system
US4733350A (en) * 1983-12-29 1988-03-22 Fujitsu Limited Improved purge arrangement for an address translation control system
US5485418A (en) * 1990-01-16 1996-01-16 Mitsubishi Denki Kabushiki Kaisha Associative memory
US5446686A (en) * 1994-08-02 1995-08-29 Sun Microsystems, Inc. Method and appartus for detecting multiple address matches in a content addressable memory

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FR2348544B1 (fr) 1979-01-12
FR2348544A1 (fr) 1977-11-10

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