FR2304178A1 - Montage integre a semi-conducteurs - Google Patents
Montage integre a semi-conducteursInfo
- Publication number
- FR2304178A1 FR2304178A1 FR7606664A FR7606664A FR2304178A1 FR 2304178 A1 FR2304178 A1 FR 2304178A1 FR 7606664 A FR7606664 A FR 7606664A FR 7606664 A FR7606664 A FR 7606664A FR 2304178 A1 FR2304178 A1 FR 2304178A1
- Authority
- FR
- France
- Prior art keywords
- integrated semiconductor
- semiconductor mounting
- mounting
- integrated
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2510593A DE2510593C3 (de) | 1975-03-11 | 1975-03-11 | Integrierte Halbleiter-Schaltungsanordnung |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2304178A1 true FR2304178A1 (fr) | 1976-10-08 |
FR2304178B1 FR2304178B1 (fr) | 1982-10-08 |
Family
ID=5941047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7606664A Granted FR2304178A1 (fr) | 1975-03-11 | 1976-03-09 | Montage integre a semi-conducteurs |
Country Status (7)
Country | Link |
---|---|
US (1) | US4323913A (fr) |
JP (1) | JPS51113475A (fr) |
CA (1) | CA1055619A (fr) |
DE (1) | DE2510593C3 (fr) |
FR (1) | FR2304178A1 (fr) |
GB (1) | GB1514624A (fr) |
IT (1) | IT1056855B (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3144920A1 (de) * | 1981-11-12 | 1983-05-26 | Krauss-Maffei AG, 8000 München | Mischkopf |
EP0090111A2 (fr) * | 1982-03-31 | 1983-10-05 | Kabushiki Kaisha Toshiba | Procédé pour la fabrication d'un dispositif semi-conducteur comportant des régions d'isolation diélectriques |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51113578A (en) * | 1975-03-31 | 1976-10-06 | Hitachi Ltd | Semi-conductor elements |
JPS6057707B2 (ja) * | 1978-01-25 | 1985-12-16 | 株式会社日立製作所 | 記憶回路 |
EP0029350B1 (fr) * | 1979-11-14 | 1987-08-05 | Fujitsu Limited | Transistor de sortie d'un dispositif TTL comportant des moyens pour décharger des porteurs |
JPS5829628B2 (ja) * | 1979-11-22 | 1983-06-23 | 富士通株式会社 | 半導体記憶装置 |
US4432008A (en) * | 1980-07-21 | 1984-02-14 | The Board Of Trustees Of The Leland Stanford Junior University | Gold-doped IC resistor region |
US4419150A (en) * | 1980-12-29 | 1983-12-06 | Rockwell International Corporation | Method of forming lateral bipolar transistors |
US4466180A (en) * | 1981-06-25 | 1984-08-21 | Rockwell International Corporation | Method of manufacturing punch through voltage regulator diodes utilizing shaping and selective doping |
JPS588514U (ja) * | 1981-07-10 | 1983-01-20 | 東芝タンガロイ株式会社 | ボ−ルエンドミル |
JPS5812350A (ja) * | 1981-07-16 | 1983-01-24 | Nec Corp | 半導体集積回路装置 |
JPS6039415U (ja) * | 1983-08-23 | 1985-03-19 | 東芝タンガロイ株式会社 | スロ−アウエイ式のエンドミル |
JPS60117613A (ja) * | 1983-11-30 | 1985-06-25 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS62230051A (ja) * | 1986-03-31 | 1987-10-08 | Nec Corp | トランジスタ |
US5095348A (en) * | 1989-10-02 | 1992-03-10 | Texas Instruments Incorporated | Semiconductor on insulator transistor |
US7084483B2 (en) * | 2004-05-25 | 2006-08-01 | International Business Machines Corporation | Trench type buried on-chip precision programmable resistor |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2132347A1 (fr) * | 1971-04-03 | 1972-11-17 | Philips Nv |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1774929C3 (de) * | 1968-03-01 | 1975-09-04 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithische Speicherzelle mit zwei kreuzgekoppelten Transistoren |
US3631311A (en) * | 1968-03-26 | 1971-12-28 | Telefunken Patent | Semiconductor circuit arrangement with integrated base leakage resistance |
US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
NL161301C (nl) * | 1972-12-29 | 1980-01-15 | Philips Nv | Halfgeleiderinrichting en werkwijze voor de vervaar- diging daarvan. |
US3962717A (en) * | 1974-10-29 | 1976-06-08 | Fairchild Camera And Instrument Corporation | Oxide isolated integrated injection logic with selective guard ring |
-
1975
- 1975-03-11 DE DE2510593A patent/DE2510593C3/de not_active Expired
-
1976
- 1976-02-13 GB GB5684/76A patent/GB1514624A/en not_active Expired
- 1976-02-27 CA CA246,721A patent/CA1055619A/fr not_active Expired
- 1976-03-04 IT IT20832/76A patent/IT1056855B/it active
- 1976-03-09 FR FR7606664A patent/FR2304178A1/fr active Granted
- 1976-03-10 JP JP51026014A patent/JPS51113475A/ja active Granted
-
1979
- 1979-10-17 US US06/085,735 patent/US4323913A/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2132347A1 (fr) * | 1971-04-03 | 1972-11-17 | Philips Nv |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3144920A1 (de) * | 1981-11-12 | 1983-05-26 | Krauss-Maffei AG, 8000 München | Mischkopf |
EP0090111A2 (fr) * | 1982-03-31 | 1983-10-05 | Kabushiki Kaisha Toshiba | Procédé pour la fabrication d'un dispositif semi-conducteur comportant des régions d'isolation diélectriques |
EP0090111A3 (en) * | 1982-03-31 | 1986-01-15 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device comprising a dielectric isolation region |
Also Published As
Publication number | Publication date |
---|---|
DE2510593B2 (de) | 1981-07-16 |
FR2304178B1 (fr) | 1982-10-08 |
JPS51113475A (en) | 1976-10-06 |
DE2510593C3 (de) | 1982-03-18 |
CA1055619A (fr) | 1979-05-29 |
US4323913A (en) | 1982-04-06 |
GB1514624A (en) | 1978-06-14 |
JPS5526620B2 (fr) | 1980-07-15 |
IT1056855B (it) | 1982-02-20 |
DE2510593A1 (de) | 1976-09-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |