FR2084903A5 - - Google Patents
Info
- Publication number
- FR2084903A5 FR2084903A5 FR7109753A FR7109753A FR2084903A5 FR 2084903 A5 FR2084903 A5 FR 2084903A5 FR 7109753 A FR7109753 A FR 7109753A FR 7109753 A FR7109753 A FR 7109753A FR 2084903 A5 FR2084903 A5 FR 2084903A5
- Authority
- FR
- France
- Prior art keywords
- memory
- low speed
- word
- read
- memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
- G11B5/09—Digital recording
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US21040A US3609665A (en) | 1970-03-19 | 1970-03-19 | Apparatus for exchanging information between a high-speed memory and a low-speed memory |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2084903A5 true FR2084903A5 (fr) | 1971-12-17 |
Family
ID=21801985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7109753A Expired FR2084903A5 (fr) | 1970-03-19 | 1971-03-19 |
Country Status (7)
Country | Link |
---|---|
US (1) | US3609665A (fr) |
JP (1) | JPS4830168B2 (fr) |
BE (1) | BE763887A (fr) |
DE (1) | DE2111642C3 (fr) |
FR (1) | FR2084903A5 (fr) |
GB (1) | GB1310467A (fr) |
NL (1) | NL156262B (fr) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3806880A (en) * | 1971-12-02 | 1974-04-23 | North American Rockwell | Multiplexing system for address decode logic |
US3806888A (en) * | 1972-12-04 | 1974-04-23 | Ibm | Hierarchial memory system |
US3866180A (en) * | 1973-04-02 | 1975-02-11 | Amdahl Corp | Having an instruction pipeline for concurrently processing a plurality of instructions |
US3987417A (en) * | 1974-10-07 | 1976-10-19 | Brunson Raymond D | Address memory system |
US4125877A (en) * | 1976-11-26 | 1978-11-14 | Motorola, Inc. | Dual port random access memory storage cell |
EP0019358B1 (fr) * | 1979-05-09 | 1984-07-11 | International Computers Limited | Système hiérarchique de mémorisation de données |
US4459662A (en) * | 1980-09-29 | 1984-07-10 | Texas Instruments Incorporated | Microcomputer having ROM mass memory for downloading main RAM memory with microcomputer instructions |
JPS60229111A (ja) * | 1984-04-26 | 1985-11-14 | Fanuc Ltd | 数値制御方式 |
EP0167959B1 (fr) * | 1984-07-02 | 1992-05-06 | Nec Corporation | Traitement pour registres de vecteur de calculateur |
JPS6261132A (ja) * | 1985-09-12 | 1987-03-17 | Fujitsu Ltd | デ−タ転送命令制御方式 |
JPS62230169A (ja) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | ワイプ波形選択装置 |
DE69430891T2 (de) * | 1993-04-16 | 2003-03-13 | Sony Corp., Tokio/Tokyo | Vorrichtung zur informationsaufnahme und -übertragung. |
CA2121852A1 (fr) * | 1993-04-29 | 1994-10-30 | Larry T. Jost | Maillage de disque et nappage de memoire souple au moyen d'une antememoire a souplesse accrue |
US6370614B1 (en) | 1999-01-26 | 2002-04-09 | Motive Power, Inc. | I/O cache with user configurable preload |
US6463509B1 (en) | 1999-01-26 | 2002-10-08 | Motive Power, Inc. | Preloading data in a cache memory according to user-specified preload criteria |
-
1970
- 1970-03-19 US US21040A patent/US3609665A/en not_active Expired - Lifetime
-
1971
- 1971-03-05 BE BE763887A patent/BE763887A/fr not_active IP Right Cessation
- 1971-03-11 DE DE2111642A patent/DE2111642C3/de not_active Expired
- 1971-03-17 NL NL7103580.A patent/NL156262B/xx not_active IP Right Cessation
- 1971-03-18 JP JP46014800A patent/JPS4830168B2/ja not_active Expired
- 1971-03-19 FR FR7109753A patent/FR2084903A5/fr not_active Expired
- 1971-04-19 GB GB2279371A patent/GB1310467A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
NL156262B (nl) | 1978-03-15 |
NL7103580A (fr) | 1971-09-21 |
BE763887A (fr) | 1971-08-02 |
JPS4830168B2 (fr) | 1973-09-18 |
GB1310467A (en) | 1973-03-21 |
JPS463005A (fr) | 1971-10-25 |
DE2111642A1 (de) | 1971-09-30 |
US3609665A (en) | 1971-09-28 |
DE2111642C3 (de) | 1974-05-22 |
DE2111642B2 (de) | 1973-10-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name | ||
TP | Transmission of property | ||
ST | Notification of lapse |