FI956099A - Menetelmä puolijohdelaitteen valmistamiseksi - Google Patents

Menetelmä puolijohdelaitteen valmistamiseksi Download PDF

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Publication number
FI956099A
FI956099A FI956099A FI956099A FI956099A FI 956099 A FI956099 A FI 956099A FI 956099 A FI956099 A FI 956099A FI 956099 A FI956099 A FI 956099A FI 956099 A FI956099 A FI 956099A
Authority
FI
Finland
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Application number
FI956099A
Other languages
English (en)
Swedish (sv)
Other versions
FI956099A0 (fi
Inventor
Kazuhiro Yoshida
Original Assignee
Murata Manufacturing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co filed Critical Murata Manufacturing Co
Publication of FI956099A0 publication Critical patent/FI956099A0/fi
Publication of FI956099A publication Critical patent/FI956099A/fi

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66848Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863Lateral single gate transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/10Lift-off masking
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
FI956099A 1994-12-20 1995-12-19 Menetelmä puolijohdelaitteen valmistamiseksi FI956099A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6317019A JPH08172102A (ja) 1994-12-20 1994-12-20 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
FI956099A0 FI956099A0 (fi) 1995-12-19
FI956099A true FI956099A (fi) 1996-06-21

Family

ID=18083517

Family Applications (1)

Application Number Title Priority Date Filing Date
FI956099A FI956099A (fi) 1994-12-20 1995-12-19 Menetelmä puolijohdelaitteen valmistamiseksi

Country Status (5)

Country Link
US (1) US5587328A (fi)
EP (1) EP0718877A3 (fi)
JP (1) JPH08172102A (fi)
KR (1) KR0163833B1 (fi)
FI (1) FI956099A (fi)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5940697A (en) * 1997-09-30 1999-08-17 Samsung Electronics Co., Ltd. T-gate MESFET process using dielectric film lift-off technique
US7435108B1 (en) 1999-07-30 2008-10-14 Formfactor, Inc. Variable width resilient conductive contact structures
US6713374B2 (en) * 1999-07-30 2004-03-30 Formfactor, Inc. Interconnect assemblies and methods
US6524937B1 (en) * 2000-08-23 2003-02-25 Tyco Electronics Corp. Selective T-gate process
ATE304220T1 (de) 2002-02-05 2005-09-15 Bernd E Dr Maile Verfahren zur herstellung einer t-förmigen elektrode
DE10340926A1 (de) * 2003-09-03 2005-03-31 Technische Universität Ilmenau Abteilung Forschungsförderung und Technologietransfer Verfahren zur Herstellung von elektronischen Bauelementen
CN100421217C (zh) * 2004-01-29 2008-09-24 罗姆及海斯电子材料有限公司 T栅的形成方法
US20060009038A1 (en) 2004-07-12 2006-01-12 International Business Machines Corporation Processing for overcoming extreme topography
KR20110133828A (ko) * 2010-06-07 2011-12-14 삼성전자주식회사 포토레지스트 패턴 형성 방법
JP2013258368A (ja) * 2012-06-14 2013-12-26 Toshiba Corp 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358891A (en) * 1979-06-22 1982-11-16 Burroughs Corporation Method of forming a metal semiconductor field effect transistor
US4567132A (en) * 1984-03-16 1986-01-28 International Business Machines Corporation Multi-level resist image reversal lithography process
KR920009718B1 (ko) * 1987-08-10 1992-10-22 스미도모덴기고오교오 가부시기가이샤 화합물반도체장치 및 그 제조방법
FR2646291B1 (fr) * 1989-04-21 1991-06-14 Thomson Hybrides Microondes Procede de realisation d'un transistor autoaligne
FR2663155B1 (fr) * 1990-06-12 1997-01-24 Thomson Composants Microondes Procede de realisation d'une grille de transistor.
JP2895634B2 (ja) * 1990-12-18 1999-05-24 沖電気工業株式会社 電界効果トランジスタの製造方法
US5288660A (en) * 1993-02-01 1994-02-22 Avantek, Inc. Method for forming self-aligned t-shaped transistor electrode
US5486483A (en) * 1994-09-27 1996-01-23 Trw Inc. Method of forming closely spaced metal electrodes in a semiconductor device

Also Published As

Publication number Publication date
KR0163833B1 (ko) 1999-02-01
EP0718877A2 (en) 1996-06-26
FI956099A0 (fi) 1995-12-19
EP0718877A3 (en) 1997-01-15
US5587328A (en) 1996-12-24
JPH08172102A (ja) 1996-07-02

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