ES8402954A1 - Unidad para tratamiento de informacion. - Google Patents

Unidad para tratamiento de informacion.

Info

Publication number
ES8402954A1
ES8402954A1 ES520203A ES520203A ES8402954A1 ES 8402954 A1 ES8402954 A1 ES 8402954A1 ES 520203 A ES520203 A ES 520203A ES 520203 A ES520203 A ES 520203A ES 8402954 A1 ES8402954 A1 ES 8402954A1
Authority
ES
Spain
Prior art keywords
instruction
data
processing unit
memory
information processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES520203A
Other languages
English (en)
Other versions
ES520203A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=12386450&utm_source=***_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ES8402954(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES8402954A1 publication Critical patent/ES8402954A1/es
Publication of ES520203A0 publication Critical patent/ES520203A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4494—Execution paradigms, e.g. implementations of programming paradigms data driven

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

UNIDAD PARA TRATAMIENTO DE INFORMACION.COMPRENDE: UNA MEMORIA DE INSTRUCCION (2) PARA ALMACENAR LAS INSTRUCCIONES; UNA MEMORIA DE DATOS (3) PARA ALMACENAR LOS DATOS OPERANTES; UNA PARTE DE BUSQUEDA DE INSTRUCCION (4, 5), PARA BUSCAR UNA O VARIAS INSTRUCCIONES EJECUTABLES DESDE LA MEMORIA DE INSTRUCCION; Y UNA UNIDAD DE OPERACION (7) PARA CARGAR LOS DATOS OPERANTES DESEADOS DESDE LA MEMORIA DE DATOS, PARA EJECUTAR LA INSTRUCCION O INSTRUCCIONES BUSCADAS, EN PARALELO.
ES520203A 1982-03-03 1983-03-01 Unidad para tratamiento de informacion. Granted ES520203A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57033435A JPS58151655A (ja) 1982-03-03 1982-03-03 情報処理装置

Publications (2)

Publication Number Publication Date
ES8402954A1 true ES8402954A1 (es) 1984-03-01
ES520203A0 ES520203A0 (es) 1984-03-01

Family

ID=12386450

Family Applications (1)

Application Number Title Priority Date Filing Date
ES520203A Granted ES520203A0 (es) 1982-03-03 1983-03-01 Unidad para tratamiento de informacion.

Country Status (7)

Country Link
US (1) US4675806A (es)
EP (1) EP0087978B1 (es)
JP (1) JPS58151655A (es)
BR (1) BR8301016A (es)
CA (1) CA1204516A (es)
DE (1) DE3379850D1 (es)
ES (1) ES520203A0 (es)

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USRE34052E (en) * 1984-05-31 1992-09-01 International Business Machines Corporation Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage
JP2539357B2 (ja) * 1985-03-15 1996-10-02 株式会社日立製作所 デ−タ処理装置
US5206945A (en) * 1985-03-15 1993-04-27 Hitachi, Ltd. Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses
US4972314A (en) * 1985-05-20 1990-11-20 Hughes Aircraft Company Data flow signal processor method and apparatus
JPH0632056B2 (ja) * 1985-05-31 1994-04-27 松下電器産業株式会社 デ−タ処理装置
JPH0766329B2 (ja) * 1985-06-14 1995-07-19 株式会社日立製作所 情報処理装置
US5349672A (en) * 1986-03-17 1994-09-20 Hitachi, Ltd. Data processor having logical address memories and purge capabilities
DE3751503T2 (de) * 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
US4814978A (en) * 1986-07-15 1989-03-21 Dataflow Computer Corporation Dataflow processing element, multiprocessor, and processes
US4980824A (en) * 1986-10-29 1990-12-25 United Technologies Corporation Event driven executive
US4811215A (en) * 1986-12-12 1989-03-07 Intergraph Corporation Instruction execution accelerator for a pipelined digital machine with virtual memory
US5001624A (en) * 1987-02-13 1991-03-19 Harrell Hoffman Processor controlled DMA controller for transferring instruction and data from memory to coprocessor
US4972315A (en) * 1987-03-10 1990-11-20 Mitsubishi Denki Kabushiki Kaisha Data flow machine
JPH0192851A (ja) * 1987-10-02 1989-04-12 Hitachi Ltd アドレス空間切替装置
JPH0646414B2 (ja) * 1987-10-20 1994-06-15 シャープ株式会社 情報処理装置
US5115510A (en) * 1987-10-20 1992-05-19 Sharp Kabushiki Kaisha Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
US5117499A (en) * 1988-01-22 1992-05-26 Sharp Kabushiki Kaisha Data flow type processing apparatus having external and cache memories for fetching paired executing instruction when mishit occurs
JPH06101044B2 (ja) * 1988-01-23 1994-12-12 シャープ株式会社 デッドロック回避実行制御方式
JPH01188951A (ja) * 1988-01-23 1989-07-28 Sharp Corp データフロープログラムの実行制御方式
US5125097A (en) * 1988-01-29 1992-06-23 Sharp Kabushiki Kaisha Data flow type information processors where data packets pass through plurality of merging and branching portions of the internal path
US4974146A (en) * 1988-05-06 1990-11-27 Science Applications International Corporation Array processor
US5513332A (en) * 1988-05-31 1996-04-30 Extended Systems, Inc. Database management coprocessor for on-the-fly providing data from disk media to all without first storing data in memory therebetween
WO1990001192A1 (en) * 1988-07-22 1990-02-08 United States Department Of Energy Data flow machine for data driven computing
US5163142A (en) * 1988-10-28 1992-11-10 Hewlett-Packard Company Efficient cache write technique through deferred tag modification
US5241635A (en) * 1988-11-18 1993-08-31 Massachusetts Institute Of Technology Tagged token data processing system with operand matching in activation frames
US5689647A (en) * 1989-03-14 1997-11-18 Sanyo Electric Co., Ltd. Parallel computing system with processing element number setting mode and shortest route determination with matrix size information
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5150470A (en) * 1989-12-20 1992-09-22 International Business Machines Corporation Data processing system with instruction queue having tags indicating outstanding data status
USRE35311E (en) * 1990-04-04 1996-08-06 International Business Machines Corporation Data dependency collapsing hardware apparatus
US5404553A (en) * 1991-01-09 1995-04-04 Mitsubishi Denki Kabushiki Kaisha Microprocessor and data flow microprocessor having vector operation function
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
WO1993001546A1 (en) 1991-07-08 1993-01-21 Seiko Epson Corporation Extensible risc microprocessor architecture
US5423040A (en) * 1991-07-24 1995-06-06 International Business Machines Corporation System and method for efficiently executing directed acyclic graphs
US5363495A (en) * 1991-08-26 1994-11-08 International Business Machines Corporation Data processing system with multiple execution units capable of executing instructions out of sequence
EP0544083A3 (en) * 1991-11-26 1994-09-14 Ibm Interleaved risc-type parallel processor and processing methods
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
WO1993020505A2 (en) 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
KR950701437A (ko) * 1992-05-01 1995-03-23 요시오 야마자끼 슈퍼스칼라 마이크로프로세서에서의 명령어 회수를 위한 시스템 및 방법
US5636150A (en) * 1992-08-06 1997-06-03 Sharp Kabushiki Kaisha Data driven type digital filter unit and data driven type information processor including the same
EP0663083B1 (en) * 1992-09-29 2000-12-20 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994016384A1 (en) 1992-12-31 1994-07-21 Seiko Epson Corporation System and method for register renaming
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
CA2123442A1 (en) * 1993-09-20 1995-03-21 David S. Ray Multiple execution unit dispatch with instruction dependency
US5765014A (en) * 1993-10-12 1998-06-09 Seki; Hajime Electronic computer system and processor element for processing in a data driven manner using reverse polish notation
GB2289664B (en) * 1994-05-27 1998-04-29 Instance Ltd David J Labels and manufacture thereof
US5826072A (en) * 1995-11-13 1998-10-20 Oasis Design, Inc. Pipelined digital signal processor and signal processing system employing same
US6092184A (en) * 1995-12-28 2000-07-18 Intel Corporation Parallel processing of pipelined instructions having register dependencies
US5974538A (en) * 1997-02-21 1999-10-26 Wilmot, Ii; Richard Byron Method and apparatus for annotating operands in a computer system with source instruction identifiers
RU2130198C1 (ru) * 1997-08-06 1999-05-10 Бурцев Всеволод Сергеевич Вычислительная машина
US6553483B1 (en) * 1999-11-29 2003-04-22 Intel Corporation Enhanced virtual renaming scheme and deadlock prevention therefor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7004570A (es) * 1970-03-31 1971-10-04
BE789583A (fr) * 1971-10-01 1973-02-01 Sanders Associates Inc Appareil de controle de programme pour machine de traitement del'information
GB1443777A (en) * 1973-07-19 1976-07-28 Int Computers Ltd Data processing apparatus
US4025771A (en) * 1974-03-25 1977-05-24 Hughes Aircraft Company Pipe line high speed signal processor
US3962706A (en) * 1974-03-29 1976-06-08 Massachusetts Institute Of Technology Data processing apparatus for highly parallel execution of stored programs
US4168523A (en) * 1975-11-07 1979-09-18 Ncr Corporation Data processor utilizing a two level microaddressing controller
US4153941A (en) * 1976-11-11 1979-05-08 Kearney & Trecker Corporation Timing circuit and method for controlling the operation of cyclical devices
US4366536A (en) * 1980-04-15 1982-12-28 National Semiconductor Corporation Modular digital computer system for storing and selecting data processing procedures and data

Also Published As

Publication number Publication date
US4675806A (en) 1987-06-23
EP0087978A2 (en) 1983-09-07
EP0087978A3 (en) 1985-07-31
CA1204516A (en) 1986-05-13
BR8301016A (pt) 1983-11-22
EP0087978B1 (en) 1989-05-10
DE3379850D1 (en) 1989-06-15
ES520203A0 (es) 1984-03-01
JPS58151655A (ja) 1983-09-08

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001