ES8302945A1 - Perfeccionamientos en conjuntos de memorias con entradas multiples. - Google Patents

Perfeccionamientos en conjuntos de memorias con entradas multiples.

Info

Publication number
ES8302945A1
ES8302945A1 ES511598A ES511598A ES8302945A1 ES 8302945 A1 ES8302945 A1 ES 8302945A1 ES 511598 A ES511598 A ES 511598A ES 511598 A ES511598 A ES 511598A ES 8302945 A1 ES8302945 A1 ES 8302945A1
Authority
ES
Spain
Prior art keywords
bit line
memory
memory array
multiport memory
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES511598A
Other languages
English (en)
Other versions
ES511598A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of ES511598A0 publication Critical patent/ES511598A0/es
Publication of ES8302945A1 publication Critical patent/ES8302945A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

CONJUNTOS DE MEMORIAS CON ENTRADAS MULTIPLES. COMPRENDE FUNDAMENTALMENTE UNA PLURALIDAD DE ELEMENTOS DE ALMACENAMIENTO EN MEMORIA Y UN PRIMER PAR DE LINEAS DE ACCESO ASOCIADAS A ELLOS. ESTAS LINEAS, PREVIAMENTE CARGADAS, PROPORCIONAN SEÑALES DE INTERROGACION A LOS ELEMENTOS DE ALMACENAMIENTO. ESTOS ELEMENTOS QUEDAN AISLADOS DE LAS PRIMERAS LINEAS DE ACCESO DURANTE EL INTERVALO DE CARGA PREVIA. LA RESPUESTA TIENE LUGAR EN UN INSTANTE INMEDIATAMENTE SIGUIENTE A LA CARGA. UN SEGUNDO PAR DE LINEAS DE ACCESO, PROPORCIONAN CARGA Y RESPUESTA INDEPENDIENTES.
ES511598A 1981-04-23 1982-04-22 Perfeccionamientos en conjuntos de memorias con entradas multiples. Expired ES8302945A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/256,697 US4395765A (en) 1981-04-23 1981-04-23 Multiport memory array

Publications (2)

Publication Number Publication Date
ES511598A0 ES511598A0 (es) 1983-02-16
ES8302945A1 true ES8302945A1 (es) 1983-02-16

Family

ID=22973231

Family Applications (1)

Application Number Title Priority Date Filing Date
ES511598A Expired ES8302945A1 (es) 1981-04-23 1982-04-22 Perfeccionamientos en conjuntos de memorias con entradas multiples.

Country Status (16)

Country Link
US (1) US4395765A (es)
JP (1) JPS57181493A (es)
AU (1) AU546325B2 (es)
BE (1) BE892929A (es)
CA (1) CA1173566A (es)
CH (1) CH654947A5 (es)
DE (1) DE3214230C2 (es)
ES (1) ES8302945A1 (es)
FR (1) FR2504714B1 (es)
GB (1) GB2097623B (es)
HK (1) HK7086A (es)
IE (1) IE53486B1 (es)
IL (1) IL65529A (es)
IT (1) IT1150876B (es)
NL (1) NL192755C (es)
SE (1) SE449672B (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
US4737933A (en) * 1983-02-22 1988-04-12 Storage Technology Partners CMOS multiport general purpose register
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
FR2595859B1 (fr) * 1986-03-14 1988-05-13 Radiotechnique Compelec Memoire avec tampon amplificateur
ATE89946T1 (de) * 1987-01-23 1993-06-15 Siemens Ag Halbleiterspeicher mit wahlfreiem zugriff ueber zwei getrennte ein/ausgaenge.
JPS63225836A (ja) * 1987-03-13 1988-09-20 Brother Ind Ltd 記憶装置
US5093807A (en) * 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
US5150328A (en) * 1988-10-25 1992-09-22 Internation Business Machines Corporation Memory organization with arrays having an alternate data port facility
US5166903A (en) * 1988-10-25 1992-11-24 International Business Machines Corporation Memory organization with arrays having an alternate data port facility
US4995001A (en) * 1988-10-31 1991-02-19 International Business Machines Corporation Memory cell and read circuit
US5235543A (en) * 1989-12-29 1993-08-10 Intel Corporation Dual port static memory with one cycle read-modify-write
US5708850A (en) * 1994-07-27 1998-01-13 Sony Corporation Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3618050A (en) * 1969-05-07 1971-11-02 Teletype Corp Read-only memory arrays in which a portion of the memory-addressing circuitry is integral to the array
US3636528A (en) * 1969-11-14 1972-01-18 Shell Oil Co Half-bit memory cell array with nondestructive readout
US3866180A (en) * 1973-04-02 1975-02-11 Amdahl Corp Having an instruction pipeline for concurrently processing a plurality of instructions
US3916394A (en) * 1974-12-09 1975-10-28 Honeywell Inf Systems High-speed random access memory
US3978459A (en) * 1975-04-21 1976-08-31 Intel Corporation High density mos memory array
US4051358A (en) * 1976-02-20 1977-09-27 Intel Corporation Apparatus and method for composing digital information on a data bus
JPS52129337A (en) * 1976-04-23 1977-10-29 Hitachi Ltd Memory circuit
US4104719A (en) * 1976-05-20 1978-08-01 The United States Of America As Represented By The Secretary Of The Navy Multi-access memory module for data processing systems
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
US4123799A (en) * 1977-09-19 1978-10-31 Motorola, Inc. High speed IFGET sense amplifier/latch
US4209851A (en) * 1978-07-19 1980-06-24 Texas Instruments Incorporated Semiconductor memory cell with clocked voltage supply from data lines
EP0011375A1 (en) * 1978-11-17 1980-05-28 Motorola, Inc. Multi-port ram structure for data processor registers
JPS5634179A (en) * 1979-08-24 1981-04-06 Mitsubishi Electric Corp Control circuit for memory unit

Also Published As

Publication number Publication date
CH654947A5 (de) 1986-03-14
US4395765A (en) 1983-07-26
AU546325B2 (en) 1985-08-29
IE53486B1 (en) 1988-11-23
BE892929A (fr) 1982-08-16
IL65529A (en) 1985-05-31
SE449672B (sv) 1987-05-11
IT8220885A0 (it) 1982-04-22
IE820949L (en) 1982-10-23
GB2097623A (en) 1982-11-03
NL192755B (nl) 1997-09-01
DE3214230A1 (de) 1982-11-18
NL192755C (nl) 1998-01-06
FR2504714A1 (fr) 1982-10-29
NL8201680A (nl) 1982-11-16
SE8202234L (sv) 1982-10-24
HK7086A (en) 1986-02-07
GB2097623B (en) 1984-09-26
AU8293282A (en) 1982-10-28
CA1173566A (en) 1984-08-28
DE3214230C2 (de) 1994-01-13
ES511598A0 (es) 1983-02-16
IL65529A0 (en) 1982-07-30
FR2504714B1 (fr) 1989-04-28
IT1150876B (it) 1986-12-17
JPS57181493A (en) 1982-11-08

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