ES538881A0 - Un dispositivo generador de refresco para una memoria de acceso aleatorio dinamica en una instalacion de tratamiento de datos - Google Patents

Un dispositivo generador de refresco para una memoria de acceso aleatorio dinamica en una instalacion de tratamiento de datos

Info

Publication number
ES538881A0
ES538881A0 ES538881A ES538881A ES538881A0 ES 538881 A0 ES538881 A0 ES 538881A0 ES 538881 A ES538881 A ES 538881A ES 538881 A ES538881 A ES 538881A ES 538881 A0 ES538881 A0 ES 538881A0
Authority
ES
Spain
Prior art keywords
signal
refresh
circuit
memory
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES538881A
Other languages
English (en)
Other versions
ES8602321A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES8602321A1 publication Critical patent/ES8602321A1/es
Publication of ES538881A0 publication Critical patent/ES538881A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Transmitters (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Bidet-Like Cleaning Device And Other Flush Toilet Accessories (AREA)
  • Superstructure Of Vehicle (AREA)
  • Air Bags (AREA)
  • Control Of Eletrric Generators (AREA)
ES538881A 1984-02-27 1984-12-20 Un dispositivo generador de refresco para una memoria de acceso aleatorio dinamica en una instalacion de tratamiento de datos Granted ES538881A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/584,032 US4575826A (en) 1984-02-27 1984-02-27 Refresh generator system for a dynamic memory

Publications (2)

Publication Number Publication Date
ES8602321A1 ES8602321A1 (es) 1985-11-01
ES538881A0 true ES538881A0 (es) 1985-11-01

Family

ID=24335623

Family Applications (1)

Application Number Title Priority Date Filing Date
ES538881A Granted ES538881A0 (es) 1984-02-27 1984-12-20 Un dispositivo generador de refresco para una memoria de acceso aleatorio dinamica en una instalacion de tratamiento de datos

Country Status (14)

Country Link
US (1) US4575826A (es)
EP (1) EP0153469B1 (es)
JP (1) JPS60182598A (es)
KR (1) KR890001311B1 (es)
AT (1) ATE43194T1 (es)
BR (1) BR8500629A (es)
CA (1) CA1211857A (es)
DE (1) DE3478258D1 (es)
ES (1) ES538881A0 (es)
GB (1) GB8431255D0 (es)
HK (1) HK102489A (es)
MX (1) MX158687A (es)
PH (1) PH23949A (es)
ZA (1) ZA85181B (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4723204A (en) * 1982-07-07 1988-02-02 Gte Automatic Electric Incorporated Dynamic RAM refresh circuit
JPS621187A (ja) * 1985-06-26 1987-01-07 Toshiba Corp ダイナミツクメモリのアクセス制御方式
US4754425A (en) * 1985-10-18 1988-06-28 Gte Communication Systems Corporation Dynamic random access memory refresh circuit selectively adapted to different clock frequencies
JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
JPH02166692A (ja) * 1988-12-20 1990-06-27 Sanyo Electric Co Ltd ダイナミツクメモリのリフレツシユ方法
US5060138A (en) * 1990-08-31 1991-10-22 Advanced Micro Devices, Inc. Apparatus for use with a computing device for generating a substitute acknowledgement to an input when the computing device is in an operational hiatus
US5940851A (en) * 1996-11-27 1999-08-17 Monolithic Systems, Inc. Method and apparatus for DRAM refresh using master, slave and self-refresh modes
US6262937B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Synchronous random access memory having a read/write address bus and process for writing to and reading from the same
US6262936B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Random access memory having independent read port and write port and process for writing to and reading from the same
US6069839A (en) * 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4332008A (en) * 1976-03-09 1982-05-25 Zilog, Inc. Microprocessor apparatus and method
JPS5694580A (en) * 1979-12-27 1981-07-31 Fujitsu Ltd Direct memory access control device
JPS5760588A (en) * 1980-09-26 1982-04-12 Toshiba Corp Memory controller
US4556952A (en) * 1981-08-12 1985-12-03 International Business Machines Corporation Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
JPS58215789A (ja) * 1982-06-07 1983-12-15 Hitachi Ltd ダイナミツクｒａｍのリフレツシユ回路
JPS60151894A (ja) * 1984-01-20 1985-08-09 Hitachi Ltd ダイナミツクｒａｍのリフレツシユ回路

Also Published As

Publication number Publication date
ATE43194T1 (de) 1989-06-15
BR8500629A (pt) 1985-10-01
HK102489A (en) 1990-01-05
EP0153469B1 (en) 1989-05-17
KR890001311B1 (ko) 1989-04-29
MX158687A (es) 1989-02-27
EP0153469A3 (en) 1986-12-03
ZA85181B (en) 1985-10-30
US4575826A (en) 1986-03-11
DE3478258D1 (en) 1989-06-22
KR860002251A (ko) 1986-04-24
EP0153469A2 (en) 1985-09-04
GB8431255D0 (en) 1985-01-23
US4575826B1 (es) 1990-02-06
PH23949A (en) 1990-01-23
CA1211857A (en) 1986-09-23
JPS60182598A (ja) 1985-09-18
ES8602321A1 (es) 1985-11-01

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20000601