ES2075045T3 - Aparato y metodo para acceder a una memoria en modo pagina en un sistema informatico. - Google Patents

Aparato y metodo para acceder a una memoria en modo pagina en un sistema informatico.

Info

Publication number
ES2075045T3
ES2075045T3 ES89302136T ES89302136T ES2075045T3 ES 2075045 T3 ES2075045 T3 ES 2075045T3 ES 89302136 T ES89302136 T ES 89302136T ES 89302136 T ES89302136 T ES 89302136T ES 2075045 T3 ES2075045 T3 ES 2075045T3
Authority
ES
Spain
Prior art keywords
memory
cas
memory cycle
column address
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89302136T
Other languages
English (en)
Inventor
Patrick Maurice Bland
Mark Edward Dean
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2075045T3 publication Critical patent/ES2075045T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Hardware Redundancy (AREA)
  • Memory System (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Bus Control (AREA)

Abstract

UN COMPUTADOR INCLUYE UNA PAGINA DE MEMORIA EN LA CUAL UNA DIRECCION DE FILA ACOMPAÑADA POR UNA SELECCION DE DIRECCION DE FILA (RAS) ES SEGUIDA POR UNA DIRECCION DE COLUMNA ACOMPAÑADA POR UN SELECCION DE DIRECCION DE COLUMNA (CAS) PARA LEER DATOS DE UNA POSICION DE MEMORIA DURANTE UN CICLO DE MEMORIA. CUANDO, EN UN CICLO DE MEMORIA SIGUIENTE, HAY QUE ACCEDER A OTRA POSICION DE LA MISMA PAGINA, LA DIRECCION DE FIJA Y LA RAS PERMANECEN CONSTANTES Y SE UTILIZA UNA NUEVA DIRECCION DE COLUMNA CON LA CAS QUE ES PRECARGADA CONMUTANDOLA A SU ESTADO DE APAGADA Y LUEGO VOLVIENDO A ENCENDERLA. ESTO SE REALIZA NORMALMENTE AL INICIO DEL SIGUIENTE CICLO DE MEMORIA. EN EL PRESENTE SISTEMA, LOS DATO SON LEIDOS Y ENGANCHADOS POCO DESPUES DE LA LLEGADA DE LA DIRECCION DE COLUMNA Y DE LA CAS AL PRIMERO DE LOS CICLOS DE MEMORIA DE FORMA QUE LA RECARGA DE LA CAS PUEDE TENER LUGAR AL FINAL DEL PRIMER CICLO DE MEMORIA Y ANTES DEL INICIO DEL SIGUIENTE CICLO DE MEMORIA.
ES89302136T 1988-05-26 1989-03-03 Aparato y metodo para acceder a una memoria en modo pagina en un sistema informatico. Expired - Lifetime ES2075045T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/196,721 US5034917A (en) 1988-05-26 1988-05-26 Computer system including a page mode memory with decreased access time and method of operation thereof

Publications (1)

Publication Number Publication Date
ES2075045T3 true ES2075045T3 (es) 1995-10-01

Family

ID=22726583

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89302136T Expired - Lifetime ES2075045T3 (es) 1988-05-26 1989-03-03 Aparato y metodo para acceder a una memoria en modo pagina en un sistema informatico.

Country Status (24)

Country Link
US (1) US5034917A (es)
EP (1) EP0343769B1 (es)
JP (1) JPH06101225B2 (es)
KR (1) KR920010950B1 (es)
CN (1) CN1010809B (es)
AT (1) ATE125058T1 (es)
BE (1) BE1003816A4 (es)
BR (1) BR8902399A (es)
CA (1) CA1319201C (es)
DE (2) DE68923403T2 (es)
DK (1) DK189589A (es)
ES (1) ES2075045T3 (es)
FI (1) FI95971C (es)
GB (1) GB2219418A (es)
HK (1) HK23896A (es)
IT (1) IT1230189B (es)
MX (1) MX167244B (es)
MY (1) MY104737A (es)
NL (1) NL8901237A (es)
NO (1) NO891581L (es)
NZ (1) NZ228610A (es)
PH (1) PH30402A (es)
PT (1) PT90631B (es)
SE (1) SE8901304L (es)

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JPH07248963A (ja) * 1994-03-08 1995-09-26 Nec Corp Ｄｒａｍ制御装置
JPH08314795A (ja) * 1994-05-19 1996-11-29 Hitachi Ltd 記憶装置の読み出し回路及び記憶システム
AU703750B2 (en) * 1994-10-14 1999-04-01 Compaq Computer Corporation Easily programmable memory controller which can access different speed memory devices on different cycles
US5701143A (en) * 1995-01-31 1997-12-23 Cirrus Logic, Inc. Circuits, systems and methods for improving row select speed in a row select memory device
USRE36532E (en) * 1995-03-02 2000-01-25 Samsung Electronics Co., Ltd. Synchronous semiconductor memory device having an auto-precharge function
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US5638534A (en) * 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
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CN113361683B (zh) * 2021-05-18 2023-01-10 山东师范大学 一种生物仿脑存储方法及***

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Also Published As

Publication number Publication date
NO891581D0 (no) 1989-04-18
CN1010809B (zh) 1990-12-12
FI891784A (fi) 1989-11-27
PT90631A (pt) 1989-11-30
KR920010950B1 (ko) 1992-12-24
MX167244B (es) 1993-03-11
FI891784A0 (fi) 1989-04-14
JPH06101225B2 (ja) 1994-12-12
FI95971B (fi) 1995-12-29
PT90631B (pt) 1994-10-31
CN1037983A (zh) 1989-12-13
DE68923403D1 (de) 1995-08-17
HK23896A (en) 1996-02-16
NO891581L (no) 1989-11-27
BR8902399A (pt) 1990-01-16
GB8904917D0 (en) 1989-04-12
KR890017611A (ko) 1989-12-16
PH30402A (en) 1997-05-08
DE3909896C2 (es) 1990-09-20
EP0343769A3 (en) 1992-04-29
GB2219418A (en) 1989-12-06
FI95971C (fi) 1996-04-10
DK189589D0 (da) 1989-04-19
CA1319201C (en) 1993-06-15
JPH0223591A (ja) 1990-01-25
NZ228610A (en) 1991-03-26
IT1230189B (it) 1991-10-18
ATE125058T1 (de) 1995-07-15
IT8920624A0 (it) 1989-05-24
DK189589A (da) 1989-11-27
MY104737A (en) 1994-05-31
EP0343769B1 (en) 1995-07-12
EP0343769A2 (en) 1989-11-29
DE3909896A1 (de) 1989-11-30
NL8901237A (nl) 1989-12-18
US5034917A (en) 1991-07-23
SE8901304D0 (sv) 1989-04-11
BE1003816A4 (fr) 1992-06-23
SE8901304L (sv) 1989-11-27
DE68923403T2 (de) 1996-03-07

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