ES2004078A6 - Sistema de tratamiento de datos, panel y subsistema de memoria para dicho sistema,y metodo de almacenar datos. - Google Patents

Sistema de tratamiento de datos, panel y subsistema de memoria para dicho sistema,y metodo de almacenar datos.

Info

Publication number
ES2004078A6
ES2004078A6 ES878700205A ES8700205A ES2004078A6 ES 2004078 A6 ES2004078 A6 ES 2004078A6 ES 878700205 A ES878700205 A ES 878700205A ES 8700205 A ES8700205 A ES 8700205A ES 2004078 A6 ES2004078 A6 ES 2004078A6
Authority
ES
Spain
Prior art keywords
array
activity
memory
arrays
logic signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES878700205A
Other languages
English (en)
Inventor
Paul J Natusch
Eugene L Yu
David C Senerchia
John F Herny
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of ES2004078A6 publication Critical patent/ES2004078A6/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)

Abstract

SISTEMA DE TRATAMIENTO DE DATOS, PANEL Y SUBSISTEMA DE MEMORIA PARA DICHO SISTEMA, Y METODO DE ALMACENAR DATOS, EN DONDE EL SISTEMA COMPRENDE UNA LINEA GENERAL, AL MENOS UNA UNIDAD DE TRATAMIENTO DE DATOS, UNA UNIDAD DE INTERFAZ DE MEMORIA Y CELDAS DE ALMACENAMIENTO DE DATOS. EL PANEL DE MEMORIA INCLUYE CONJUNTOS PARA ALMACENAR DATOS, SECUENCIADORES PARA CONTROLAR EL FUNCIONAMIENTO DE DICHOS CONJUNTOS Y UN INTERFAZ PARA APLICAR SEÑALES A DICHO SISTEMA. EL SUBSISTEMA DE MEMORIA INCLUYE UNA LINEA GENERAL, UN INTERFAZ PARA TRRANSFERIR SEÑALES A DICHO SISTEMA, AL MENOS UN PANEL DE MEMORIA, CONJUNTOS DE MEMORIA ACOPLADOS A DICHO PANEL Y MEDIOS DE CONTROL DE DICHOS PANELES. EL METODO COMPRENDE DISPONER CONJUNTOS DE SEMICONDUCTORES ACOPLADOS EN GRUPOS, ACOPLAR ESTOS A LA UNIDAD DE TRATAMIENTO Y ACTIVAR INDEPENDIENTEMENTE CADA GRUPO DE CONJUNTOS. EL INVENTO ES UTIL PARA CENTRALIZAR EL CONTROL DE MEMORIAS DE ORDENADORES.
ES878700205A 1986-01-29 1987-01-28 Sistema de tratamiento de datos, panel y subsistema de memoria para dicho sistema,y metodo de almacenar datos. Expired ES2004078A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US82368786A 1986-01-29 1986-01-29

Publications (1)

Publication Number Publication Date
ES2004078A6 true ES2004078A6 (es) 1988-12-01

Family

ID=25239418

Family Applications (1)

Application Number Title Priority Date Filing Date
ES878700205A Expired ES2004078A6 (es) 1986-01-29 1987-01-28 Sistema de tratamiento de datos, panel y subsistema de memoria para dicho sistema,y metodo de almacenar datos.

Country Status (12)

Country Link
EP (1) EP0288479B1 (es)
JP (1) JPH01501346A (es)
KR (1) KR910005379B1 (es)
CN (1) CN1007186B (es)
AU (1) AU6931087A (es)
CA (1) CA1286412C (es)
DE (1) DE3785191D1 (es)
ES (1) ES2004078A6 (es)
IL (1) IL81427A (es)
IN (1) IN170464B (es)
MX (1) MX168581B (es)
WO (1) WO1987004825A1 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1324679C (en) * 1989-02-03 1993-11-23 Michael A. Gagliardo Method and means for interfacing a system control unit for a multi-processor system with the system main memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343140A (en) * 1964-10-27 1967-09-19 Hughes Aircraft Co Banked memory system
DE2537787A1 (de) * 1975-08-25 1977-03-03 Computer Ges Konstanz Modularer arbeitsspeicher fuer eine datenverarbeitungsanlage und verfahren zum durchfuehren von speicherzugriffen an diesem speicher
US4245303A (en) * 1978-10-25 1981-01-13 Digital Equipment Corporation Memory for data processing system with command and data buffering
US4451880A (en) * 1980-10-31 1984-05-29 Honeywell Information Systems Inc. Memory controller with interleaved queuing apparatus
JPS58215777A (ja) * 1982-06-07 1983-12-15 Hitachi Ltd 記憶制御方式

Also Published As

Publication number Publication date
JPH01501346A (ja) 1989-05-11
IL81427A (en) 1991-06-10
IN170464B (es) 1992-03-28
CN87102176A (zh) 1987-09-02
EP0288479A1 (en) 1988-11-02
IL81427A0 (en) 1987-08-31
WO1987004825A1 (en) 1987-08-13
CA1286412C (en) 1991-07-16
KR910005379B1 (ko) 1991-07-29
EP0288479B1 (en) 1993-03-31
AU6931087A (en) 1987-08-25
KR880700973A (ko) 1988-04-13
CN1007186B (zh) 1990-03-14
MX168581B (es) 1993-06-01
DE3785191D1 (de) 1993-05-06

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19980401