EP3437138A1 - Vertikaler sic-mosfet - Google Patents
Vertikaler sic-mosfetInfo
- Publication number
- EP3437138A1 EP3437138A1 EP17703935.1A EP17703935A EP3437138A1 EP 3437138 A1 EP3437138 A1 EP 3437138A1 EP 17703935 A EP17703935 A EP 17703935A EP 3437138 A1 EP3437138 A1 EP 3437138A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- mosfet
- doping
- intermediate layer
- regions
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007704 transition Effects 0.000 claims description 24
- 230000005669 field effect Effects 0.000 claims description 23
- 239000002019 doping agent Substances 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 claims description 3
- 230000002441 reversible effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 136
- 229910010271 silicon carbide Inorganic materials 0.000 description 14
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 11
- 230000000903 blocking effect Effects 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000011161 development Methods 0.000 description 5
- 230000018109 developmental process Effects 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000007943 implant Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 241000264877 Hippospongia communis Species 0.000 description 2
- 102100024061 Integrator complex subunit 1 Human genes 0.000 description 2
- 101710092857 Integrator complex subunit 1 Proteins 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000000637 aluminium metallisation Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000004083 survival effect Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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Definitions
- the present invention relates to a vertical SiC-MOSFET, that is, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, German metal oxide-semiconductor field effect transistor), which is made of silicon carbide-based and whose elements are arranged predominantly vertically one above the other. In particular, the direction of current flow is also substantially vertically aligned.
- MOSFET Metal-Oxide-Semiconductor Field Effect Transistor, German metal oxide-semiconductor field effect transistor
- Semiconductor devices in particular power devices such as PowerMOSFETs, have various criteria to be optimized. For example, a high short-circuit strength, ie the survival of a short-circuit situation in the form of a load-free operation without damage is desirable. Similarly, generally low values for Rdson, that is, the drain-to-source resistance in the on-state, are advantageous in reducing power dissipation.
- Rdson that is, the drain-to-source resistance in the on-state
- MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
- V g denotes the applied gate voltage
- V t h the applied gate voltage
- the short-circuit strength is typically energy-limited, for example by melting the aluminum metallization after impressing the
- R * d SO n directly depends on R * d SO n.
- a reduction of the R * dson therefore automatically leads to a reduction of the short-circuit strength, that is, R * dson and short-circuit strength can not be optimized independently of each other.
- Si-based 1200V semiconductors such as IGBTs (Insulated Gate Bipolar Transistor, German: bipolar transistor with insulated gate electrode). This value is not achieved by current SiC MOSFET concepts and is made even more difficult to realize by the cost-driven trend towards lower Rdson values.
- the gate oxide has a lower band offset on SiC (silicon carbide) Conduction band on as comparable Si devices, so that degradation due to tunneling currents even at lower gate field strengths occurs.
- SiC silicon carbide
- SiC MOSFETs is a reasonable field strength in the gate oxide at about 3 MV / cm. Compliance with this limit is particularly critical in lock-up mode and requires design measures to limit the gate field strength, especially for trench devices, see, for example, Kevin Matocha, "Challenges in SiC power MOSFET design", Solid-State Electronics 52 (2008) 1631-1635 ; "High Performance SiC Trench Devices with Ultra-Low Ron”, T. Nakamura et al., 2011 IEEE International Electron Devices Meeting p.26.51-26.53.
- Possibilities are known in the art for limiting at least the gate field strength.
- the field strength at the gate oxide can be reduced by introducing a double trench with deep p-type implantation.
- the lower-lying p regions shield the actual trench MOSFET structure electrostatically, see, for example, Nakamura et al.
- the field strengths at the gate oxide can likewise be reduced to approximately 4 MV / cm by introducing p-doped regions, so-called “p-bubbles" below the gate oxide, see, for example, "High-Voltage Accumulation Layer
- a corresponding doping profile can be represented without double trench, if the p-regions are very deeply implanted.
- a vertical SiC-MOSFET is provided, with a source terminal, a drain terminal and a gate area and with one between the source terminal and the drain terminal
- the intermediate layer in the epitaxial layer, it is understood in particular that the intermediate layer is surrounded on both sides by the epitaxial layer. It can thus be said that the epitaxial layer penetrates through the intermediate layer into an upper region, which as a rule lies on the side of the intermediate layer facing the source connection, and into a lower region, which as a rule lies on the side of the intermediate layer facing the drain connection. is split. In a special case, further regions or layers may be arranged between the intermediate layer and the upper and / or the lower region of the epitaxial layer. But it is also possible that the intermediate layer directly and in a special case over the entire surface respectively at the top and / or at the bottom of the
- Epitaxial layer adjoins.
- the upper and lower regions of the epitaxial layer may have the same or different doping concentrations.
- the SiC-MOSFET according to the invention has the advantage that the current through the component can be effectively limited in the event of a short circuit. This makes it possible to produce components with particularly high short-circuit ruggedness, which were previously not available for SiC technology.
- the concept according to the invention is integrated vertically, the additional structures do not result in any additional space requirement on the chip.
- the invention is thus surface-neutral with respect to conventional components with respect to Rd SO n * A.
- the inventive design offers the advantage that the field strength in the gate oxide is limited to a level below 3 MV to high
- Short channel effects in the form of an increase in the saturation current with increasing drain voltage which is also advantageous for the short circuit resistance.
- the intermediate layer it is also possible for the intermediate layer to have both regions of first doping and regions of second doping.
- the areas of both first and second doping may span the entire
- the regions of second doping are not completely eliminated when a voltage is less than or equal to a blocking voltage of the SiC-MOSFET.
- This can be achieved by a high doping, for example of at least 5 * 10 17 / cm 3 . It is advantageous if the doping changes as abruptly as possible laterally from one region to the other region. In other words, if possible, there are no or only very small transition regions with less intense doping or mixed doping. Since the regions of doping of the second type in the blocking case by clearing these areas provide significant counter charge for receiving the blocking voltage, the channel length of the MOSFET can be reduced. This results in a favorable reduction of the Rdson. It is advantageously possible that the intermediate layer completely below the
- Gate region is arranged. It then results in a relatively simple constructive structure. Including that the intermediate layer below the
- Gate area is arranged, is in particular understood that the
- Intermediate layer is arranged vertically between the gate region and the drain region. Elements of the gate region, for example a gate trench, do not then intersect or interrupt the interlayer.
- junction field effect transistor also English junction FET or JFET
- jfet EP * (
- ljf e t is the thickness of the interlayer
- IEPI is the thickness of the epitaxial layer
- N DEPI is the doping concentration of the epitaxial layer
- ND is the doping concentration of the areas of first doping of the interlayer
- NA is the doping concentration of the areas of second doping of the interlayer
- djfet is the areal extent of the areas first Doping of the intermediate layer and dpjfet the horizontal extension of the regions of the second doping of the intermediate layer.
- the reduced sheet charge density according to the invention in the body is
- qbait is the sheet charge density in the body of a conventional MOSFET, as would be required in the design without a JFET region
- qjFET is the maximum effective effective charge of the JFET region interlayer in the partially evanescerated field distribution
- Delta3D is an adaptation term for 3D effects as well as a safety margin for a sufficient blocking strength, so that no punch through body takes place to the source.
- a development of the invention provides that the transition layer to the intermediate layer vertically in the direction of the source terminal and / or in the direction of the drain terminal with a stronger than in the epitaxial layer
- Epitaxial layer of stronger doping of the first kind adjacent adjoins the upper region of the epitaxial layer. Again, current restrictions at the pn junctions are avoided.
- Epitaxial layer has a higher doping of the first kind, in particular a factor of 2 to 4 higher doping of the first kind, as one between the
- transition layers with a stronger, ie a higher concentration, doping of the first kind, which adjoin the epitaxial layer can also be referred to as spread layers.
- the design rule is observed that the total dose of the introduced dopants compared to the simple
- Epitaxial layer is kept constant. In other words, as the concentration increases at a location elsewhere, a lower doping concentration may be chosen to compensate.
- a development of the invention provides that the first areas
- Epitaxial layer adjoins. Compared to the previously described
- Embodiment here are not used complete spread layers, but only to the areas of second doping of the intermediate layer adjacent transition areas or spread areas. This results in a further optimization of the on-resistance of the MOSFET.
- design can be implemented using a multiple implant of different depths in combination with a mask spacer.
- junction field effect transistor and a channel of the MOSFET are arranged vertically one above the other
- the periodicity (cell pitch) of the junction field effect transistor can correspond to half the cell pitch of the TrenchMOS cell.
- the functional junction field effect transistor is electrically connected in series with the MOSFET.
- MOSFET is here the classic, functional MOSFET within the device, so usually the above the intermediate layer arranged region of the device understood.
- This enables the integration of a short-circuit proofed MOSFET JFET cascade into a single device.
- An advantage of this configuration is that the JFET is fed back across the voltage drop of the MOS region
- Doping the MOS region and the pinch voltage can be set within certain limits.
- Interlayer may also have a different periodicity and / or another
- Elements of the MOS structure which are arranged on a certain width of the chip, differ in number and distance from the elements of the intermediate layer.
- a typical extent of the regions of the first doping of the intermediate layer is in the region of 500 nm.
- the lateral extent of the regions of second doping of the intermediate layer is slightly larger than that of the regions of first doping, for example by a factor of 1, 2 or 1.5.
- the number of regions of first and second doping per unit cell of the MOS structure, that is, for example per gate trench, then results from the ratio between the distance between these MOS structures and the periodicity of the intermediate layer.
- the MOS structure can be on the chip (supervision or layout) as
- Line structure or two-dimensional grid structure may be present.
- three-dimensional structures such as square gratings, honeycombs or
- Hexagonal grid be present. These can in principle be combined with any analog periodic JFET grid structure.
- FIG. 1 shows an equivalent circuit diagram of an embodiment of the invention
- FIG. 2 shows a cross section through an exemplary embodiment of a MOSFET according to the invention
- FIG. 3 shows a detailed illustration of the intermediate layer from FIG. 2,
- FIG. 4 shows a diagram in which possible doping concentrations are plotted
- FIG. 5 shows a further diagram in which possible doping concentrations are plotted
- FIG. 6 shows a cross section through an embodiment in which a path for a line integral is shown schematically
- FIG. 7 shows a cross section through an embodiment with transition layers
- FIG. 8 shows a development of the embodiment shown in FIG. 7,
- FIG. 9 shows a further embodiment of the invention
- FIG. 10 shows an alternative possibility for designing the intermediate layer
- Figure 1 3 embodiments, which differ in the embodiment of
- FIG. 13 shows a horizontal section through the exemplary embodiment from FIG. 11,
- FIG. H shows a representation analogous to FIG. 12,
- Figure 15 shows two further embodiments of the MOSFET according to the invention
- Figure 16 is a typical embodiment of the invention
- 17 shows the applicability of the concept to different transistor concepts
- FIG. 1 shows an equivalent circuit diagram of an embodiment of the invention.
- On display are the typical elements of a MOSFET 1, namely the
- the conductive connection 12 between the source terminal 2 and the JFET gate 14 is a
- a junction field effect transistor is formed which effectively limits high currents through the device 1.
- Figure 2 shows a cross section through an embodiment of a
- the device may consist of a plurality of unit cells. Also, some elements of MOSFET 20 are not fully illustrated.
- n-doped substrate 21 On a typically heavily doped substrate 21 is an n-doped
- Epitaxial layer 22 applied, in turn, an intermediate layer 24 is embedded.
- the epitaxial layer is divided into an upper region 22.1 and a lower region 22.2.
- a metallization 26 represents the drain connection.
- the intermediate layer 24 is initially illustrated in FIG. 2 without further details.
- a metallization 28 as a source contact 2
- a metallization 30 as a gate contact.
- n-doped source region 34 and the gate region 36 arranged in a trench are shown.
- the gate region 36 is formed by an insulating layer 38 from the source region 32 and from the
- Epitaxial layer 22 separated. If a voltage is applied between the source contact 2 and the gate contact 4, an electric current flows in the figure from top to bottom, ie vertically, through the MOSFET 20, when a voltage above the threshold voltage of the MOSFET 20 is applied to the gate contact 32 and at the drain 26 a positive with respect to the source contact 28
- FIG. 3 shows a detailed illustration of the intermediate layer 24 from FIG. 2.
- the upper and lower parts of the epitaxial layer adjoining the intermediate layer 24 are in each case in the upper and in the lower region of the FIGURE
- Embodiments can also be made with reversed doping.
- Important design parameters for the functionality of the device 20 are the dimensions of the p-doped regions 40 and the n-doped regions 42 as well as the thickness lj fe t of the intermediate layer 22.
- the intermediate layer 22 as such forms the so-called JFET region as a whole.
- the width of the p-doped regions 40 is denoted by dpj f et and the width of the n-doped regions 42 by dj f et.
- the source terminal 17 is in the upper portion of the epitaxial layer 22 in the figure, whereas the drain terminal 18 of the junction field effect transistor 16 in the lower
- the gate 19 of the Junction field effect transistor is connected to the p-doped regions 40.
- these p-doped regions 40 are the gate of the
- FIG. 4 shows a diagram in which possible doping concentrations for the n-doped regions 42 are dependent on the width of the n-doped regions
- Curve 101 is for the minimum size for djfet for each
- Figure 5 shows a diagram analogous to Figure 4 with the difference that of a doping concentration of 5 * 10 17 / cm 3 for the p-doped regions
- n-side space charge zones become the same size as djfet, that is, between the p-doped regions 40 disappear the quasi-neutral areas of the n-majority carriers of the n-doped areas 42.
- UMOS expediently has values of at least 1V, typically between 5V and 20V. A reasonable upper limit may be 20% of the reverse voltage. It applies
- the line integral Int1 extends from the source region 34 through the epitaxial layer 22 to the n-doped region 42.
- the limit for djfet corresponds to the lowest one as djfet_min
- Figure 7 shows a cross section through an embodiment
- the transition layers 50.1, 50.2 each have an n-doping of higher concentration than the epitaxial layer 22.1 or 22.2. Such a configuration prevents large space charge zones or current restrictions from occurring form the vertical pn junctions to the p-doped regions 40.
- pijfet as the lateral dimension of the JFET structure.
- FIG. 8 shows a development of the exemplary embodiment shown in FIG. 6, which is characterized by a third transitional layer 50
- Source region 34 and the epitaxial layer 22 is arranged. It also becomes clear that the dopants of the three transition layers ns P i, ns P 2 and ns P 3 can be different.
- FIG. 9 shows a variant in which the transition layers do not cover the entire cross-section of the MOSFET, but only extend in regions in the addressed layers. They are therefore considered
- Transition areas or spread areas 52.1, 52.2, 52.3 are designated. Of the
- Transition region 52.1 is again above the intermediate layer 24 in the region between the intermediate layer 24 and the epitaxial layer 22.
- Transition region 52.2 is located below the intermediate layer 24 between the intermediate layer 24 and the epitaxial layer 22.
- the transition regions 52.1, 52.2 each span the n-doped region 42 between two p-doped regions 40.1, 40.2. Moreover, on both sides of the n-doped region of the intermediate layer 24, they cover a small part of the
- regions 40.1, 40.2 are approximately as large as half the width of the n-doped region in the intermediate layer.
- the third transition region 52.3 is arranged in the region in which the gate region 36, p-body 64 and epitaxial layer 22 adjoin one another. It has a relatively small extent. It becomes clear that NA and N D, ie ppjfet and rijfet, N DEPI, as well as the doping between the MOSFET body and the JFET region, need not be constant, but may have a location dependency.
- FIG. 10 shows a further possibility for designing the intermediate layer 24.
- the goal is to avoid current constrictions.
- this is achieved by slightly “retracting" the p-doped regions 40 in the vicinity of the epitaxial layer 22.
- Interlayer 24 here as from three separate layers 24.1, 24.2, 24.3 understood, which are basically identical, but differ in the lateral extent.
- the middle layer 24.2 is in
- the width of the n-doped region 42.2 is the middle layer
- the overall result is a roughly hourglass-shaped or double-funnel-shaped cross section for the n-doped region 40.
- Figure 1 1 shows three embodiments, which are in the embodiment of
- Epitaxial layer 22.1 above the intermediate layer 24 differ.
- An exemplary embodiment is shown in the left-hand area of the figure, in which a p-doped region 62.1 extending to the intermediate layer 24 is introduced below the gate trench 39 in the epitaxial layer 22.
- the area between gate trench 39 and intermediate layer 24 is mostly filled with p-doped material.
- the region of the intermediate layer 24 which lies below the gate trench 39 is also made of p-doped material. It is thus in comparison to the previously described embodiments below the
- another p-doped region 62.2 is arranged below the p-body region 64. Also this area is in
- Figure 12 shows a longitudinal and a cross section through an embodiment analogous to the embodiment shown in Figures 2 and 3.
- the vertical dashed line indicates the sectional plane of the section shown in the right portion of FIG. It can be seen that the p-doped regions 40 are conductively connected to the source pad 2. Farther It can be seen that the gate electrode 36 arranged in the gate trench 39 was partially interrupted for the contacting. Technically, the
- transverse webs 60 Realize connection with p-doped transverse webs 60 between the p-doped regions. These transverse webs 60 are shown in FIG.
- a contact via deep contact implant In the case of two JFET channels per parallel MOS cell, no transverse webs are required for the electrical connection of the p areas.
- the contacts are not limited to running parallel to the trench JFET structures but can also be made selectively at contact points between JFET grid (p regions of the JFET region) and the contact designs. Likewise, contacting the p regions outside the active MOS cells is conceivable.
- FIG. 13 shows a horizontal section along the horizontal dashed line from FIG. 12. The section thus runs through the intermediate layer 24 and parallel to it. As dashed lines lying on the plane above the gate areas 36 are shown. After the vertical
- Trenches 39 can be seen here, it can be seen that the individual p-doped regions 40 are interconnected by the n-doped
- Areas 42 of the intermediate layer 24 are interrupted.
- FIG. 14 shows a representation analogous to FIG. 13.
- the gate regions 36 again shown as dashed lines, it becomes clear that the
- Gate trenches 39 and the n-doped regions 42 of the intermediate layer 24 an angle of for example 20 °, 45 ° or even 90 ° exist.
- the n-doped regions 42 of the intermediate layer 24 can also run parallel to the gate regions 39. Likewise, different periodicities are possible.
- FIG. 15 shows two embodiments of the MOSFET 20 according to the invention, which are characterized only by the structure of the intermediate layer 24 and in turn by the spacing and number of the n-doped regions 42 and the p-doped regions Regions 40 of the intermediate layer 24 differ.
- an example is shown which has only one n-doped region 42 in the intermediate layer 24 per MOS cell.
- the embodiment shown in the right part of the figure has five n-doped regions 42 per unit cell, one of which is located centrally below the gate trench 39 and, since only one half cell is shown, only half is shown.
- the p-doped regions 40 lying between the n-doped regions 42 are made slightly wider than the n-doped regions 40.
- Figure 16 shows a typical embodiment. All important dimensions are illustrated once more in the figure. There are the already known from the other figures reference numerals.
- Figure 17 shows the applicability of the concept to various
- Transistor concepts The left part of the figure shows the already known integration into a trench MOSFET.
- a DMOS English: double-diffused metal-oxide semiconductor field effect transistor
- a VMOS from English: v-groved MOS field-effect transistor
- FIG. 18 shows output characteristics (107) of a conventional MOSFET in comparison to two MOSFETs (108), (109) according to the invention.
- MOSFET According to the MOSFET according to the invention is to detect a large increase in current at low drain voltages (ie good on-resistance). For higher drain voltages, a sharp transition to an almost horizontal characteristic occurs. When the drain voltage reaches the pinch voltage of the
- junction field effect transistor it comes to the transition.
- voltages above the transition voltage can be set to different values, as can be seen from the comparison of the two MOSFET characteristics of the invention.
- Dopants be replaced by p-type dopants and vice versa.
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Abstract
Description
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DE102016205331.0A DE102016205331A1 (de) | 2016-03-31 | 2016-03-31 | Vertikaler SiC-MOSFET |
PCT/EP2017/051895 WO2017167469A1 (de) | 2016-03-31 | 2017-01-30 | Vertikaler sic-mosfet |
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US (1) | US11164971B2 (de) |
EP (1) | EP3437138A1 (de) |
JP (1) | JP6807948B2 (de) |
CN (1) | CN108886056B (de) |
DE (1) | DE102016205331A1 (de) |
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JP7206919B2 (ja) * | 2019-01-07 | 2023-01-18 | 株式会社デンソー | 半導体装置 |
DE102019212649A1 (de) * | 2019-08-23 | 2021-02-25 | Robert Bosch Gmbh | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
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DE102004015921B4 (de) * | 2004-03-31 | 2006-06-14 | Infineon Technologies Ag | Rückwärts sperrendes Halbleiterbauelement mit Ladungskompensation |
JP4604241B2 (ja) * | 2004-11-18 | 2011-01-05 | 独立行政法人産業技術総合研究所 | 炭化ケイ素mos電界効果トランジスタおよびその製造方法 |
JP5052025B2 (ja) * | 2006-03-29 | 2012-10-17 | 株式会社東芝 | 電力用半導体素子 |
JP2008172007A (ja) * | 2007-01-11 | 2008-07-24 | Fuji Electric Device Technology Co Ltd | 絶縁ゲート型炭化珪素半導体装置とその製造方法。 |
JP2008177335A (ja) | 2007-01-18 | 2008-07-31 | Fuji Electric Device Technology Co Ltd | 炭化珪素絶縁ゲート型半導体装置。 |
US7875951B2 (en) * | 2007-12-12 | 2011-01-25 | Infineon Technologies Austria Ag | Semiconductor with active component and method for manufacture |
US8203181B2 (en) * | 2008-09-30 | 2012-06-19 | Infineon Technologies Austria Ag | Trench MOSFET semiconductor device and manufacturing method therefor |
TW201108388A (en) * | 2009-04-10 | 2011-03-01 | Sumitomo Electric Industries | Insulated gate field effect transistor |
CN102723355B (zh) * | 2012-06-29 | 2015-06-10 | 电子科技大学 | 槽栅半导体功率器件 |
CN102779852B (zh) * | 2012-07-18 | 2014-09-10 | 电子科技大学 | 一种具有复合栅介质结构的SiC VDMOS器件 |
US8637922B1 (en) * | 2012-07-19 | 2014-01-28 | Infineon Technologies Ag | Semiconductor device |
US20140103439A1 (en) * | 2012-10-15 | 2014-04-17 | Infineon Technologies Dresden Gmbh | Transistor Device and Method for Producing a Transistor Device |
CN103840012A (zh) * | 2012-11-22 | 2014-06-04 | 无锡华润上华半导体有限公司 | 一种结型场效应晶体管及其制备方法 |
US9293558B2 (en) * | 2012-11-26 | 2016-03-22 | Infineon Technologies Austria Ag | Semiconductor device |
US9035380B2 (en) * | 2012-11-27 | 2015-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage drain-extended MOSFET having extra drain-OD addition |
DE102014000613A1 (de) | 2014-01-18 | 2015-07-23 | Lanxess Deutschland Gmbh | Polyester Zusammensetzungen |
DE102014200613A1 (de) * | 2014-01-15 | 2015-07-16 | Robert Bosch Gmbh | SiC-Trench-Transistor und Verfahren zu dessen Herstellung |
CN103915506B (zh) * | 2014-04-28 | 2016-08-31 | 重庆大学 | 一种具有纵向npn结构的双栅ldmos器件 |
JP6857351B2 (ja) * | 2017-02-28 | 2021-04-14 | 国立研究開発法人産業技術総合研究所 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
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CN108886056A (zh) | 2018-11-23 |
US11164971B2 (en) | 2021-11-02 |
TW201803125A (zh) | 2018-01-16 |
DE102016205331A1 (de) | 2017-10-05 |
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TWI714749B (zh) | 2021-01-01 |
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