CN108886056A - 垂直SiC-MOSFET - Google Patents
垂直SiC-MOSFET Download PDFInfo
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- CN108886056A CN108886056A CN201780021075.XA CN201780021075A CN108886056A CN 108886056 A CN108886056 A CN 108886056A CN 201780021075 A CN201780021075 A CN 201780021075A CN 108886056 A CN108886056 A CN 108886056A
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- 230000015556 catabolic process Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 description 13
- 229910010271 silicon carbide Inorganic materials 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
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- 238000001465 metallisation Methods 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
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Abstract
提出一种垂直SiC‑MOSFET(20),其具有源极连接端(2)、漏极连接端(4)和栅极区域(36)并且具有布置在所述源极连接端(2)与所述漏极连接端(4)之间的、具有第一类型的掺杂的外延层(22),其中,水平延伸的中间层(24)嵌入到所述外延层(22)中,所述中间层具有以下区域(40):所述区域具有与第一类型的掺杂不同的第二类型的掺杂。所述垂直SiC‑MOSFET(20)的特征在于,至少具有第二类型的掺杂的区域(40)与所述源极连接端(2)导电连接。栅极区域(36)可以布置在栅极沟道(39)中。
Description
技术领域
本发明涉及一种垂直SiC-MOSFET,即一种MOSFET(Metal-Oxide-SemiconductorField Effect Transistor,德语Metall-Oxid-Halbleiter-Feldeffekttransistor:金属氧化物半导体场效应晶体管),其在硅碳基上制造并且其元件主要彼此垂直地布置。电流流动的方向尤其同样基本上垂直定向。
背景技术
半导体构件、尤其功率构件例如功率MOSFET具有不同的待优化的标准。因此,高的短路强度、即经受住以无负载运行的形式的短路情况而无损害是值得希望的。同样,一般地,Rdson、即在漏极与源极之间在导通状态中的电阻的低的值是有利的,以便降低损耗功率。经典地,在传统的MOSFET的情况下使两个值彼此直接相关:对于典型的传统的MOSFET(Metal-Oxide-Semiconductor Field-Effect-Transistor,德文:Metall-Oxid-Halbleiter-Feldeffekttransistor:金属氧化物半导体场效应晶体管)——其在此代表功率MOSFET被考虑,
以下基本的MOSFET等式适用,饱和电流根据以下等式:
在此,Vg表示存在的栅极电压,Vth表示MOS通道的应用阈值电压,并且,R* dson=Rdson-R漂移表示MOSFET在线性区域中的通道电阻。对于常量Kf
对于根据现有技术的MOSFET得出值KF=1(对于Idsat在线性运行平台(plateaus)的开始处测量的)。
短路强度典型地是能量受限的,例如通过在施加短路能量Esc,max之后熔化铝金属化部,从而可达到的短路时间tscwt在存在的电压Uds的情况下由于
而直接取决于R* dson。在传统的MOSFET的情况下,R* dson的降低因此自动地导致短路强度的降低,也就是说,R* dson和短路强度不能够相互独立地被优化。
在牵引应用中,tscwt>10μs的有保障的短路强度是基于Si的1200V半导体如IGBT(英文:insulated-Gate Bipolar Transistor,德文:Bipolartransistor mit isolierterGate-Elektrode:绝缘栅双极晶体管)的现有技术。所述值不由当前SiC-MOSFET方案实现并且由于至更低的Rdson值的成本驱动的趋势还更难实现。
例如参见
《Short Circuit Robustness of 1200V SiC Junction Transistors and powerMOSFETs》,Siddarth Sundaresan等人所著,(GeneSiCSemiconductor)ICSCRM 2015;《Repetitive Short-Circuit tests on SiC VMOS devices》,Maxime Berthou等人所著,(Laboratoire Ampere,France),ICSCRM 2015;《Concept with grounded Bottom layerfrom Mitsubishi》
《Impact of Grounding the Bottom Oxide Protection Layer on the Short-Circuit Ruggedness of 4H-SiC TrenchMOSFETs》,R Tanaka等人所著,(MitsubishiElectr.Corp)ISPSD2014;
《Temperature-Dependent Short-Circuit Capability of Silicon CarbidePower MOSFETs》,Z.Wang等人所著,(Univ.of Tennessee)IEEE TRANSACTIONS ON POWERELECTRONICS,第31卷,第2期,2016年2月。
另一问题可以是栅极氧化物中的过高场。原则上,SiC(碳化硅)上的栅极氧化物与可比的硅构件相比具有在导带中的更小的带偏移,从而由于隧道电流引起的退化已经在更低的栅极场强的情况下出现。对于SiC-MOSFET,栅极氧化物中的有意义的场强处于大约3MV/cm。该边界值的遵守尤其在截止运行中是关键的并且使得主要在沟道设备中需要用于限制栅极场强的设计措施,例如参见Kevin Matocha所著的《Challenges in SiC powerMOSFET design》,Solid-State Electronics 52(2008)1631-1635;《High PerformanceSiC Trench Devices with Ultra-low Ron》,T Nakamura等人所著,2011IEEEInternational Electron Devices Meeting第26.51-26.53页。
由现有技术已知一些用于至少限制栅极场强的可能性。因此,例如可以通过引入具有深的p注入的双沟道来降低栅极氧化物处的场强。在此,处于更深的p区域以静电的方式屏蔽真正的沟道MOSFET结构,例如参见Nakamura等人所著。
栅极氧化物处的场强可以同样通过引入p掺杂的区域、在栅极氧化物之下的所谓的“p泡(p-bubble)”来降低到大约4MV/cm,参见例如《High-Voltage Accumulation-LayerUMOSFET’s in 4H-SiC》,J.Tan等人所著,IEEE ELECTRON DEVICE LETTERS,第19卷,第12期,1998年12月。
替代地,可以将以上所提及的两个措施(双沟道,p泡)组合,参见Shinsuke Harada等人所著的《Determination of optimum structure of 4H-SiC Trench MOSFET》,2012年第24期会议记录国际功率半导体器件与集成电路会议,第253页之后。作为另外的变型方案,当非常低地注入p区域时,可以示出在无双沟道的情况下的相应的掺杂特性。
由DE10201400613A1已知一种垂直沟道MOSFET,其在外延层以内具有补偿层,该补偿层具有相反的掺杂,所述补偿层能够实现:限制最大出现的场强。
发明内容
根据本发明提供一种垂直SiC-MOSFET,其具有源极连接端、漏极连接端和栅极区域并且具有布置在所述源极连接端与所述漏极连接端之间的、具有第一类型的掺杂的外延层,其中,水平延伸的中间层嵌入到所述外延层中,所述中间层具有以下区域:所述区域具有与第一类型的掺杂不同的第二类型的掺杂,其中,至少具有第二类型的掺杂的区域与所述源极连接端导电连接。在传统的MOS结构之下存在另一平面,该另一平面至少具有以下区域:所述区域具有与外延层的掺杂相反的掺杂。
中间层嵌入到外延层中尤其理解为,中间层在两侧由外延层包围。即可以说,外延层通过中间层划分成上区域和下区域,所述上区域在通常情况下处于中间层的指向源极连接端的一侧上,所述下区域在通常情况下处于中间层的指向漏极连接端的一侧上。在特殊情况下,在中间层与外延层的上区域和/或下区域之间可以布置有另外的区域或层。但同样也可能的是,中间层直接并且在特殊情况下全面积地分别邻接外延层的上区域和/或下区域。外延层的上区域和下区域可以具有相同的或不同的掺杂浓度。
根据本发明的SiC-MOSFET具有如下优点:可以通过部件在短路情况下有效地限制电流。因此可以制造具有特别高的短路稳定性的部件,如其至今对于SiC技术是不可获得的那样。
通过垂直地集成根据本发明的方案的方式,通过附加的结构不在芯片上产生附加的空间需求。
本发明因此相对于传统的部件在Rdson*A方面是面中性的
此外,根据本发明的设计提供如下优点:将栅极氧化物中的场强限制到3MV以下的水平上,以便满足对于部件的使用寿命的高的要求。因此,不仅可以限制短路情况中的电流而且可以在截止情况中在存在的电压的情况下有效地屏蔽栅极氧化物。
通过屏蔽MOS通道使其免受漏极场的影响得出可靠性优点并且此外能够实现以饱和电流随着升高的漏极电压而上升的形式的短通道效应的降低,这同样对于短路强度是有利的。
也可能的是,中间层不仅具有第一掺杂的区域而且具有第二掺杂的区域。通过选择不同区域的尺寸和掺杂浓度,可以有针对性地调节MOSFET的特性。第一掺杂的区域和第二掺杂的区域可以在整个层厚度上延伸。
有利地设置,当电压小于或等于SiC-MOSFET的截止电压时,不完全腾空第二掺杂的区域。这可以通过高的掺杂、例如至少5*1017/cm3的掺杂实现。在此,有利的是,掺杂横向地从一区域至另一区域尽可能突然变化。换言之,根据可能性,不存在具有较不强的掺杂或混合掺杂的过渡区域,或者,仅仅存在非常小的具有较不强的掺杂或混合掺杂的过渡区域。因为具有第二类型的掺杂的区域在截止情况下通过腾空所述区域来提供用于接收(Aufnahme)截止电压的显著的反电荷,所以可以降低MOSFET的通道长度。这导致Rdson的有利的减小。
有利地可能的是,中间层完全布置在栅极区域之下。然后,得出相对简单的结构性的构造。中间层布置在栅极区域之下尤其理解为,中间层垂直地布置在栅极区域与漏极区域之间。栅极区域的元件、例如栅极沟道不切割中间层或不使其中断。
根据本发明的一种优选的实施方式设置,中间层与外延层一起功能性地构成截止层场效应晶体管。在具有关断的栅极的静态的截止情况下,随着增加的漏极电压,腾空第一掺杂的区域,也就是说,在中间层中的具有第一类型的掺杂的区域中不再存在近似中性(quasineutral)的区域,从而基本上通过JFET可以接收漏极电压的进一步提高。通过截止层场效应晶体管(也是英文Junction-FET或JFET),可以在短路情况中有效地限制流过MOSFET的电流。
不完全腾空区域尤其理解为,在施加截止电压之后还在所涉及的区域中存在近似中性的区域。
此外,因此得出另一设计参数,因为MOSFET的上部分中的MOS区域现在可以对于显著更小的截止电压设计,因为中间层或JFET接收截止电压的主要部分。在截止情况中提供腾空的反电荷,从而在真正的MOS结构处仅仅存在显著更小的电场并且因此在体中需要更少的反电荷。这允许相对于现有技术通道长度的降低。
这通过如下方式实现:如此选择具有第二类型的掺杂的区域的厚度和掺杂(NA=ppjfet),使得至少通过具有第二类型的掺杂的区域的电荷可以削减漂移区域的电压。由此得出以下设计法则(对于恒定的掺杂):
在此,ljfet是中间层的厚度,lEPI是外延层的厚度,NDEPI是外延层的掺杂浓度,ND是中间层的第一掺杂的区域的掺杂浓度,NA是中间层的第二掺杂的区域的掺杂浓度,djfet是中间层的第一掺杂的区域的水平延展,并且,dpjfet是中间层的第二掺杂的区域的水平延展。掺杂比例关系的特定的、有意义的选择例如是ND=njfet>NEPI,NA=ppjfet>ND。
在中间层和EPI层中的非逐段式恒定的掺杂的情况下,替代NA、ND和尺寸的乘积,可以进行相应的体积积分。
基于JFET功能性,可以根据关系qb新=qb旧-qJFET+Delta3D使体中的薄层电荷密度(Sheet-Ladungsdichte)降低。在此,qb新是体中的根据本发明降低的薄层电荷密度,qb旧是传统的MOSFET的体中的薄层电荷密度,如其在设计的情况下在无JFET区域的情况下所需要的那样,qJFET是在相应于截止情况中的场分布的部分腾空的状态中充当JFET区域的中间层的在最大电压的情况下起作用的有效电压,并且,Delta3D是用于3D效应的匹配项以及用于足够的截止强度的安全附加,从而不发生通过体至源极的穿通。
本发明的一个扩展方案设置,具有相对于外延层更强的第一类型的掺杂的过渡层垂直地在源极连接端的方向上和/或在漏极连接端的方向上邻接中间层。因此阻止:至中间层的第二掺杂的区域的垂直的pn结导致大的垂直空间电荷区域或在中间层之上或之下的电流收缩(Stromeinengung)。
此外,有利的是,具有相对于外延层更强的第一类型的掺杂的过渡层垂直地在源极连接端的方向上邻接外延层。换言之,过渡层邻接外延层的上区域。在此,也避免在pn结处的电流收缩。
由于相同的原因,有利的是,外延层的布置在源极连接端与中间层之间的上部分相比外延层的布置在中间层与漏极连接端之间的下部分具有更高的第一类型的掺杂、尤其高2倍至4倍的第一类型的掺杂。
所描述的具有更强的、即更高浓缩的第一类型的掺杂的过渡层——所述过渡层邻接外延层——也可以称为扩展层(Spreadschicht)。有利地,在扩展层的构型中遵守设计法则:使所引入的掺杂物的总剂量相比于简单的外延层保持恒定。换言之,在提高在一部位的浓度的情况下可以在另一部位选择更低的掺杂浓度,以便实现平衡。
本发明的另一扩展方案设置,具有与外延层相比更强的第一类型的掺杂的过渡区域垂直地在源极连接端的方向上和/或在漏极连接端的方向上邻接中间层的第一掺杂的区域,其中,外延层至少部分地邻接中间层的第二掺杂的区域。相比于之前描述的实施方式,在此,不使用完整的扩展层,而是仅仅使用邻接中间层的第二掺杂的区域的过渡区域或扩展区域。由此得出MOSFET的导通电阻的进一步优化。所描述的设计可以实际上例如通过不同深度的多重注入与掩模间隔区(Maskenspacer)组合地实现。
本发明的一种特别的构型设置,中间层的第一掺杂的区域具有双节漏斗形的轮廓或沙漏形的轮廓。换言之,中间层的第一掺杂的区域的水平延展分别从上部并且从下部向中间层的中间缩细。借助该措施,也可以提高击穿电压。所描述的所有措施显然可以彼此组合,只要几何上可能。
本发明的一种有利的构型设置,截止层场效应晶体管的通道和MOSFET的通道彼此垂直地布置。截止层场效应晶体管的周期性(单元节距(Zellpitch))在此可以相应于沟道MOS单元的半个单元节距。
以这种方式,可以使截止层场效应晶体管的量值最小化到电阻RDSon。从最优位置出发,构件的功能在此相对于JFET区域相对MOS区域或dpJFET的尺寸的变化的横向移位(失调)相对较不敏感。
有利地设置,功能性的截止层场效应晶体管与MOSFET串联地电连接。在此,MOSFET理解为部件内的经典的、功能性的MOSFET,即在通常情况中构件的布置在中间层之上的区域。由此,能够在唯一的部件中实现针对短路强度设计的MOSFET-JFET-级联的集成。该配置的一个优点是,JFET通过MOS区域的电压下降与MOSFET反向耦合(gegenkoppeln)并且因此向上限制电流:如果漏极电流升高到如此程度,使得在MOS区域上的电压下降达到JFET的夹断电压(Pinch-Spannung)的量值的数量级,则JFET决定性地为电流限制做贡献。漏极电流通过达到JFET的阈值条件(夹断电压)来限制。因此,避免通道长度调制并且因此避免在高漏极电压的情况下MOSFET的进一步升高的饱和电流。可以通过MOS区域上的电压下降或MOS区域的掺杂以及夹断电压在一定的边界中调节阈值条件的达到。
与MOS单元相比,JFET区域内的或中间层内的JFET通道也可以具有不同的周期性和/或不同的取向。换言之,MOS结构的布置在芯片的确定宽度上的元件可以在中间层的元件的数目和距离方面不同。在MOS平面的元件的、即例如栅极二极管的取向与中间平面的元件的定向之间也可以存在任意角度。
此外,可以实现其他的JFET栅极形状例如蜂巢结构、方形结构等。中间层的第一掺杂的区域的典型的延展处于500nm的范围中。有利地,中间层的第二掺杂的区域的横向延展比第一掺杂的区域的横向延展略大、例如大1.2倍或1.5倍。MOS结构的每单位单元、即例如每栅极沟道的第一和第二掺杂的区域的数目由所述MOS结构的距离与中间层的周期性之间的比例关系得出。
MOS结构可以在芯片(俯视图或布局)上作为线结构或二维格栅结构存在。在此,在JFET层的平面或中间平面以内也可以存在三维结构,如方形格栅、蜂巢或六角形形格栅。这些可以在原理上与任意类似的周期性的JFET格栅结构组合。
本发明的有利扩展方案在从属权利要求中说明并且在说明书中描述。
附图说明
根据附图和以下的描述更详细地阐述本发明的实施例。附图说明:
图1:本发明的实施方式的等效电路图;
图2:根据本发明的MOSFET的实施例的横截面;
图3:图2中的中间层的详细示图;
图4:在其中绘出可能的掺杂浓度的图表;
图5:在其中绘出可能的掺杂浓度的另一图表;
图6:一种实施方式的横截面,其中,示意性绘出用于线集成的焊盘;
图7:具有过渡层的实施方式的横截面;
图8:图7中示出的实施例的扩展方案;
图9:本发明的另一实施例;
图10:用于中间层的构型的替代的可能性;
图11:三种实施方式,其在中间层之上的外延层的构型方面不同;
图12:与图2和图3中示出的实施例类似的一个实施例的纵截面和横截面;
图13:图11中的实施例的水平截面;
图14:类似于图12的示图;
图15:根据本发明的MOSFET的两种另外的实施方式;
图16:本发明的一个典型的实施例;
图17:所述方案对于不同的晶体管方案的可应用性;
图18:实施例的输出特征曲线。
具体实施方式
图1示出本发明的一种实施方式的等效电路图。在此,可看见的是MOSFET 1的典型元件,即源极连接端2、漏极连接端4以及栅极连接端6。此外,绘出两个电阻,即MOS区域8的电阻和漂移区域10的电阻。通过源极连接端2与JFET栅极14之间的导电连接部12构造截止层场效应晶体管,所述截止层场效应晶体管通过构件1有效地限制高电流。
当在MOS区域6和8上下降的电压变得大于或等于截止层场效应晶体管的夹断电压的量值时,截止层场效应晶体管接收进一步的漏极电压上升。因此,避免通道长度调制以及因此避免在高的漏极电压的情况下MOSFET的进一步升高的饱和电流。以下还根据另外的附图阐述截止层场效应晶体管的或JFET的准确的工作原理。
图2示出根据本发明的MOSFET 20的一个实施例的横截面。在此,仅仅示出构件的一个区段,典型地,构件可以由多个单位单元构成。同样地,MOSFET 20的一些元件未完全示出。
在典型地高度掺杂的衬底21上施加有n掺杂的外延层22,在该n掺杂的外延层中又嵌入有中间层24。实际上,外延层划分成上区域22.1和下区域22.2。向下,金属化部26是漏极连接端。中间层24在图2中首先不具有其他的细节地示出。在图的上区域中,示出沟道MOSFET 20的典型元件:可以看出作为源极接通部2的金属化部28和作为栅极接通部的金属化部30。此外,示出n掺杂的源极区域34以及布置在沟道、即沟槽结构中的栅极区域36。栅极区域36通过绝缘层38与源极区域32并且与外延层22分离。如果在源极接通部2与栅极接通部4之间施加一电压,当在栅极接通部32处存在高于MOSFET的阈值电压的电压并且在漏极26处存在相对于源极接通部28为正的电压时,则电流在图中从上向下、即垂直地流过MOSFET 20。
图3示出图2中的中间层24的详细示图。在图的上区域和下区域中,此外可以看见邻接中间层24的外延层的上部分和下部分22.1、22.2。明显地,中间层24在水平的或横向的方向上具有特定结构。因此,在中间层中存在p掺杂的区域40.1、40.2和40.3以及n掺杂的区域42.1和42.2。在这点上再一次指出,如在MOSFET的情况下通常的那样,也可以借助分别相反的掺杂制造所示出的实施例。
对于构件20的功能的重要设计参数是p掺杂的区域40的尺寸以及n掺杂的区域42的尺寸以及中间层22的厚度ljfet。像这样的中间层22总体上构成所谓的JFET区域。在此,p掺杂的区域40的宽度借助dpjfet并且n掺杂的区域42的宽度借助djfet表示。示意性地又绘出导电连接部12,该导电连接部建立p掺杂的区域40与源极连接端2之间的电连接。同样示意性地并且仅仅为了说明工作原理而绘出截止层场效应晶体管的电路符号16,该截止层场效应晶体管的源极连接端17处于外延层22的在图中的上区域中,与此相反,截止层场效应晶体管16的漏极连接端18处于外延层22的下区域中。截止层场效应晶体管的栅极连接端19与p掺杂的区域40连接。因此,所述p掺杂的区域40是截止层场效应晶体管16的栅极。
另一重要的设计参数是区域40和42的掺杂。图4示出一图表,其中,对于n掺杂的区域42的可能的掺杂浓度,根据n掺杂的区域42的宽度、对于不同的JFET夹断电压UgJFETthr,也就是说通过参数的相应选择可以调节JFET的夹断电压。在此,所示出的所有值是针对p掺杂的区域的5*1018/cm3的掺杂浓度计算的。曲线101适用于相应的掺杂浓度的d_jfet的最小大小。曲线102适用于JFET夹断电压Ugthr=5V,曲线103适用于JFET夹断电压Ugthr=10V,曲线104适用于JFET夹断电压Ugthr=20V,并且曲线105适用于JFET夹断电压Ugthr=50V。
图5示出类似于图4的图表,具有以下区别:从对于p掺杂的区域的5*1017/cm3的掺杂浓度出发。
JFET区域的夹断电压UgJFETthr——其存在于接通部17与19之间(参见例如图2和图3)——的特征在于,n侧的空间电荷区域变得与djfet同样大小,也就是说,在这些p掺杂的区域40之间,n掺杂的区域42的n多数载流子的近似中性区域消失。深度tjfet和MOS区域之内的n掺杂为了考虑短路行为而如此选择,使得对于力求达到的饱和电流IDsat在存在的电压Uds=Ucc的情况下(这典型地相应于构件的额定截止强度的50%)对于n多数载流子实现电势下降“UMOS”直至JFET区域24的n空穴其使JFET置于电流限制的状态中。换言之,通过预电压,包围n层42的pn连接部的空间电荷区域扩大到如下程度,使得其大于或等于djfet。符合目的地,UMOS具有至少1V、典型地在5V与20V之间的值。有意义的上边界可以是截止电压的20%。具有:
以及
其中,用于图6中的线积分的路径作为Int1绘出。线积分Int1从源极区域34通过外延层22延伸至n掺杂的区域42。
JFET区域之内的n区域40的和p区域42的横向延展和掺杂如此选择,使得在Uds=0V的情况下n空穴djfet大于NA与ND之间的pn连接部的双倍n侧空间电荷区域,从而在无电压的状态中在JFET区域的n区域之内n多数载流子对于电流运输保留剩余。
对于一维的突变pn结的情况,据此得出以下理想典型的设计法则:
Djfet的边界值分别相应于图4和图5中的作为d_jfet_min绘出的最下部的曲线。对于真实的、空间上的几何结构和掺杂分布,相应的相互关系不能够解析式地示出,但是同样存在并且数值地可解。在此,Ubi表示“嵌入的”电压,其已经在无所施加的外部电压的情况下基于掺杂在价带和导带中在pn结上下降。NA是p掺杂浓度,并且,ND是n掺杂浓度。
图7示出具有过渡层50.1、50.2的实施方式的横截面,这些过渡层分别布置在中间层24之上和之下。过渡层50.1、50.2分别具有一个高浓度的n掺杂作为外延层22.1或22.2。通过这种构型阻止:在到p掺杂的区域40的垂直的pn结处形成大的空间电荷区域或电流收缩。此外,绘出pijfet作为JFET结构的横向尺寸。
图8示出在图6中示出的实施例的扩展方案,所述扩展方案的特征在于第三过渡层50.3,所述第三过渡层布置在源极区域34与外延层22之间。同样明显地,三个过渡层nSp1、nSp2和nSp3的掺杂可以是不同的。
在图9中示出一种变型方案,其中,过渡层不是覆盖MOSFET的整个横截面,而是仅局部地在所提及的层中延伸。因此,它们被称为过渡区域或扩展区域52.1、52.2、52.3。过渡区域52.1又在中间层24与外延层22之间的区域中处于中间层24之上。过渡区域52.2在中间层24与外延层22之间处于中间层24之下。在此,过渡区域52.1、52.2分别跨越p掺杂的两个区域40.1、40.2之间的n掺杂的区域42。此外,它们在中间层24的n掺杂的区域的两侧上覆盖邻接的p掺杂的区域40.1、40.2的一小部分。在此,过渡层52.1、52.2越过p掺杂的区域40.1、40.2之间的“空隙”的延展大约和中间层中的n掺杂的区域的宽度的一半一样大小。
第三过渡区域52.3布置在如下区域中:在所述区域中,栅极区域36、p体64和外延层22彼此邻接。所述第三过渡区域具有相对小的延展。明显地,NA和ND、即ppjfet和njfet、NDEPI以及在MOSFET体与JFET区域之间的掺杂并非必须是恒定的,而是可以具有位置依赖性。
图10示出用于构型中间层24的另一可能性。在此,目标也是,避免电流收缩。在所示出的实施例中,这通过如下方式来实现:p掺杂的区域40在外延层22附近略微“缩回”。在此,中间层24可以理解为由三个独立的层24.1、24.2、24.3构造,这些层原理上相同地构造,但在横向延展方面不同。中部的层24.2基本上如在已经描述的实施例中那样构造。中部的层可以是三个层24.1、24.2、24.3中的最厚的层。中部的层24.2的n掺杂的区域42.2的宽度等于在已经描述的实施例中的n掺杂的区域40的宽度。然而,n掺杂的区域42的上层24.1和下层24.3具有更大的延展。总体上,得出n掺杂的区域40的沙漏形的或双节漏斗形的横截面。
图11示出三种实施方式,其在中间层24之上的外延层22.1的构型方面不同。在图的左边区域中示出一个实施例,其中,在栅极沟道39之下在外延层22中嵌入有到达直至中间层24的p掺杂的区域62.1。换言之,栅极沟道39与中间层24之间的区域大部分以p掺杂的材料填充。中间层24的处于栅极沟道39之下的区域同样由p掺杂的材料构成。因此,与至今描述的实施方式相比,在栅极沟道39之下,n掺杂的材料已经通过p掺杂的材料取代。
在图11的中间区域中,在p体区域64之下布置有另一p掺杂的区域62.2。该区域也基本上覆盖相同地布置在中间层24的p掺杂的区域40上方。在图11的右边区域中示出一个实施例,其将两个版本彼此组合,即不仅具有p掺杂的区域62.1而且具有p掺杂的区域62.2。在图11中示出的所有实施方式具有如下优点:提供不处于通道区域中的p电荷。
图12示出类似于在图2和图3中示出的实施例的一个实施例的纵截面和横截面。垂直延伸的虚线表示在图12的右边区域中示出的截面的截面平面。可以识别,p掺杂的区域40与源极焊盘2导电地连接。还可以识别,布置在栅极沟道39中的栅极电极36部分地为了接通而已经被中断。技术上,例如可以借助在沟道39中的接通注入与p掺杂的横向接片(Querstegen)60结合来在p掺杂的区域之间实现接通。所述横向接片60在图13中示出。
同样可能的是通过深的接通注入的接通。在每平行延伸的MOS单元的两个JFET通道的情况下不需要用于p区域的电连接的横向接片。在此,接通部不限于与沟道平行地延伸的JFET结构,而是也可以逐点地在JFET格栅(JFET区域的p区域)与接通实施之间的接通点处实现。同样地,可以考虑p区域的在主动MOS单元之外的接通。
图13示出沿图12中的水平虚线的水平截面。因此,该截面延伸穿过中间层24并且平行于所述中间层。作为虚线绘出本身处于所示出的平面上方的栅极区域36。在借助沟道39的中断部实现p掺杂的区域40的垂直接通之后,在此可以识别,使各个p掺杂的区域40彼此连接,其方式是,使中间层24的n掺杂的区域42中断。
图14示出类似于图13的示图。根据又作为虚线绘出的栅极区域36,明显地,可以使中间平面24以任意角度α相对于MOSFET的剩余部分旋转。换言之,可以在例如栅极沟道39与中间层24的n掺杂的区域42之间存在例如20°、45°或90°的角度。但显而易见地,中间层24的n掺杂的区域42也可以平行于栅极区域39延伸。同样地,可以实现不同的周期性。
图15示出根据本发明的MOSFET 20的两种实施方式,所述两种实施方式仅仅通过中间层24的结构并且在此又通过中间层24的n掺杂的区域42和p掺杂的区域40的距离和数目来区分。在图的左边区域中示出一个示例,其对于每个MOS单元具有中间层24中的仅仅一个n掺杂的区域42。相反,在图的右边部分中示出的实施例对于每个单位单元具有五个n掺杂的区域42,其中的一个区域居中地处于栅极沟道39下方,并且,因为示出仅仅一个半单元,所以仅仅示出一半。处于n掺杂的区域42之间的p掺杂的区域40相比n掺杂的区域40实施略微更宽地实施。
图16示出一个典型的实施例。在图中再一次说明所有重要的尺度。由其他图已经已知的附图标记也适用。
图17示出所述方案对于不同的晶体管方案的可应用性。在图的左边部分中可以看见到沟道MOSFET中的已知的集成。在图的中间部分中可以看见具有根据本发明的中间层24的DMOS(英文:double-diffused metal-oxide semiconductor field effecttransistor:双扩散金属氧化物半导体场效应晶体管)。在图的右边部分中示出具有根据本发明的中间层24的VMOS(英文:v-groved MOS field-effect transistor:V形槽MOS场效应晶体管)。
图18示出传统的MOSFET相比于两个根据本发明的MOSFET(108)、(109)的输出特征曲线(107)。在传统的MOSFET中可以识别饱和电流随着上升的漏极电压的、突出的增加。在根据本发明的MOSFET中,在小的漏极电压的情况下可以识别强烈的电流增加(也就是说良好的导通电阻)。对于更高的漏极电压出现到几乎水平的特征曲线的清晰过渡。如果漏极电压达到截止层场效应晶体管的夹断电压,则出现过渡。视实施方案和设计而定,可以将饱和电流在高的漏极电压、也就是说过渡电压以上的电压的情况下调节到不同值上,如由两个根据本发明的MOSFET特征曲线的比较可以得出的那样。有利地,如此选择JFET的夹断电压的态势,使得其明显处于MOSFET的接通状态中的典型导通电压以上,但以有意义的方式不超出MOSFET的截止电压的20%。
在描述的所有实施例中,显然可以交换掺杂的符号,而不偏离根据本发明的方案。换言之,可以通过p掺杂替换所描述的所有n掺杂,反之亦然。
Claims (14)
1.一种垂直SiC-MOSFET(20),其具有源极连接端(2)、漏极连接端(4)和栅极区域(36)并且具有布置在所述源极连接端(2)与所述漏极连接端(4)之间的、具有第一类型的掺杂的外延层(22),其中,水平延伸的中间层(24)嵌入到所述外延层(22)中,所述中间层具有以下区域(40):所述区域具有与第一类型的掺杂不同的第二类型的掺杂,其特征在于,至少具有第二类型的掺杂的区域(40)与所述源极连接端(2)导电连接。
2.根据权利要求1所述的垂直SiC-MOSFET(20),其中,所述中间层(22)不仅具有第一掺杂的区域(42)而且具有第二掺杂的区域(40)。
3.根据权利要求1或2所述的垂直SiC-MOSFET(20),其中,当电压小于或等于所述SiC-MOSFET(20)的截止电压时,不完全腾空所述第二掺杂的区域(40)。
4.根据以上权利要求中任一项所述的垂直SiC-MOSFET(20),其中,所述中间层(24)完全布置在所述栅极区域(36)之下。
5.根据以上权利要求中任一项所述的垂直SiC-MOSFET(20),其中,所述中间层(24)与所述外延层(22)一起功能性地构成截止层场效应晶体管。
6.根据以上权利要求中任一项所述的垂直SiC-MOSFET(20),其中,所述截止层场效应晶体管的夹断电压处于1V至所述SiC-MOSFET(20)的击穿电压的50%之间的范围中。
7.根据以上权利要求中任一项所述的垂直SiC-MOSFET(20),其中,具有相比于所述外延层(22)更强的第一类型的掺杂的过渡层(50.1,50.2)垂直地在所述源极连接端(2)的方向上和/或在所述漏极连接端(4)的方向上邻接所述中间层(24)。
8.根据以上权利要求中任一项所述的垂直SiC-MOSFET(20),其中,具有相比于所述外延层(22)更强的第一类型的掺杂的过渡层(50.3)垂直地在所述源极连接端(2)的方向上邻接所述外延层(22)。
9.根据以上权利要求中任一项所述的垂直SiC-MOSFET(20),其中,所述外延层的布置在所述源极连接端(2)与所述中间层(24)之间的上部分(22.1)相比所述外延层的布置在所述中间层(24)与所述漏极连接端(4)之间的下部分(22.2)具有更高的第一类型的掺杂、尤其高2倍至4倍的第一类型的掺杂。
10.根据以上权利要求中任一项所述的垂直SiC-MOSFET(20),其中,具有与所述外延层(22)相比更强的第一类型的掺杂的过渡区域(52)垂直地在所述源极连接端(2)的方向上和/或在所述漏极连接端(4)的方向上邻接所述中间层(24)的第一掺杂的区域(42),其中,所述外延层(22)至少部分地邻接所述中间层(24)的第二掺杂的区域(40)。
11.根据以上权利要求中任一项所述的垂直SiC-MOSFET(20),其中,所述中间层(24)的第一掺杂的区域(42)具有双节漏斗形的轮廓或沙漏形的轮廓。
12.根据权利要求5至11中任一项所述的垂直SiC-MOSFET(20),其中,所述截止层场效应晶体管的通道(56)和所述MOSFET的通道(58)彼此垂直地布置。
13.根据权利要求5至12中任一项所述的垂直SiC-MOSFET(20),其中,所述截止层场效应晶体管与所述MOSFET串联地电连接。
14.一种用于车辆的控制设备,所述控制设备包括根据以上权利要求中任一项所述的垂直SiC-MOSFET(20)。
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US9293558B2 (en) * | 2012-11-26 | 2016-03-22 | Infineon Technologies Austria Ag | Semiconductor device |
DE102014000613A1 (de) | 2014-01-18 | 2015-07-23 | Lanxess Deutschland Gmbh | Polyester Zusammensetzungen |
DE102014200613A1 (de) * | 2014-01-15 | 2015-07-16 | Robert Bosch Gmbh | SiC-Trench-Transistor und Verfahren zu dessen Herstellung |
JP6857351B2 (ja) * | 2017-02-28 | 2021-04-14 | 国立研究開発法人産業技術総合研究所 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
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EP1814162A1 (en) * | 2004-11-18 | 2007-08-01 | National Institute of Advanced Industrial Science and Technology | Silicon carbide mos field-effect transistor and process for producing the same |
US20070272977A1 (en) * | 2006-03-29 | 2007-11-29 | Kabushiki Kaisha Toshiba | Power semiconductor device |
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US20140103439A1 (en) * | 2012-10-15 | 2014-04-17 | Infineon Technologies Dresden Gmbh | Transistor Device and Method for Producing a Transistor Device |
CN103840012A (zh) * | 2012-11-22 | 2014-06-04 | 无锡华润上华半导体有限公司 | 一种结型场效应晶体管及其制备方法 |
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CN103915506A (zh) * | 2014-04-28 | 2014-07-09 | 重庆大学 | 一种具有纵向npn结构的双栅ldmos器件 |
Also Published As
Publication number | Publication date |
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EP3437138A1 (de) | 2019-02-06 |
TW201803125A (zh) | 2018-01-16 |
JP2019514206A (ja) | 2019-05-30 |
WO2017167469A1 (de) | 2017-10-05 |
JP6807948B2 (ja) | 2021-01-06 |
CN108886056B (zh) | 2022-05-17 |
TWI714749B (zh) | 2021-01-01 |
DE102016205331A1 (de) | 2017-10-05 |
US20200295186A1 (en) | 2020-09-17 |
US11164971B2 (en) | 2021-11-02 |
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