CN103915506B - 一种具有纵向npn结构的双栅ldmos器件 - Google Patents
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Abstract
本发明公开了一种具有纵向NPN结构的双栅LDMOS器件,涉及一种半导体功率器件，P‑衬底、有源顶层硅、横向多晶硅栅、纵向多晶硅栅、源电极区、漏电极区和场氧层，有源硅层包含有纵向NPN结构即纵向排列的上层N型硅条、中层P型硅条及下层N型硅条所组成；本发明在常规的功率LDMOS器件基础上，将类似超结结构的NPN漂移区、常规横向栅以及纵向槽型栅结合起来，只要至少一个栅极打开，器件即处于开态，而当两个栅极均打开时，器件为电子提供上下两个导通通道，所以可以有效降低器件导通电阻。另外，器件处于关态时，纵向的NPN结构的RESURF效应得以增强，可在较高掺杂浓度情况下获得高的击穿电压，进一步降低器件导通电阻。
Description
技术领域
本发明涉及一种半导体功率器件，特别涉及一种具有纵向NPN结构的双栅LDMOS器件。
背景技术
功率LDMOS(Lateral Double-diffused Metal-Oxide-Semiconductor即横向双扩散金属-氧化物-半导体)器件广泛应用于功率集成领域，而击穿电压与导通电阻之间的矛盾是人们长期关注的焦点问题之一，并由此提出众多缓解该矛盾的方案，其中RESURF(Reduced SURfaceField,降低表面电场)技术和超结(Superjunction)技术认、是能够有效缓解该矛盾的结构之一。图1为典型的单RESURF技术(Single-RESURF)中1、P-衬底，2、衬底电极，3、漏电极，4、源电极，5、场氧层，6、漏N+区，7、源N+区，9、源P+区，11、横向多晶硅栅，14、P阱，18、N-漂移区。关态时，衬底及源电极接地，漏电极接高压，该结构当外延层全部耗尽时，外延层耗尽区电场与衬底耗尽区电场相互抵消，降低了表面电场，使击穿点由PN结表面转移到体内，达到提高击穿电压和降低比导通电阻的效果。相关内容可见参考文献：J.A.Appels and H.M.J.Vaes,High-voltage thin layer devices,IEDM Tech.Dig.,1979,pp.238-241；S.Y.Han,H.W.Kim,and S.K.Chung,Surface field distributionand breakdown voltage of RESURF LDMOSFETs,Microelectronics Journal,2001,31(8),pp.685-688。在单RESURF结构基础上，双RESURF(Double-RESURF)结构被提出，见图2，其中1、P-衬底，2、衬底电极，3、漏电极，4、源电极，5、场氧层，6、漏N+区，7、源N+区，9、源P+区，11、横向多晶硅栅，14、P阱，18、N-漂移区，19、P-top层。与单RESURF相比较可以看出，双RESURF是在漂移区表面加一个P-top层，该P-top层辅助耗尽N-漂移区，在满足RESURF条件时使得N-漂移区掺杂浓度进一步提高，从而获得更小的导通电阻。相关内容可见参考文献：Souza M.M.D.,Narayanan E.M.S.,Double RESURF technologyfor HVIC,Electronics Letters,1996,Vol.32,No.12,pp.1092-1093；Hardikar S.,SouzaM.M.D.,Xu Y.Z.,et al.,A novel double RESURF LDMOS for HVIC’s,MicroelectronicsJournal,2004,Vol.35,No.3,pp.305-310。超结技术见图3，1、P-衬底，2、衬底电极，3、漏电极，4、源电极，6、漏N+区，7、源N+区，9、源P+区，11、横向多晶硅栅，14、P阱，20、超结N型硅条，21、超结P型硅条。其概念是用交替的高浓度的N区和P区构成了漂移区，在反向偏置电压下N区与P区相互补偿耗尽，达到电荷平衡，所以在漂移区达到了均匀的电场分布，在给定的漂移区长度下，均匀分布的电场可以获得高的击穿电压，而且几乎和漂移区的掺杂浓度无关，并且由于采用了高掺杂浓度的N区，所以导通电阻得到了很好的改善。详见文献D.J.Coe.High voltage semiconductor device.U.S.Patent4754310,June28,1988；X.B.Chen.Semiconductor power devices with alternating conductivitytype high voltage breakdown region.U.S.Patent5216275,June1,1993。目前，采用RESURF结构和超结结构的器件仍然是世界范围内的研究热点，而上述常规的Single-RESURF、Double-RESURF及超结结构都只有一个横向沟道为载流子提供导通路径，在一定程度上限制了器件导通电阻的进一步降低。
发明内容
有鉴于此，为了解决进一步降低功率MOS的导通电阻，缓解器件击穿电压与导通电阻之间的问题，本发明提出一种具有纵向NPN结构的双栅LDMOS器件，较常规RESURF结构大大提高了漂移区掺杂浓度，并且利用纵向沟道和横向沟道分别控制上下两个电子通道，从而有效降低器件在开态时候的导通电阻。
本发明的目的是通过这样的技术方案实现的，一种具有纵向NPN结构的双栅LDMOS器件，包括第一区域和第二区域，所述第一区域与第二区域镜像对称；所述第一区域包括P-衬底1、有源顶层硅、横向多晶硅栅11、纵向多晶硅栅12、源电极区、漏电极区和场氧层5；所述有源顶层硅包括自上而下纵向排列的上层N型硅条15、中层P型硅条16及下层N型硅条17，所述源电极区包括设置在场氧层5内的源电极4、横向沟道源N+区7、纵向沟道源N+区8和源P+区9，其中横向沟道源N+区7和纵向沟道源N+区8位于源P+区9的左右两侧，所述横向沟道源N+区7、纵向沟道源N+区8和源P+区9三者并排设置于上层N型硅条15中且三者同时与源电极4下表面接触；所述漏电极区包括设置在场氧层5内的漏电极3和设置在上层N型硅条15中的漏N+区6，所述漏N+区6与漏电极3的下表面接触，所述横向多晶硅栅11设置在场氧层5内且与场氧层的下表面分离，所述源电极和漏电极设置在横向多晶硅栅的左右两侧，所述上层N型硅条中还设置有与中层P型硅条接触的P阱14，所述P阱14分别与横向沟道源N+区7、纵向沟道源N+区8、源P+区9以及场氧层5的下表面接触；所述纵向多晶硅栅12纵向伸入有源顶层硅中并分别与源电极4、纵向沟道源N+区8、P阱14、中层P型硅条16及下层N型硅条17接触；所述漏N+区6的下表面还设置有伸入上层N型硅条的N阱13，所述N阱13分别与中层P型硅条16、下层N型硅条17接触。
进一步，所述纵向多晶硅栅包括纵向栅氧10和纵向栅氧所包围的导电介质22。
进一步，所述有源顶层硅硅、Si、SiC、GaN半导体材料中的一种或多种。
进一步，还包括SOI衬底埋氧层，所述SOI衬底埋氧层设置于埋于整个P-衬底硅层表面和有源顶层硅之间。
进一步，所述SOI衬底埋氧层还设置有半导体窗口。
由于采用了上述技术方案，本发明具有如下的优点：
本发明在常规的基于RESURF器件基础上，采用纵向的NPN结构，使得关态获得较高耐压的同时，N漂移区的掺杂浓度得以提高，并且采用两个栅极形成横向和纵向两个沟道,从而有效的降低了导通电阻。由于有双栅的结构设计，在两个都打开的情况较单独一个打开的情况下导通电阻更小。该结构同样适用于基于SOI技术的功率器件。
附图说明
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步的详细描述，其中：
图1为常规单RESURF器件结构示意图；
图2为双RESURF器件结构示意图；
图3为常规超结结构示意图；
图4为本发明提出的一种具有纵向NPN结构的双栅LDMOS器件结构；
其中1、P-衬底；2、衬底电极；3、漏电极；4、源电极；5、场氧层；6、漏N+区；7、横向沟道源N+区；8、纵向沟道源N+区；9、源P+区；10、纵向栅氧；11、横向多晶硅栅；12、纵向多晶硅栅；13、N阱；14、P阱；15、上层N型硅条；16、中层P型硅条；17、下层N型硅条；18、N-漂移区；19、P-top层；20、超结N型硅条；21、超结P型硅条、22、导电介质。
具体实施方式
以下将结合附图，对本发明的优选实施例进行详细的描述；应当理解，优选实施例仅为了说明本发明，而不是为了限制本发明的保护范围。
图4为本发明提出的一种具有纵向NPN结构的双栅LDMOS器件结构，如图所示，一种具有纵向NPN结构的双栅LDMOS器件，包括第一区域和第二区域，所述第一区域与第二区域镜像对称；所述第一区域包括P-衬底1、有源顶层硅、横向多晶硅栅11、纵向多晶硅栅12(包括纵向栅氧10和纵向栅氧10所包围的导电介质22)、源电极区、漏电极区和场氧层5；所述有源顶层硅包括自上而下纵向排列的上层N型硅条15、中层P型硅条16及下层N型硅条17，所述源电极区包括设置在场氧层5内的源电极4、横向沟道源N+区7、纵向沟道源N+区8和源P+区9，其中横向沟道源N+区7和纵向沟道源N+区8位于源P+区9的左右两侧，所述横向沟道源N+区7、纵向沟道源N+区8和源P+区9三者并排设置于上层N型硅条15中且三者同时与源电极4下表面接触；所述漏电极区包括设置在场氧层5内的漏电极3和设置在上层N型硅条15中的漏N+区6，所述漏N+区6与漏电极3的下表面接触，所述横向多晶硅栅11设置在场氧层5内且与场氧层的下表面分离，所述源电极和漏电极设置在横向多晶硅栅的左右两侧，所述上层N型硅条中还设置有与中层P型硅条接触的P阱14，所述P阱14分别与横向沟道源N+区7、纵向沟道源N+区8、源P+区9以及场氧层5的下表面接触；所述纵向多晶硅栅12纵向伸入有源顶层硅中并分别与源电极4、纵向沟道源N+区8、P阱14、中层P型硅条16及下层N型硅条17接触；所述漏N+区6的下表面还设置有伸入上层N型硅条的N阱13，所述N阱13分别与中层P型硅条16、下层N型硅条17接触。
本发明的工作原理：下面以图4提出的一种具有纵向NPN结构的双栅LDMOS器件结构，对所提出的新器件结构的工作机理进行详细说明。当其漏电极3端外加一个高电压Vd，而源电极4及衬底电极2接地，横向多晶硅栅11加合适正电压，横向沟道打开，即位于上层N型硅条15内形成载流子通路；若纵向多晶硅栅12加合适正电压，则纵向沟道打开，即穿过P阱14、中层P型硅条16接触于底层N型硅条17形成载流子通路。当两个栅电极都加电压时，两个沟道同时打开，则载流子从漏极到源极有两条通路，相当于采用了并联的形式，因而降低了导通电阻。关态时，由于采用NPN结构，中层P型硅条16辅助耗尽上层N型硅条15及下层N型硅条17，在优化横向电场的同时可使得上下N型硅条掺入较高浓度杂志，进一步降低导通电阻。
所述有源顶层硅硅、Si、SiC、GaN半导体材料中的一种或多种。
本发明所提出的结构还可应用于SOI衬底上，当应用于SOI衬底上时，本发明所提出的结构还包括SOI衬底埋氧层，所述SOI衬底埋氧层设置于埋于整个P-衬底硅层表面和有源顶层硅之间；介质埋层可为SiO2和/或Si3N4。
所述SOI衬底埋氧层还设置有半导体窗口。
以上所述仅为本发明的优选实施例，并不用于限制本发明，显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
Claims (4)
1.一种具有纵向NPN结构的双栅LDMOS器件，其特征在于：包括第一区域和第二区域，所述第一区域与第二区域镜像对称；所述第一区域包括P-衬底（1）、有源顶层硅、横向多晶硅栅（11）、纵向多晶硅栅（12）、源电极区、漏电极区和场氧层（5）；所述有源顶层硅包括自上而下纵向排列的上层N型硅条（15）、中层P型硅条（16）及下层N型硅条（17），所述源电极区包括设置在场氧层（5）内的源电极（4）、横向沟道源N+区（7）、纵向沟道源N+区（8）和源P+区（9），其中横向沟道源N+区（7）和纵向沟道源N+区（8）位于源P+区（9）的左右两侧，所述横向沟道源N+区（7）、纵向沟道源N+区（8）和源P+区（9）三者并排设置于上层N型硅条（15）中且三者同时与源电极（4）下表面接触；所述漏电极区包括设置在场氧层（5）内的漏电极（3）和设置在上层N型硅条（15）中的漏N+区（6），所述漏N+区（6）与漏电极（3）的下表面接触，所述横向多晶硅栅（11）设置在场氧层（5）内且与场氧层的下表面分离，所述源电极和漏电极设置在横向多晶硅栅的左右两侧，所述上层N型硅条中还设置有与中层P型硅条接触的P阱（14），所述P阱（14）分别与横向沟道源N+区（7）、纵向沟道源N+区（8）、源P+区（9）以及场氧层（5）的下表面接触；所述纵向多晶硅栅（12）纵向伸入有源顶层硅中并分别与源电极（4）、纵向沟道源N+区（8）、P阱（14）、中层P型硅条（16）及下层N型硅条（17）接触；所述漏N+区(6)的下表面还设置有伸入上层N型硅条的N阱（13），所述N阱（13）分别与中层P型硅条（16）、下层N型硅条（17）接触。
2.根据权利要求1所述的具有纵向NPN结构的双栅LDMOS器件，其特征在于：所述纵向多晶硅栅包括纵向栅氧（10）和纵向栅氧（10）所包围的导电介质（22）。
3.根据权利要求1所述的具有纵向NPN结构的双栅LDMOS器件，其特征在于：还包括SOI衬底埋氧层，所述SOI衬底埋氧层设置于埋于整个P-衬底和有源顶层硅之间。
4.根据权利要求3所述的一种具有纵向NPN结构的双栅LDMOS器件，其特征在于：所述SOI衬底埋氧层还设置有半导体窗口。
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