Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/148—Charge coupled imagers
  • H01L27/14806—Structural or functional details thereof
  • H01L27/14812—Special geometry or disposition of pixel-elements, address lines or gate-electrodes
  • H01L27/14818—Optical shielding
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
  • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/148—Charge coupled imagers
  • H01L27/14831—Area CCD imagers
  • H01L27/14843—Interline transfer

Definitions

• the present invention relates to the field of integrated image sensors and, more particularly, sensors allows ⁇ a good detection at low illumination. Presentation of the prior art
• image capture devices are known.
• the most common structure of these sensors comprises a plurality of elementary detection devices or pixels, each comprising a photodiode formed in a semiconductor substrate, associated with a charge transfer device and a charge reading circuit that has been transferred. It is generally sought to minimize the number of sensor elements by using a read circuit for several photodiodes.
• incident photons penetrate the semiconductor substrate and form electron-hole pairs in the substrate. The electrons of these pairs are then captured by the photodiode and then transferred by the charge transfer transistor to the associated readout circuit.
• US patent application 2007/0176213 describes a structure comprising, in addition to the aforementioned elements, devices, associated with each pixel, allowing the amplification of photogenerated electrons in this pixel to improve the sensitivity of the sensors.
• CCD registers charge transfer device
• Figure 1 illustrates a pixel of an image sensor comprising a charge multiplication stage and 2A to 2E are potential curves illustrating the functioning ⁇ that pixel during different steps of the detection.
• the pixel of FIG. 1 is formed in and on a P-type substrate 10 biased to a reference voltage, for example ground.
• a photodiode consisting of a heavily doped N-type region (N +).
• the photodiode is illuminated by a light beam 13.
• an isolated transfer gate 14 controlled by a transfer signal V ⁇ .
• Next to the transfer gate 14 are formed several isolated grids for the multiplication of charges by avalanche effect.
• FIGS. 2A to 2E illustrate the potential in the substrate 10, in the plane of FIG. 1, during different stages of the image capture. In these figures, a single cycle of storage, transfer and multiplication of electrons is described. The potential illustrated in each of these figures is the potential in the substrate 10 along a line that is will call later "line of maximum potential". This line passes, deep in the substrate, by the points of strongest polarization opposite isolated grids and in the photodiode.
• the maximum polarization line passes through more or less deep points in the substrate. Note that, in the following description, we will call the grid 16 "first multiplication grid" although this grid also plays a role during the initial transfer step.
• FIG. 2A shows the potential curve in the photodiode 12 and in the substrate 10 during an initial charge storage phase in the photodiode 12.
• the illumination of the sensor of FIG. 1 causes the storage of electrons in the region 12 and the potential of this region, initially equal to V ] _, decreases to reach a value V2 which is a function of the number of electrons stored and therefore the number of incident photons.
• V ⁇ applied to the transfer gate is zero to form a potential wall and to prevent electrons from coming out of the photo ⁇ diode 12.
• the potential ⁇ l, associated with the first multiplication grid of Charges 16 is, preferably just before the transfer step, set at a voltage V3, greater than V ] _, in anticipation of the next step.
• Vr j substantially equal to or slightly greater than V ] _, is applied to the transfer gate 14, while the voltage ⁇ l applied to the first charge multiplication gate 16 is equal to V3 (greater than V ] _ and that the voltage ⁇ 2 applied to the second multiplication gate 18 is zero.
• the charges stored in the photodiode 12 are thus transferred ⁇ into the potential well formed in the substrate 10, below the first multiplication grid 16.
• the voltage V ⁇ (transfer gate) returns to a reference potential while the voltage ⁇ 2 remains at this reference potential, for example equal to zero, which blocks the electrons in the region of the substrate 10 located under the gate 16.
• a new charge storage phase can then begin at the photodiode 12.
• a the step illustrated in Figure 2D decreases the voltage ⁇ l applied to the gate 16 to a low voltage V4. The potential of the substrate 10 located below the gate 16 is thus lowered.
• the voltages Vr j and ⁇ 2 applied, respectively, to the gates 14 and 18, are zero (reference potential).
• the voltage ⁇ 3 applied to the gate 20 is set to a voltage V5 much higher than the voltage V4, in anticipation of the next step.
• the voltage ⁇ 2 applied to the gate 18 increases rapidly to be of the order of the voltage V4, or slightly higher than V4. Since the voltage ⁇ 3 is equal to V5 (much higher than V4), the charges are transferred to the region of the substrate situated under the gate 20. The potential difference between the region located under the gate 18 ( ⁇ V4) and under the gate 20 (V5) is sufficiently high to allow ⁇ multiplication of charges by electronic avalanche.
• the gate 22 is biased to a zero voltage to form a potential wall and block the charges at the gate 20.
• the voltage V4 may be of the order of 1 V and the 10 V V5 voltage.
• the charge transfer step ( Figure 2B) may also participate in the amplifica ⁇ tion thereof, the voltage applied to the gate 16 during this step then being adapted to produce a multiplication (high voltage).
• An object of an embodiment of the present invention is to provide an image sensor allowing good detection during low illumination.
• one embodiment of the present invention provides a unit device of an image sensor include an ⁇ ing a photodiode consisting of a doped region of a first conductivity type formed on the surface of a semiconduc- tor substrate a second type of conductivity adapted to be polarized at a first reference voltage, the photodiode being associated with a device for transferring, multiplying and isolating charges, the photodiode being of the completely depleted type and comprising, on the surface of the doped zone of the first conductivity type, a highly doped region of the second conductivity type adapted to be biased to a second reference voltage.
• the device for transferring, multiplying and isolating charges comprises a transfer gate, an isolation gate and a plurality of multiplication gates adapted to be polarized so as to fix the gate. potential of the underlying substrate and allow the transfer, isolation and multiplication of charges by electronic avalanche effect.
• the device for transferring, multiplying and isolating charges comprises at least five grids.
• the first and second reference voltages are equal and are ground voltages.
• a doped layer of the first type of conductivity is formed, on the surface of the substrate, facing the transfer gates, isolation and multiplication charges.
• the device further comprises an optical mask formed on the device for transferring, multiplying and isolating the charges.
• the substrate is thinned and is intended to be illuminated by the face opposite to that on which is formed the device for transferring, multiplying and isolating charges.
• the first type of conductivity is the type N.
• the present invention also provides an image sensor comprising a plurality of elementary devices as above.
• FIG. illustrates a conventional charge amplification image sensor
• FIGS. 2A to 2E are potential curves illustrating the operation of the device of FIG. 1 when it is subjected to a large illumination
• FIG. 3 shows the structure of FIG. 1
• FIGS. 4A to 4C are potential curves illustrating a problem likely to be posed by this structure in the absence or at low level of illumination
• Fig. 5 illustrates an image sensor according to an embodiment of the present invention
• Figures 6 and 7 are potential curves in the sensor of Figure 5
• Figure 8 illustrates a variant of a device according to an embodiment of the present invention.
• FIG. 3 shows the structure of FIG. 1, in a case of almost zero illumination (no light beam 13).
• the device comprises a photodiode 12 consisting of a strongly doped N-type region (N +) formed on the surface of a P-type substrate 10, an insulated transfer gate 14 formed on the surface of the substrate 10 and controlled by a transfer signal.
• FIGS. 4A to 4C are curves of the potential in the substrate 10, along lines of maximum potential, during different stages of operation of the device of FIG. 3.
• FIG. 4A illustrates the potential in the substrate 10 during a succession of storage and charge transfer steps (the potential V 1 of the gate 14 varying between zero and
• V ] _ When the illumination of the photodiode is zero, no electron / hole pair is created and the potential of the photodiode should theoretically remain constant. However, it turns out that it increases gradually over the cycles of storage / transfer, up to, in the example shown, a voltage V ] _ '( Figure 4B).
• the increase of the potential in the photodiode, during a succession of cycles in the absence or at a very low level of illumination, is due to a leakage current between the strongly doped N-type photodiode 12 and the charging zone. of space located opposite the gate 16.
• the transfer is distorted due to the variation of the potential during the period without illumination of the photodiode (transferring fewer charges than there were actually stored in the photodiode 12).
• the reading of the charges carried out by the device of FIG. 3 is not good.
• the inventors propose to use a particular photodiode and, more particularly ⁇ , a photodiode in which the potential of the electron capture region can not rise above a predetermined threshold. In this way, the photogenerated charges can be correctly read, even in cases of low illumination.
• Figure 5 illustrates such a photodiode.
• the inven ⁇ tors suggest using a photodiode and clamped completely depleted (in English fully-depleted photodiode, or pinned photodiode).
• the photodiode is formed in a P-type substrate and comprises an N-type doped capture region 32 at the surface of which extends a P-type (P +) strongly doped thin-film region 34.
• the substrate 30 is biased at a first reference potential V re - Q and the heavily doped P-type region 34 is biased at a second reference potential, V re f2.
• the first and second reference potentials, V re -Q and V re f2 may be equal and correspond to a ground voltage, but it will be noted that it is also possible to bias the substrate 30 and the region 34 to voltages. different reference numbers.
• the photodiode is associated with a transfer gate 36, charge multiplication gates 38, 40, 42, and an isolation gate 44 formed on the surface of the substrate 30, in the vicinity of the photodiode.
• the gates 36, 38, 40, 42, 44 have insulated gate structures and are controlled respective ⁇ , for V ⁇ control signals, ⁇ l, ⁇ 2, ⁇ 3, ⁇ 4.
• a protective layer (not shown), or optical mask, above the transfer gate 36, amplification grids or multiplication 38, 40, 42 and the isolation grid 44, so that incident light beams do not generate charges in the substrate located under these grids.
• the doping of the zones 32 and 34 are adjusted so that the heavily doped region 34 of P-type full ⁇ depleted zone 32 of N-type
• the potential of the zone 32 is fixed only by the doping of the photodiode and the substrate, which avoids the low inversion regime when the charges are transferred to the substrate situated opposite the gate 38. It will be noted that, contrary to what is shown in FIG. 5, in a real device, most of the surface of each pixel is assigned to the photodiode (detection zone of the device).
• the potential in the heart of the N-type region 34 is completely determined by the doping of the regions 30, 32, 34 and, thus, the region 32 reaches at most a potential V ] _ max .
• FIG. 7 illustrates a potential curve identical to that represented in FIG. 4A (along the line of maximum potential) in the case of the device of FIG. 5.
• the potential of the region 32 always remains equal to or less than V ] _ max .
• all photogenerated charges stored in the photodiode are transferred during a transfer phase where the voltage V ⁇ it switches to a voltage V4 equal to or slightly greater than V ] _ max , which makes the sensor effective even in the case of very low illumination or after a long period of zero illumination.
• a charge amplification cycle is performed in a conventional manner, by applying a large electric field between two adjacent gates.
• the gain of the amplification is adjusted by controlling the number of back and forth under the grids 38, 40 and 42.
• the transfer gate 36 and the isolation grid 44 then serve as potential walls to prevent charges from being lost. exit the device during the amplification of the loads.
• Grids 38 and 42 are alternately polarized to create large potential differences enabling the electronic avalanche effect. Note that it will also be possible to form the device for transferring, amplifying and isolating charges by combining more than five neighboring grids.
• a thin N-type doped layer 46 may be formed, on the surface of the substrate 30, facing the transfer gate 36, of multiplication 38, 40, 42 and of isolation 44.
• This thin layer 46 makes it possible to move the maximum potential point slightly away from the surface of the substrate in order to avoid parasitic phenomena (noises) often present at the interfaces between the gate insulator and the semiconductor substrate.
• FIG. 8 illustrates a variant of the device of FIG. 5 in which the image sensor is illuminated by the rear face of the substrate 30.
• the device of FIG. 8 differs from that of FIG. 5 in that the substrate 30 is thinned. and is illuminated by the face opposite that on which are formed the transfer gate 36, the multiplied grids ⁇ cation loads 38, 40, 42 and the isolation gate 44.
• a light beam 48 reaching the substrate generates electron pairs / holes and the electrons of these pairs are collected in the potential well formed by the photodiode 32.
• a beam arriving through the rear face of a substrate encounters less power. obstacles and is more easily detectable than a beam arriving on the front face of the substrate.
• the operation of this device is then similar to that described above.
• the devices of Figures 5 and 8 may also be used in the case of high levels of illumination. In this case, it is possible to adapt the integration time, or accumulation of charges, in the photodiode as a function of the illumination, using a suitable electronic circuit, to avoid the saturation of the pixel .

Landscapes

• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Electromagnetism (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Solid State Image Pick-Up Elements (AREA)
• Transforming Light Signals Into Electric Signals (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=41381729

Family Applications (1)

Country Status (5)

Families Citing this family (5)

Family Cites Families (6)

• 2009
  • 2009-05-14 FR FR0953192A patent/FR2945667B1/fr not_active Expired - Fee Related
• 2010
  • 2010-05-11 JP JP2012510344A patent/JP2012527106A/ja active Pending
  • 2010-05-11 US US13/319,782 patent/US20120119264A1/en not_active Abandoned
  • 2010-05-11 EP EP10731767A patent/EP2430659A1/de not_active Withdrawn
  • 2010-05-11 WO PCT/FR2010/050919 patent/WO2010130950A1/fr active Application Filing

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events