EP2013917A1 - Corps semi-conducteur émetteur de rayonnement avec un substrat de support et son procédé de fabrication - Google Patents

Corps semi-conducteur émetteur de rayonnement avec un substrat de support et son procédé de fabrication

Info

Publication number
EP2013917A1
EP2013917A1 EP07722350A EP07722350A EP2013917A1 EP 2013917 A1 EP2013917 A1 EP 2013917A1 EP 07722350 A EP07722350 A EP 07722350A EP 07722350 A EP07722350 A EP 07722350A EP 2013917 A1 EP2013917 A1 EP 2013917A1
Authority
EP
European Patent Office
Prior art keywords
carrier substrate
semiconductor layer
radiation
semiconductor
layer stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07722350A
Other languages
German (de)
English (en)
Inventor
Volker HÄRLE
Zeljko Spika
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP2013917A1 publication Critical patent/EP2013917A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the invention relates to a radiation-emitting semiconductor body with a carrier substrate and to a method for producing the same.
  • Carrier substrate wafer possible, which run so that each of the sections through the semiconductor layer sequence and by the carrier substrate wafer, which limit the semiconductor body on one side, in a common plane or surface or, in other words, represent a single cut.
  • the mutually facing surfaces of the semiconductor layer stack and the associated carrier substrate then necessarily have the same dimensions are arranged flush.
  • Such semiconductor bodies are usually electrically contacted with a bonding pad arranged on the radiation decoupling surface.
  • the bondpad it may be desirable to arrange it not on the semiconductor layer stack, but on the carrier substrate.
  • the semiconductor layer stack comprises the Carrier substrate not completely covered.
  • the document DE 103 39 985 A1 specifies a semiconductor body in which a semiconductor layer stack is arranged on a carrier substrate which has a larger base area than the semiconductor layer stack. Such semiconductor bodies can not be produced in the wafer composite by conventional methods.
  • An object of the present invention is to provide a simplified and cost-effective method for producing radiation-emitting semiconductor bodies with a carrier substrate.
  • a further object of the present invention is to provide a radiation-emitting semiconductor body with a carrier substrate, which has the largest possible radiation exit area and can be inexpensively manufactured and simply contacted.
  • a method according to the invention for producing a plurality of radiation-emitting semiconductor bodies with a carrier substrate comprises in particular the steps of: providing a carrier-substrate wafer; - forming a semiconductor layer sequence that is suitable "for generating electromagnetic radiation;
  • the structured connection is carried out such that at least one semiconductor layer stack is connected to exactly one associated carrier substrate;
  • At least one section through the carrier substrate wafer of any of the sections through the semiconductor layer sequence is extended such that there is a straight cut through the carrier substrate wafer and the semiconductor layer sequence.
  • the semiconductor layer sequence preferably comprises a pn junction, a double heterostructure, a single quantum well or more preferably a multiple quantum well structure (MQW) for generating radiation.
  • quantum well structure does not contain any information about the dimensionality of the quantization. It thus includes quantum wells, quantum wires and quantum dots and any combination of these structures. Examples of MQW structures are described in the publications WO 01/39282, US 5,831,277, US 6,172,382 Bl and US 5,684,309, the disclosure content of which is hereby incorporated by reference.
  • the structured connection is carried out such that a plurality of semiconductor layer stacks is respectively connected to exactly one associated carrier substrate. Particularly preferably, each semiconductor layer stack is connected to exactly one associated carrier substrate.
  • the semiconductor layer sequence does not have to be directly adjacent to the carrier substrate wafer. Rather, one or more further layers, for example a connection layer, can be arranged between the semiconductor layer sequence and the carrier substrate wafer.
  • the method makes use of the idea that a structured connection between a semiconductor layer sequence and a carrier substrate wafer can be produced.
  • the composite comprising the semiconductor layer sequence and the carrier substrate wafer is subsequently structured to form individual semiconductor bodies, which each comprise a semiconductor layer stack and a carrier substrate. This can be done, for example, by cuts through the semiconductor layer sequence and by cuts through the carrier substrate wafer.
  • the projection of at least one section through the carrier substrate wafer into the connection plane contains the projection none of the cuts through the semiconductor layer sequence in this plane completely.
  • connection plane is that plane which contains the connection surface or an area of the connection layer.
  • Sections through the semiconductor layer sequence do not need to cut through the carrier substrate wafer. Neither do cuts through the carrier substrate wafer need to sever the semiconductor layer sequence. Nevertheless, these sections produce individual semiconductor bodies in which the semiconductor layer stack and the associated carrier substrate are advantageously not arranged flush with one another. Rather, semiconductor bodies with a semiconductor layer stack and a carrier substrate can be produced in the wafer composite in which the semiconductor layer stack does not cover a connection region of the carrier substrate in a plan view of the front side of the semiconductor layer stack facing away from the carrier substrate and / or in which the carrier substrate is viewed in plan view from that of FIG
  • Semiconductor layer sequence used to produce semiconductor layer stack Apart from the loss through the cuts and possibly. an edge of the semiconductor layer sequence which is eliminated due to geometric conditions - for example, in the production of semiconductor bodies having a rectangular base area of a semiconductor layer sequence with a circular base area - Preferably no material of the semiconductor layer sequence is lost.
  • the number of process and adjustment steps for producing a plurality of semiconductor bodies, in which a connection region of the carrier substrate is not covered by the semiconductor layer sequence, is particularly small.
  • the connection plane Preferably, in at least one semiconductor body, but preferably in a plurality of semiconductor bodies, particularly preferably in all semiconductor bodies produced by the method, there is at least one offset direction contained in the connection plane.
  • adjacent sections are offset from one another by the semiconductor layer sequence and by the carrier substrate wafer.
  • the side surfaces produced by the cuts which delimit a semiconductor layer stack and the associated carrier substrate in plan view along this direction, are then shifted in the offset direction from one another.
  • the projections of the offset sections or side surfaces in the connection plane then do not touch or intersect.
  • the offset direction is parallel to the distance vector between the projections.
  • adjacent sections may be formed differently by the semiconductor layer sequence and by the carrier substrate wafer. For example, they can be curved differently and / or at least one of the cuts can be guided over the corner. Then, it may happen that the side surfaces of the semiconductor layer stack and the associated carrier substrate of a semiconductor body which delimits from these sections is shifted in places against each other and in places are flush.
  • the growth of the semiconductor layer sequence takes place along the surface normal of the connection plane pointing to the front side of the semiconductor layer sequence facing away from the carrier substrate.
  • This surface normal is called the "growth direction".
  • growth direction due to certain process conditions, for example, there may be slight deviations from the direction designated as growth direction or variations in the direction of the actual layer growth.
  • the growth direction also corresponds to the main emission direction of the semiconductor bodies.
  • the radiation generated by the semiconductor bodies during operation is coupled out through the carrier substrate wafer.
  • the sections are expediently guided in such a way that the semiconductor body has a step which is formed by the semiconductor layer stack and the carrier substrate.
  • the semiconductor layer stack therefore covers the side of a first region of the carrier substrate facing it, while the surface facing the semiconductor layer stack covers a Terminal region of the carrier substrate is free from the semiconductor layer stack.
  • the semiconductor layer stack of at least one semiconductor body may have a first partial area which, essentially parallel to the connection plane, transitions over protrudes the edge of the carrier substrate.
  • the semiconductor body then has a second step, which is formed by the semiconductor layer sequence and the carrier substrate, such that the first subregion of the semiconductor layer stack represents an overhang, which is located in an offset direction next to the carrier substrate.
  • the composite comprising the semiconductor layer sequence and the carrier substrate wafer is provided with at least one pair of mutually offset sections, which on the one hand faces away from the carrier substrate wafer side of the semiconductor layer sequence and on the other side facing away from the semiconductor layer sequence side of the carrier substrate wafer, preferably along and against Growth direction, led, subdivided. Only together with a region left free of the structured connection in the connection plane does this produce at least one coherent "cut” which, viewed from the side of the carrier substrate wafer facing away from the semiconductor layer sequence, first cuts through the carrier substrate wafer, then kinks and subsequently parallel to the connection plane along an offset direction, runs before it kinks again and, preferably in the growth direction, cuts through the semiconductor layer sequence.
  • sections may be prepared by the semiconductor layer sequence and the carrier substrate, which extend parallel to the direction of displacement, • be arranged in a common plane, so that they together form a straight continuous section of the semiconductor layer sequence and the carrier substrate wafer.
  • Sections through the semiconductor layer sequence and through the carrier substrate wafer, which do not run parallel to the offset direction, may for example be offset from one another and / or have different curvatures, so that in at least one semiconductor body, the semiconductor layer stack does not cover a connection region of the associated carrier substrate, and preferably has a first subregion which protrudes beyond the edge of the carrier substrate in this direction. Particularly preferably, these sections are perpendicular to the offset direction.
  • first and a second offset direction both lying in the connection plane and preferably perpendicular to one another.
  • at least one pair of sections is then offset from one another in the first offset direction by the semiconductor layer sequence and by the carrier substrate wafer, and at least one further pair of sections through the semiconductor layer sequence and through the carrier substrate wafer are offset from one another in the second offset direction.
  • the semiconductor body is in this case the Semiconductor layer stack shifted in the first and in the second offset direction against the associated carrier substrate.
  • the cuts are made such that none of the cuts through the semiconductor layer sequence is completely contained in one of the regions defined by the imaginary continuation of a cut in the carrier substrate to the front of the semiconductor layer sequence.
  • the sections through the semiconductor layer sequence and / or through the carrier substrate wafer may also be used to subdivide the one, several or all of the further layers.
  • Semiconductor layer sequence not the carrier substrate wafer and cuts through the carrier substrate wafer do not separate the semiconductor layer sequence unless they together form a straight line cut.
  • the cuts through the carrier substrate wafer and / or through the semiconductor layer sequence are preferably carried out by means of sawing and / or by means of other suitable mechanical (for example milling) or chemical (for example dry etching) material-removing processes.
  • the cuts are made by means of a material-removing laser process.
  • the term "cut” covers all trenches which are produced before or after the connection of the semiconductor layer sequence and at least partially sever the semiconductor layer sequence or the carrier substrate wafer and thereby - optionally together with points not connected by the structured connection in the connection plane - in semiconductor layer stack or Subdivide carrier substrates.
  • the production of the structured connection first comprises a full-area connection of the semiconductor layer sequence to the carrier substrate wafer. Subsequently, the full-surface connection is partially resolved again.
  • a sacrificial layer is produced.
  • the sacrificial layer is preferably adjacent to the bonding layer or surface by means of which the full-area connection is made.
  • the partial release of the connection between the carrier substrate wafer and the semiconductor layer sequence preferably takes place by partial damage or destruction of the sacrificial layer.
  • a layer serving primarily for a different purpose may also be suitable as a sacrificial layer and identified and used as such.
  • the partial release of the connection takes place by means of laser radiation.
  • the sacrificial layer is expediently carried along by the carrier substrate wafer Laser radiation irradiated.
  • Suitable materials for a sacrificial layer preferably have a suitable, in particular small, bandgap and / or low chemical stability and comprise, for example, GaN, InGaN or other nitride compound semiconductor materials.
  • the irradiation takes place primarily at those points where the connection is to be released.
  • the mask need not be connected to the carrier substrate wafer. Alternatively, however, it can also be applied to the carrier substrate wafer.
  • the mask is irradiated areally or sequentially, for example by moving a line-shaped radiation source relative to it.
  • An alternative to radiation through a mask is to use at least one laser beam with a sufficiently small beam cross-section, which is moved relative to the carrier substrate and thereby decomposes the sacrificial layer according to the desired structure and in this way the not connected to the carrier substrate areas of the semiconductor layer sequence generated.
  • no complete connection between the semiconductor layer sequence and the carrier substrate wafer is produced from the beginning. Instead, the semiconductor layer sequence and the carrier substrate wafer are connected to one another only in places, primarily only those regions in which the semiconductor layer stack and the carrier substrate overlap in the later semiconductor bodies.
  • connection between the carrier substrate wafer and the semiconductor layer sequence can be produced, for example, by means of a connection layer. This can be formed on the carrier substrate wafer or on the semiconductor layer sequence.
  • the connecting layer has, for example, a solder layer, which in particular comprises or consists of a solder such as Au, AuSn, Pd, In and / or Pt.
  • a solder layer which in particular comprises or consists of a solder such as Au, AuSn, Pd, In and / or Pt.
  • an adhesive layer for example based on an epoxy resin, is conceivable as a bonding layer.
  • connection layer can be provided which imparts the adhesion via a diffusion process.
  • germanium-gold layers, metal oxide or metal nitride layers and / or dielectric layers are suitable for this purpose.
  • the latter may for example contain or consist of SiO, SiN and / or TiN.
  • ayogge fürlose connection ie a connection to a Connecting surface but without a connection layer between the carrier substrate wafer and the semiconductor layer sequence, provided.
  • the adhesion between the carrier substrate wafer and the growth-adjacent surface is then mediated, for example, by electrostatic forces and / or by diffusion, which may, for example, result in the formation of a eutectic.
  • an electrical voltage can be applied between the semiconductor layer sequence and the carrier substrate wafer, and / or heat can be supplied to the carrier substrate wafer and / or the semiconductor layer sequence.
  • the partial connection preferably takes place by means of a soldering process.
  • the solder layer according to the desired pattern of the connection layer is already structured on the main surface of the carrier substrate wafer to be connected to the semiconductor layer sequence or on the rear side of the semiconductor layer sequence facing the carrier substrate wafer.
  • the structuring is preferably achieved by means of a mask, through which the solder is applied, for example by vapor deposition or sputtering.
  • the solder is applied over the entire surface and structured in a subsequent method step, which comprises, for example, a lithographic process.
  • a structured adhesive surface or the production of a structured, fichtge Anlagen connection for example by anodic bonding, such as by anodic bonding of a patterned layer, in particular a structured electrically conductive layer such as a metal layer, is possible.
  • Subsections of the semiconductor layer sequence may arise in the method according to the invention, such as edge regions of the semiconductor layer sequence and / or regions between the semiconductor layer stacks provided for the semiconductor bodies, which are not part of the desired semiconductor bodies and in the present case are not referred to as semiconductor layer stacks. These are preferably not even connected to the carrier substrate wafer or, after bonding, for example, after a full-area connection of semiconductor layer sequence and carrier substrate wafer, released again from the carrier substrate wafer. After forming the cuts through the semiconductor layer sequence and through the carrier substrate wafer to define the
  • semiconductor layer stack these subregions are then preferably removed.
  • regions of the semiconductor layer sequence can be connected to parts of the carrier substrate wafer that do not represent carrier substrates-for example with edge regions of the carrier substrate wafer.
  • the method is preferably carried out in this way, ie the semiconductor layer sequence is subdivided into sections such that the subareas of the semiconductor layer sequence not used for semiconductor bodies make up as small a proportion as possible of the entire semiconductor layer sequence.
  • semiconductor bodies in which in each case part of the surface of the carrier substrate facing the semiconductor layer stack is not covered by the semiconductor layer stack can advantageously be produced in the wafer composite.
  • the method advantageously allows a very good utilization of the available semiconductor layer sequence, whereby a cost-effective production of the semiconductor body can be ensured.
  • a contact layer preferably at least partially radiation-permeable, is applied to a semiconductor body, which at least partially covers a surface of its semiconductor layer stack facing away from the carrier substrate and at least part of the connection region of its carrier substrate, that is, the region not overlapping with the semiconductor layer stack ,
  • the contact layer preferably covers substantially the entire surface of the semiconductor layer stack facing away from the carrier substrate.
  • the contact layer is pulled from the front side of the semiconductor layer stack over at least one side surface onto the connection region of the carrier substrate.
  • the contact layer thus preferably also covers at least one side surface of the semiconductor layer stack at least partially.
  • the contact layer in several parts.
  • portions of the contact layer may be sequentially formed, for example, when applied to areas that are not parallel to one another.
  • a partial region of the contact layer which is also formed in particular on the front side of the semiconductor layer stack, has a material which is at least partially permeable to electromagnetic radiation, while another partial region is substantially radiation-impermeable.
  • subregions of the contact layer adjoin one another or overlap, so that they are electrically conductively connected.
  • the contact layer or a partial region of the contact layer preferably comprises or consists of a transparent conductive oxide (TCO), in particular indium tin oxide (ITO), and / or a conductive polymer.
  • TCO transparent conductive oxide
  • ITO indium tin oxide
  • the contact layer can be deposited, for example, directly on the semiconductor body. Alternatively, it may for example be applied to a carrier foil and subsequently laminated onto the semiconductor body. If the contact layer is, for example, a conductive polymer, the contact layer itself can be a film and in particular be laminated onto the semiconductor body.
  • a first electrically insulating layer is applied to at least part of the connection region of the carrier substrate prior to the formation of the contact layer. This is especially true at an electrically conductive carrier substrate in order not to electrically short the semiconductor layer stack.
  • a second electrically insulating layer is applied to this side surface, preferably at least in the region of the contact layer.
  • the first and / or the second electrically insulating layer may, for example, comprise a silicon oxide and / or a silicon nitride, such as SiO 2 , SiN or SiO x N 7 . It can also be a plastic or polymer layer. Preferably, it is then laminated or sprayed on. If the contact layer is applied to a carrier foil or if the contact layer is a foil, the first and / or the second electrically insulating layer can also be applied to these. Then, the first and / or second electrically insulating layer is preferably applied to the semiconductor body together with the contact layer, in particular laminated. These process steps are described for example in the document DE 103 39 985 A1, the disclosure content of which is hereby incorporated by reference.
  • the first and the second electrically insulating layer can be produced in one piece, for example, by pulling the second electrically insulating layer from a side surface of the semiconductor layer stack as a first electrically insulating layer onto the connection region of the carrier substrate. This is particularly useful if, for example, the contact layer is applied to a carrier foil or represents a foil.
  • a first and / or a second electrical connection layer for example a bonding pad, is formed on the connection region of the carrier substrate.
  • the first and / or second electrical connection layer comprises a metal.
  • the first and / or second electrical connection layer comprises or consists of at least one of the following materials: AuSn, PdIn, Sn, Au, Al, Bi.
  • the first electrical connection layer is preferably arranged on the contact layer and is in this way electrically conductively connected to the front side of the semiconductor layer stack.
  • the second electrical connection layer is preferably electrically conductively connected to the rear side of the semiconductor layer stack facing the carrier substrate.
  • the carrier substrate wafer is electrically sufficiently conductive, it can be arranged directly on the carrier substrate for this purpose and the carrier substrate can act as an electrical connection between the second connection layer and the back side of the semiconductor layer stack.
  • the second connection layer can thereby on the
  • Semiconductor layer stack facing front or on the side facing away from the semiconductor layer stack rear side of the carrier substrate are applied.
  • a sufficiently electrically conductive layer is preferably arranged between the latter and the semiconductor layer sequence, which layer forms the connection region of the Substratwafers at least partially covered and on which then the second connection layer is formed.
  • the electrically conductive layer is preferably applied before the connection of the semiconductor layer sequence to the carrier substrate wafer. It can be applied, for example, structured or structured after application.
  • the electrically conductive layer is expediently applied to the carrier substrate wafer.
  • the electrically conductive layer can be applied both to the semiconductor layer sequence and to the carrier substrate wafer. Expediently, the part of the electrically conductive layer arranged on the connection region of the carrier substrate is uncovered when the connection between the semiconductor layer sequence and the carrier substrate wafer is partially released. If a sacrificial layer is present, the electrically conductive layer preferably adjoins it.
  • the second electrical connection layer can alternatively be formed on the rear side of this first partial region of the semiconductor layer stack.
  • an electrically insulating or not sufficiently conductive Carrier substrate extend the second electrical connection layer on the back of the carrier substrate and cover these partially or completely.
  • the semiconductor body can thus be installed and contacted in conventional device housings in a simple manner, for example by means of conventional die-bonding methods, even in the case of an electrically insulating carrier substrate.
  • the semiconductor layer sequence comprises a growth substrate wafer.
  • the remaining layers of the semiconductor layer sequence are preferably grown epitaxially on the growth substrate wafer.
  • the growth substrate wafer is thinned or removed before or after the connection of the semiconductor layer sequence with the carrier substrate wafer.
  • the semiconductor layer sequence is based on a III / V compound semiconductor material, for example, a nitride compound semiconductor material or a phosphide compound semiconductor material. In another embodiment, the semiconductor layer sequence is based on a II / VI compound semiconductor material.
  • An IIl / V compound semiconductor material comprises at least one element of the third main group such as Al, Ga, In, and a fifth main group element such as for example, B, N, P, As.
  • III / V compound semiconductor material means the group of binary, ternary or quaternary compounds containing at least one element from the third main group and at least one element from the fifth main group, in particular nitride and phosphide compound semiconductors.
  • Such a binary, ternary or quaternary compound may additionally have, for example, one or more dopants and additional constituents.
  • an II / VI compound semiconductor material has at least one element of the second main group such as Be, Mg, Ca, Sr, and a sixth main group element such as O, S, Se.
  • an IL / VI compound semiconductor material comprises a binary, ternary or quaternary compound comprising at least one element from the second main group and at least one element from the sixth main group.
  • Such a binary, ternary or quaternary compound may additionally have, for example, one or more dopants and additional constituents.
  • the II / VI compound semiconductor materials include: ZnO, ZnMgO, CdS, ZnCdS, MgBeO.
  • a nitride compound semiconductor material preferably Al n Ga m In 1 nm N or consists of this, where 0 ⁇ n ⁇ 1, O ⁇ m ⁇ l and n + m ⁇ 1.
  • this material does not necessarily have a mathematically exact composition according to the above formula exhibit. Rather, it may, for example, have one or more dopants and additional constituents.
  • the above formula contains only the essential constituents of the crystal lattice (Al, Ga, In, N), even if these can be partially replaced and / or supplemented by small amounts of further substances.
  • On phosphide compound semiconductor material based in this context means that the semiconductor layer sequence or at least part thereof, particularly preferably at least the active zone and / or the growth substrate, preferably Al n Ga m ini- n -MP or As n Ga m In 1-nm P, where O ⁇ n ⁇ l, O ⁇ m ⁇ l and n + m ⁇ 1.
  • this material does not necessarily have to have a mathematically exact composition according to the above formula, but rather one or more dopants and additional
  • the above formula contains only the essential constituents of the crystal lattice (Al or As, Ga, In, P), even if these may be partially replaced by small amounts of other substances.
  • the carrier substrate wafer preferably comprises sapphire or is sapphire. But it can also be other materials, eg.
  • semiconductor wafers which preferably comprise or consist of GaN or SiC, can be used as carrier substrate wafers.
  • Metal, plastic or glass plates are also suitable as carrier substrate wafers.
  • At least one section through the semiconductor layer sequence and an adjacent section through the carrier substrate wafer which delimit the or the same semiconductor body, by 50 microns or more against each other added. More preferably, they are offset by 100 microns or more against each other.
  • the projections of these sections in the connection plane of semiconductor layer sequence and carrier substrate wafer have a spacing of greater than or equal to 50 ⁇ m, preferably greater than or equal to 100 ⁇ m.
  • the semiconductor body bounded by the cuts then has a connection region of the carrier substrate and / or a first subregion of the semiconductor layer stack which has an extent of greater than or equal to 50 ⁇ m, preferably greater than or equal to 100 ⁇ m, along the first and / or second offset direction.
  • the carrier substrate is placed on a stretchable pad and the stretchable pad is stretched, so that the distances between the semiconductor bodies are increased.
  • the semiconductor bodies are pulled apart when the extensible pad is stretched.
  • the stretchable pad is connected to the semiconductor layer sequence.
  • Semiconductor layer sequence, and the stretchable pad is suitably designed so that it does not dissolve completely when stretching the stretchable pad.
  • the semiconductor body adheres to the stretchable backing during stretching.
  • the adhesion between the semiconductor layer sequence and the extensible support is mediated by means of adhesion, an adhesive layer and / or a lacquer layer.
  • the semiconductor layer sequence is clamped between two stretchable pads, for example, an expandable pad of the front and another of the back of the semiconductor layer sequence is adjacent.
  • the further processing of the semiconductor body is advantageously simplified in this way.
  • the second subregion of a semiconductor body which may be covered by one or more semiconductor layer stacks of adjacent semiconductor bodies before the semiconductor bodies are pulled apart, is at least partially exposed.
  • the semiconductor bodies can then be removed individually from the extensible support in a simple manner.
  • the stretching of the extensible pad takes place substantially parallel to the connection plane between the semiconductor layer sequence and the carrier substrate wafer.
  • the stretchable pad may be sufficient to stretch the stretchable pad only in one direction.
  • the semiconductor layer stack of a semiconductor body protrudes beyond the respectively associated carrier substrate in more than one offset direction-to stretch the extensible underlay in several directions, for example in two mutually perpendicular directions.
  • the strain may be substantially isotropic in the main plane of extension of the stretchable pad.
  • the stretchable pad comprises a film, such as polyethylene.
  • the film on its side facing the semiconductor layer sequence side coated with adhesive.
  • the stretchable pad has or consists of an expanded metal mesh.
  • an expanded metal is usually a lattice-like material whose extensibility is particularly increased by the fact that meshes are formed. It may be an expanded metal to a metal ("expanded metal"), but it can for example also be made of a plastic.
  • An expanded metal mesh can be formed for example by punching or staggered cuts in a material, wherein preferably no material loss occurs and the material is deformed stretching.
  • an expanded metal in addition to its extensibility, has a high dimensional stability, in particular in the direction perpendicular to the plane in which the expansion takes place.
  • the extensibility of a stretched grid can be adjusted selectively by means of suitable design of the grid structure along specific spatial directions, so that the size and direction of the elongation can be adjusted in accordance with the sections through the semiconductor layer sequence and through the carrier substrate wafer.
  • a radiation-emitting semiconductor body comprises a carrier substrate and a semiconductor layer stack which is suitable for generating electromagnetic radiation, wherein
  • the semiconductor layer stack is at least partially disposed over a first region of the carrier substrate, such that a connection region of the carrier substrate free from the Semiconductor layer stack is;
  • the first subregion of the semiconductor layer stack is arranged in a plan view of the semiconductor layer stack, that is to say on the surface of the semiconductor layer stack facing away from the carrier substrate, next to the carrier substrate.
  • the first subregion of the semiconductor layer stack thus represents an overhang relative to the carrier substrate.
  • those areas of the semiconductor layer stack and the carrier substrate which are substantially parallel to the connection plane have substantially the same extent.
  • the semiconductor layer stack and the carrier substrate thus preferably have the same edge lengths in the main extension plane. However, each adjacent side surfaces are not flush with each other in each case, but offset from each other. In other words, the semiconductor layer stack and the carrier substrate are not congruent in plan view of the surface of the semiconductor layer stack facing away from the carrier substrate. Instead, the semiconductor layer stack projects beyond at least one offset direction beyond at least one side surface of the carrier substrate, so that the first subregion of the semiconductor layer stack forms an overhang relative to the carrier substrate.
  • a preferably at least partially radiation-permeable contact layer is applied to the semiconductor body, which covers at least in part a surface of the semiconductor layer stack facing away from the carrier substrate and at least a part of the connection region of the carrier substrate. In any case, the contact layer preferably covers substantially the entire surface of the semiconductor layer stack facing away from the carrier substrate.
  • the contact layer is drawn from the front side of the semiconductor layer stack over at least one side surface onto the connection region of the carrier substrate.
  • the contact layer thus preferably also covers at least one side surface of the semiconductor layer stack at least partially.
  • the contact layer can be designed in several parts. For example, it is possible for a partial region of the contact layer, which is also arranged in particular on the front side of the semiconductor layer stack, to have a material that is at least partially transmissive to electromagnetic radiation, while another partial region is substantially radiopaque. Conveniently, subregions of the contact layer adjoin one another or overlap, so that they are electrically conductively connected.
  • the contact layer or a partial region of the contact layer preferably contains or consists of a transparent conductive oxide (TCO), for example indium tin oxide (ITO), and / or a conductive polymer, or consists of one of these materials.
  • TCO transparent conductive oxide
  • ITO indium tin oxide
  • a first electrically insulating ⁇ coating is applied to the connection region of the carrier substrate between the carrier substrate and the contact layer, which covers the connection region of the carrier substrate at least in places.
  • the first electrically insulating layer may, for example, prevent a short circuit of the semiconductor layer stack via a conductive carrier substrate and the contact layer.
  • a second electrically insulating layer is preferably applied to the side surface of the semiconductor layer stack, covering the side surface partially or completely, in particular in the region of the contact layer.
  • the first electrically insulating layer arranged on the carrier substrate wafer also extends as a second electrically insulating layer onto the side surface of the semiconductor layer stack.
  • a first electrical connection layer or the first and a second electrical connection layer can be arranged on the connection region of the carrier substrate.
  • the first electrical connection layer is electrically conductively connected to the front side of the semiconductor layer stack and is preferably arranged on the contact layer.
  • the second electrical connection layer is connected in an electrically conductive manner to the rear side of the semiconductor layer stack.
  • a connection wire may be fastened to the first and / or the second electrical connection layer via which the semiconductor body is supplied with the electrical current necessary for its operation.
  • the arrangement of an electrical connection layer, such as a bond pad, on the front side of the semiconductor layer stack facing away from the carrier substrate is advantageously not necessary. Lead wires also do not need to be routed over the front of the semiconductor layer stack.
  • an optical element arranged downstream of the front side of the semiconductor layer stack can be arranged particularly close to the front side, if no connection wire is guided over it.
  • the second electrical connection layer is preferably arranged on the rear side of the first subregion of the semiconductor layer stack facing the front side and particularly preferably also extends to the rear side of the carrier substrate facing away from the semiconductor layer stack, in particular if, for example, the carrier substrate is not sufficiently electrically conductive.
  • the semiconductor layer stack can thus be electrically contacted in a simple manner.
  • the semiconductor layer stack comprises a growth substrate on which the remaining layers of the semiconductor layer stack are preferably epitaxially grown.
  • the growth substrate may be a bulk substrate or a quasi-substrate.
  • a bulk substrate consists of a uniform material, for example a semiconductor material, which is well suited for growing a semiconductor layer sequence from the materials of the semiconductor layer stack.
  • a quasi-substrate comprises, for example, a carrier and a thin layer of such material applied thereto.
  • the semiconductor layer stack is preferably based on a III / V compound semiconductor material, in particular a phosphide or nitride compound semiconductor material, or on an II / VI compound semiconductor material.
  • the carrier substrate preferably comprises sapphire or is sapphire.
  • the contact layer is at least partially transparent to the electromagnetic radiation generated by the semiconductor layer stack during operation. It may for example consist of a transparent, conductive oxide, in particular indium tin oxide (ITO), or comprise such a material.
  • ITO indium tin oxide
  • an edge of the connection region of the carrier substrate against an adjacent side surface of the semiconductor layer stack is in plan view of the front side of the semiconductor layer stack by 50 microns or more, more preferably by 100 microns or more, added.
  • the extent of the connection region of the carrier substrate in at least one offset direction is greater than or equal to 50 ⁇ m, in particular greater than or equal to 100 ⁇ m.
  • a side surface of the first portion of the semiconductor layer stack and an adjacent edge of the carrier substrate offset by 50 microns or more against each other.
  • the first subregion of the semiconductor layer stack thus has an extension which is greater than or equal to 50 ⁇ m in at least one offset direction.
  • a cavity which is delimited by the first subregion of the semiconductor layer stack, the carrier substrate and by a planar base, is at least partially filled with a filling material according to a further embodiment.
  • the space which is arranged under the overhang formed by the first subregion of the semiconductor layer stack is at least partially filled with a filling material.
  • a filling material may optionally protect a second electrical connection layer applied on the rear side of the first subregion of the semiconductor layer stack and / or a connection wire fastened thereto from mechanical damage.
  • the filler material may be, for example, an epoxy resin, a polychlorinated biphenyl (PCB) or bis-benzo-cyclobutene (BCB).
  • the filling material is particularly preferably thermally adapted to the expansion coefficient of the carrier substrate and / or the semiconductor layer stack.
  • Figures IA to IG 7 are schematic sectional illustration of an optoelectronic semiconductor body at different stages of the first embodiment of a method according to the invention
  • FIGS. 2A and 2B show schematic top views of a plurality of optoelectronic semiconductor bodies in the stages of the method illustrated in FIGS.
  • FIGS. 3A and 3B show schematic sectional representations of an optoelectronic semiconductor body at various stages of the second exemplary embodiment of a method according to the invention
  • FIGS. 4A and 4B show a schematic sectional representation and a schematic plan view, respectively, of an optoelectronic semiconductor body according to the invention, which is produced according to a third exemplary embodiment of a method according to the invention,
  • FIG. 5 a schematic plan view of an optoelectronic semiconductor body according to the invention, which is produced according to a fourth exemplary embodiment of a method according to the invention,
  • FIGS 6A to 6E schematic plan views of differently designed embodiments of optoelectronic semiconductor bodies according to the invention.
  • a semiconductor layer sequence 2 is formed which generates electromagnetic radiation during operation (see Fig. IA).
  • the semiconductor layer sequence 2 is based for example on GaN or another nitride compound semiconductor material and comprises a growth substrate wafer 3, on which the remaining layers of the semiconductor layer sequence 2 are epitaxially deposited.
  • the epitaxial deposition takes place for example by means of chemical vapor deposition (CVD) or physical vapor deposition (PVD) or other suitable epitaxial deposition methods.
  • the semiconductor layer sequence 2 is suitable for emitting light and preferably comprises a pn junction, a double heterostructure, a single quantum well or particularly preferably a multiple quantum well structure (MQW) for generating radiation.
  • quantum well structure does not contain any information about the dimensionality of the quantization. It thus includes u. a. Quantum wells, quantum wires and quantum dots and any combination of these structures. Examples of MQW structures are described in the publications WO 01/39282, US 5,831,277, US 6,172,382 Bl and US 5,684,309, the disclosure content of which is hereby incorporated by reference.
  • the decoupling of the radiation generated during operation of the semiconductor body takes place in the present case essentially through the front 201 of the semiconductor layer sequence 2 facing away from the carrier substrate wafer 1 into the overlying half space, so that the main emission direction 21 indicated by an arrow in FIG.
  • a sacrificial layer 4 for example of InGaN, is applied, which is partially destroyed in a later process step.
  • a carrier substrate wafer 1 which in the present case consists of sapphire.
  • a support substrate wafer 1 made of sapphire has the advantage for the present embodiment that it is at least partially permeable to electromagnetic radiation and has a similar thermal expansion coefficient as the semiconductor layer sequence 2.
  • connection layer 5 is formed on the carrier substrate wafer 1.
  • the growth substrate wafer 3 on the side 302 facing away from the semiconductor layer sequence 2, which is covered by the sacrificial layer 4 is connected to the connection layer 5 formed on the carrier substrate wafer 1.
  • the growth substrate wafer 3 may be thinned or completely removed before or after the connection of the semiconductor layer sequence 2 to the carrier substrate wafer 1.
  • the connection preferably takes place in such a way that the side of the semiconductor layer sequence 2 facing away from the growth substrate wafer 3 is connected to the carrier substrate wafer 1.
  • the radiation generated by the semiconductor bodies during operation can be coupled out by the carrier substrate wafer.
  • connection layer 5 in the present case consists of silicon oxide and / or silicon nitride and the connection can be made by conventional methods for connecting two wafers.
  • an adhesive for example an epoxy resin, or a solder, for example a solder such as Au, AuSn, Pd, In, PdIn or Pt.
  • the semiconductor layer sequence 2 is subdivided into individual semiconductor layer stacks 200 by cuts 6 from their front side 201 facing away from the carrier substrate wafer 1 (compare FIG. 1B).
  • the cuts 6 in the present case also sever the growth substrate wafer 3 and the sacrificial layer 4.
  • the bonding layer 5 is not severed by the cuts 6 through the semiconductor layer sequence.
  • the connection layer 5 is likewise severed by the sections 6 through the semiconductor layer sequence 2. This can bring about advantages, for example, in the subsequent partial release of the connection between growth substrate wafer 3 and carrier substrate wafer 1. Depending on the depth of the cuts 6 through the
  • Semiconductor layer sequence 2 in alternative embodiments of the method, can produce trenches in the connection layer 5 or in the carrier substrate wafer 1, without, however, completely cutting through the carrier substrate wafer 1.
  • the carrier substrate wafer 1 is produced by its rear side 101 facing away from the semiconductor layer sequence 2 by the sections 6 through the
  • Semiconductor layer sequence 2 staggered sections 7 divided into individual carrier substrates 100.
  • the semiconductor layer sequence or through the carrier substrate wafer runs outside the cutting plane shown in FIG. 1B and perpendicular to the sections 6, 7 shown in FIG. 1B (see FIG. 2A), so that carrier substrates and semiconductor layer stacks with a rectangular, preferably square, base surface are formed in the present case.
  • the cuts do not have to be perpendicular to one another, but can also run obliquely with respect to one another at a different angle, so that, for example, semiconductor layer stacks and / or carrier substrates can be produced which have a triangular or parallelogram-like base surface.
  • Adjacent sections 6 through the semiconductor layer sequence and adjacent sections 7 through the carrier substrate wafer have the same spacing according to this embodiment, so that the edge lengths of the carrier substrates 100 and the semiconductor layer stack 200 in the main extension plane are identical. If semiconductor bodies with different dimensions are to be produced, then the intersection distances over the wafer can also vary.
  • the cuts 7 through the carrier substrate wafer 1 also sever the connecting layer 5, but not the sacrificial layer 4.
  • the sacrificial layer 4 is also severed by the cuts 7 through the carrier substrate wafer 1. This can bring advantages, for example, in the subsequent partial decomposition of the sacrificial layer 4.
  • the cuts 7 through the carrier substrate wafer 1 can form trenches in the sacrificial layer 4 or, with the sacrificial layer 4 being severed, in the growth substrate wafer 3, or by severing the sacrificial layer 4 and
  • the cuts 6 through the semiconductor layer sequence and the cuts 7 through the carrier substrate wafer 1 are arranged so that none of the regions which would be occupied by an imaginary continuation of a cut 7 through the carrier substrate wafer 1 to the front side 201 of the semiconductor layer sequence 2, one of the cuts 6th completely contained by the semiconductor layer sequence 2.
  • none of the cuts 6 through the semiconductor layer sequence 2 represents the extension of a cut 7 by the carrier substrate wafer 1 Positions at which a section 7 intersects through the carrier substrate wafer 1 and a section 6 through the semiconductor layer sequence 2, which are not arranged parallel to one another, results in a quasi one-dimensional region 24 (see FIG. 2A) in which both the semiconductor layer sequence 2 as well as the carrier substrate wafer 1 are severed.
  • the sacrificial layer 4 is subsequently irradiated with laser radiation (indicated by the arrows 9) through a mask 8, the carrier substrate wafer 1 and the connection layer 5.
  • the irradiation may alternatively be before dividing the
  • the mask 8 is chosen so that at each
  • Semiconductor layer stack 200 a first portion 210, which is to be detached from the carrier substrate wafer 1, is irradiated, while a second portion 220 is shaded.
  • the second subareas 220 not provided for irradiation are selected such that each of the carrier substrates 100 is still connected to exactly one of the semiconductor layer stacks 200 after the region-wise release of the connection between semiconductor layer stack 200 and carrier substrates 100.
  • the sacrificial layer 4 absorbs part of the laser radiation 9 and is decomposed at the irradiated sites.
  • a laser separation method is described for example in the document WO 98/14986 A1, the disclosure content of which is hereby incorporated by reference.
  • one semiconductor layer stack 200 is connected to exactly one carrier substrate 100.
  • the connection of a semiconductor layer stack 200 with one or more further carrier substrates 100, which are arranged at least partially below the semiconductor layer stack 200, is achieved by the destruction of the sacrificial layer 4.
  • a semiconductor layer stack 200 and its associated carrier substrate 100 together form a semiconductor body 10.
  • Areas 20 of the carrier substrate wafer 1 and regions of the semiconductor layer sequence 2 including growth substrate wafer 3, etc., which are not part of semiconductor bodies 10 after the cuts 6 and 7 have been produced, can be easily removed in a further method step.
  • the carrier substrate wafer 1 subdivided into individual carrier substrates 100 is connected to an extensible support 11 (see FIG. ID).
  • the stretchable pad 11 is a film comprising or consisting of polyethylene or composed of another suitable material.
  • a stretched mesh is used as the stretchable backing 11.
  • connection between the extensible pad 11 and the carrier substrate wafer 1 is performed so mechanically stable that it remains at least so far during the subsequent stretching of the pad that the semiconductor body 10 remain connected to the stretchable pad 11.
  • the connection of the carrier substrates 100 with the stretchable pad 11 dissolves so at least not completely, if the latter is stretched.
  • an adhesive or varnish layer is disposed between the semiconductor bodies 10 and the stretchable pad 11 which provides adhesion therebetween.
  • the carrier substrate wafer 1 is preferably applied to the stretchable underlay 11 already after being subdivided into carrier substrates 100 and before the cuts 6 are carried out by the semiconductor layer sequence 2. It is also conceivable that this takes place only after the formation of the cuts 6 through the semiconductor layer sequence 2.
  • the semiconductor bodies 10 are pulled apart so far apart (compare FIG. IE) that adjacent semiconductor bodies 10 no longer overlap and can therefore be removed individually from the extensible support 11.
  • the stretchable pad 11 is bonded to the front side 201 of the semiconductor layer sequence 2 and subsequently the cuts 7 are made through the carrier substrate wafer 1 before the stretchable pad 11 is then pulled apart.
  • the terminal regions 120 of the carrier substrates 100 which are no longer connected to the semiconductor layer stack 200 of the semiconductor body 10, are exposed. These terminal areas 120 overlap before being pulled apart the semiconductor body 10 with semiconductor layer stacks 200, which belong to adjacent semiconductor bodies 10.
  • Semiconductor layer stack 200 forms an overhang with respect to the associated carrier substrate 100 and, together with this and the expandable support 11, defines a cavity 12.
  • the semiconductor bodies 10 are removed from the stretchable pad 11 in a simple manner and in any order for further method steps. However, they can also remain on the extensible support for further process steps, such as coating with a material containing phosphor and / or diffuser particles.
  • FIGS. 2A and 2B show the semiconductor bodies 10 arranged on the extensible support 11 before or after the separation and pulling apart of the extensible support 11 in plan view.
  • FIG. 2B clearly shows how a first region 110 of each carrier substrate 100 belonging to a semiconductor body 10 overlaps with the associated semiconductor layer stack 200, while a connection region 120 of the carrier substrate 100 comes to lie next to the associated semiconductor layer stack 200.
  • a first subregion 210 of each semiconductor layer stack 200 protrudes in a first offset direction 22 and in a second offset direction 23 beyond the associated carrier substrate 100 addition.
  • a second subregion 220 of the semiconductor layer stack 200 overlaps with the first region 110 of the carrier substrate 100.
  • a first electrically insulating layer 13a is applied to at least part of the connection region 120 of the carrier substrate 100 of the semiconductor body 10, which also extends over a side surface 221 of the semiconductor layer stack 200 as a second electrically insulating layer 13b (compare FIG FIG. IF).
  • the first and second electrically insulating layers 13a, 13b are made of silicon dioxide.
  • a contact layer 14 which consists for example of indium tin oxide (ITO), is applied to the front side 201 of the semiconductor layer stack 2OO, which extends on the electrically insulating layer 13b and 13a at least to a part of the connection region 120 of the carrier substrate 100 ( compare Figure IF).
  • the first and second passivation layers 13 a, 13 b prevent a short circuit of the semiconductor layer stack 200 by the contact layer 14.
  • the semiconductor body can thus advantageously be installed in conventional component packages by means of conventional die-bonding methods.
  • an electrical current can be impressed into the semiconductor body 10.
  • a connection wire 17 can be attached to the first electrical connection layer 15, via which the semiconductor body operating current can be supplied (see Figure IG).
  • the cavity 12 under the overhang 210 may, for example, be at least partially filled with a filling compound 18 such as an epoxy resin or BCB.
  • a filling compound 18 such as an epoxy resin or BCB.
  • this space 12 is practically completely filled with filling compound 18 so that its underside facing away from the semiconductor layer stack 200 together with the rear side 101 of the carrier substrate 100 or together with the second electrical connection layer 16 arranged thereon forms a positioning surface of the semiconductor body 10.
  • the stability of the semiconductor body 10 can be increased.
  • a carrier substrate wafer 1 and a semiconductor layer sequence 2, which generates electromagnetic radiation during operation and which comprises a growth substrate wafer 3 onto which the remaining layers of the semiconductor layer sequence 2, are analogously to the exemplary embodiment according to FIGS epitaxially grown.
  • a structured connection layer 5 is applied to the carrier substrate wafer 1.
  • a solder such as Au, AuSn, -Pd, In, PdIn or Pt is applied as a structured compound layer 5.
  • the connecting layer 5 can be applied to the rear side 302 of the composite of growth substrate 3 opposite the front side 201, the remaining layers of the semiconductor layer sequence 2 and optionally. be applied to further layers.
  • connection layer 5 which is subsequently structured, for example by means of an etching process.
  • the rear side 302 and the carrier substrate wafer 1 are subsequently brought together and heated so that the solder melts and the solder layer produces a structured, mechanically stable connection between the carrier substrate wafer 1 and the semiconductor layer sequence 2.
  • an adhesive for example an epoxy resin
  • heating of the bonding layer 5 can optionally be omitted or replaced or supplemented by another process step, for example for hardening.
  • sections 6 are performed by the semiconductor layer sequence 2 and sections 7 by the carrier substrate wafer 1. These cuts 6, 7 subdivide the semiconductor layer sequence 2 into individual semiconductor layer stacks 200 and the carrier substrate wafer 1 into individual carrier substrates 100 (compare FIG. 3B ' ).
  • the structured connection layer 5 is designed such that each semiconductor layer stack 200 is connected to exactly one carrier substrate 100, so that individual semiconductor bodies 10 are formed. After the subdivision into individual carrier substrates 100, the carrier substrate wafer 1 is arranged on a stretchable base 11, preferably before the subdivision of the semiconductor layer sequence by the cuts 6. This and the further method steps are analogous to the exemplary embodiment according to FIGS.
  • the second electrical contact surface 16 is not arranged on the rear side 212 of a first region 210 of the semiconductor layer stack 200, as in the embodiment shown in FIGS. Instead, between the growth substrate 3 and the carrier substrate 100, an electrically conductive layer 19 is arranged, which covers a part of the connection region 120 of the carrier substrate 100, which is free of the semiconductor layer stack 200. On this conductive layer 19, a second electrical connection layer 16 is applied.
  • the contact layer 14 is formed according to the first-described embodiment according to FIGS. IF and IG.
  • the contact layer 14 is applied directly to the connection region 120 of the carrier substrate 100, without a first between them
  • Passivation layer 13a is located. On a side surface 221 of the semiconductor layer stack 200, a second passivation layer 13 b is arranged in order to avoid an electrical short circuit of the semiconductor layer stack through the contact layer 14.
  • the first and second electrical connection layers 15, 16 do not need to be arranged on different sides of the semiconductor layer stack 200, as shown in FIGS. 4A and 4B.
  • An arrangement according to the semiconductor body according to FIG. 5, in which both electrical connection layers 15, 16 are adjacent to one another next to the same side surface 221 of the semiconductor layer stack 200, is particularly expedient and advantageous if the semiconductor layer stack 200 is over the edge on the side opposite the side surface 221 of the carrier substrate 100 projects and has an overhang 210 with respect to the adjacent end face of the carrier substrate.
  • the second electrical connection layer 16 can be applied directly to the carrier substrate 100; otherwise, a conductive layer 19 similar to the embodiment shown in FIG. 4A may be provided, which is disposed between the semiconductor layer stack 200 and the carrier substrate 100 and pulled onto the connection region 120 of the carrier substrate 100 so that the second electrical connection layer 16 can be placed thereon , If the carrier substrate 100 is electrically conductive or should the contact layer 14 also be applied to the conductive layer 19, analogously to the exemplary embodiment of FIG. IF, it must be between the contact layer 14 and the conductive layer 19 or the conductive carrier substrate
  • FIGS. 6A to 6E show various examples of the arrangement of the semiconductor layer stack 200 on the carrier substrate 100.
  • the semiconductor layer stack 200 and the carrier substrate 100 have a plan view of the front side 201 of FIG. 6A.
  • Semiconductor layer stack 200 has a rectangular shape with side lengths Ii and I 2 or I 3 and I 4 .
  • the short sides 211 and 221 of the semiconductor layer stack 200 are parallel to the short sides 111, 121 of the carrier substrate 100, that is arranged offset.
  • the two adjacent long sides of semiconductor layer stack 200 and carrier substrate 100 each lie in a common plane.
  • the semiconductor layer stack 200 consequently projects beyond a side 111 of the carrier substrate 100 on a short side of the semiconductor body 10 (in the offset direction 22).
  • the side surface 211 of the first portion 210 of the semiconductor layer stack 200 which projects beyond the carrier substrate 100, thereby has from the adjacent side surface 111 of the first region 110 of the carrier substrate 100, which is covered by the semiconductor layer stack 200, a distance d, which is greater than 50 microns in the present case.
  • the side surface 121 of the connection region 120 of the carrier substrate 100 has a distance a from the adjacent side surface 221 of the semiconductor layer stack 200 which in the present case assumes the same value as the abovementioned distance d.
  • the side surfaces of the semiconductor layer stack 200 and the carrier substrate 100 which are parallel to the plane defined by the offset direction 22 and the growth direction 21, ie, the sides having the lengths I 1 and I 3 , are not offset from each other.
  • one section 6 is not offset from one another by the semiconductor layer sequence 2 and a section 7 passes through the carrier substrate wafer 7, which run parallel to this plane, and form a common section through the semiconductor body 10. This completely cuts through the semiconductor body 10 along the growth direction 21.
  • the semiconductor layer stack 200 does not protrude beyond a lateral surface of the carrier substrate 100 in a first offset direction 22. Rather, the semiconductor layer stack is shifted diagonally relative to the carrier substrate 100.
  • the distance d between each side face 211 of the first subregion 210 of the semiconductor layer stack 200 is from the respectively adjacent one Side surface 111 of the first portion 110 of the support substrate 100 of the same size.
  • the distance d along the first offset direction 22 may be larger or smaller than the distance along the second offset direction 23. There is then no exact diagonal offset.
  • the distance a of a side surface 121 of the connection region 120 of the carrier substrate 100 from the respectively adjacent side surface 221 of the second subregion 220 of the semiconductor layer stack 200 corresponds to the above-mentioned distance d.
  • the semiconductor layer stack 200 and the carrier substrate 100 need not have the same dimensions along the main extension directions of the carrier substrate.
  • the exemplary embodiment of FIG. 6C shows an example of a semiconductor layer stack 200, which has a smaller length I 1 than the associated carrier substrate 100, which has a length I 3 > Ii.
  • the semiconductor layer stack 200 has a width I 2 which is greater than the width I 4 of the associated carrier substrate 100.
  • the semiconductor layer stack 200 is arranged so that the centers of the semiconductor layer stack 200 and the carrier substrate 100, in plan view of the
  • Semiconductor layer stack 200 seen, are stacked.
  • the connection region 120 of the carrier substrate 100 projects longitudinally beyond the semiconductor layer stack 200.
  • the electrical connection layers 15 and 16 can then be arranged as shown in FIGS. 4A and 4B, respectively.
  • the first portion 210 of the semiconductor layer stack 200 protrudes beyond the carrier substrate and represents an overhang 210.
  • one or two side surfaces of the semiconductor layer stack 200 and the carrier substrate 100 may be arranged flush with each other.
  • the semiconductor layer sequence 200 viewed in plan view of the semiconductor layer stack 200, has a circular cross section. It is arranged on a square carrier substrate 100 and offset along an edge of this carrier substrate 100 such that it has a first subregion 210 whose side surface 211 has a maximum distance d from the adjacent side surface 111 of the carrier substrate 100.
  • a semiconductor body With such a semiconductor body, improved light extraction can be achieved.
  • parts of the semiconductor layer sequence 2 remain as a waste between the semiconductor layer stacks 200, which are expediently removed.
  • the side surfaces of the carrier substrate 100 in the case of the semiconductor body according to the exemplary embodiment of FIG. 6E have, for example, recesses 12 on two opposite sides 111. These recesses 12 extend over the entire thickness of the carrier substrate 100 and have, for example, a width which corresponds to approximately half the side length. In the region of these recesses 12, a first subregion 210 of the semiconductor layer stack projects beyond the adjacent edge of the carrier substrate and in each case represents an overhang 210, which is predetermined by the shape of the recesses 12 and has a depth d.
  • the recesses 12 have a rectangular Cross-section. But they can also be formed with a semicircular, triangular or Trapezmaschinem cross-section.
  • the remaining side surfaces of the carrier substrate have, with respect to the semiconductor layer stack 200, protrusions 120 which preferably have the same dimensions as the recesses 12. If the protrusions 120 and the recesses 12 have the same dimensions, the cuts 6, 7 can be produced in the production of a plurality of such semiconductor bodies 10 be guided so that the projections 120 of a semiconductor body 10 in the recesses 12 of adjacent semiconductor body 10 are located. Adjacent carrier substrates 100 then engage in one another similar to puzzle pieces, and between adjacent semiconductor layer stacks 200 there advantageously does not arise a waste of the semiconductor layer sequence.
  • the projections 120 each have a depth a and represent the connection region 120 of the carrier substrate 100, which is free of the semiconductor layer stack 200 and can be arranged on the electrical electrical contact surfaces 15, 16.
  • the arrangement can take place, for example, as shown in FIGS. 4A and 4B.
  • the semiconductor body 10 In the case of the semiconductor body 10 according to the exemplary embodiment of FIG. 6E, there is no edge of the carrier substrate 100, beyond which the semiconductor layer stack 200 protrudes at all points.
  • the semiconductor body 10 therefore advantageously has a high stability. Nevertheless, a plurality of such semiconductor bodies 10 can be produced according to one of the methods according to the invention without parts of the semiconductor layer sequence 2 or of the carrier substrate wafer 1 remaining unused and having to be removed between the semiconductor bodies 10.

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Abstract

L'invention concerne un corps semi-conducteur émetteur de rayonnement avec un substrat de support et son procédé de fabrication. Ce procédé permet de fabriquer un composé structuré d'une suite de couches semi-conductrices (2) avec une plaquette de substrat de support (1). La suite de couches semi-conductrices est fractionnée en une pluralité d'empilements de couches semi-conductrices (200) au moyen d'entailles (6) à travers la suite de couches semi-conductrices et la plaquette de substrat de support (1) est fractionnée en une pluralité de substrats de support (100) avec des entailles (7) à travers la plaquette de substrat de support (1). Le composé structuré est ainsi réalisé de telle sorte qu'au moins un empilement de couches semi-conductrices (200) est relié précisément à un substrat de support (100) correspondant. En outre, au moins une entaille (7) à travers la plaquette de substrat de support n'est prolongée par aucune entaille (6) à travers la suite de couches semi-conductrices, afin d'obtenir une entaille rectiligne à travers la plaquette de substrat de support et la suite de couches semi-conductrices.
EP07722350A 2006-05-03 2007-05-03 Corps semi-conducteur émetteur de rayonnement avec un substrat de support et son procédé de fabrication Withdrawn EP2013917A1 (fr)

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DE102006020537 2006-05-03
DE102006033502A DE102006033502A1 (de) 2006-05-03 2006-07-19 Strahlungsemittierender Halbleiterkörper mit Trägersubstrat und Verfahren zur Herstellung eines solchen
PCT/DE2007/000793 WO2007124737A1 (fr) 2006-05-03 2007-05-03 Corps semi-conducteur émetteur de rayonnement avec un substrat de support et son procédé de fabrication

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Families Citing this family (15)

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Publication number Priority date Publication date Assignee Title
DE102008009108A1 (de) 2008-02-14 2009-08-20 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Halbleiterlasers sowie Halbleiterlaser
JP2009212179A (ja) * 2008-03-03 2009-09-17 Sanyo Electric Co Ltd 半導体レーザ素子および半導体レーザ素子の製造方法
KR100999779B1 (ko) * 2010-02-01 2010-12-08 엘지이노텍 주식회사 발광소자, 발광소자의 제조방법 및 발광소자 패키지
KR101159782B1 (ko) 2010-02-05 2012-06-26 신왕균 투명 엘이디 웨이퍼 모듈 및 그 제조방법
WO2011111937A2 (fr) * 2010-03-09 2011-09-15 신왕균 Module tranche led transparent et procédé de fabrication associé
GB2480873B (en) * 2010-06-04 2014-06-11 Plastic Logic Ltd Reducing defects in electronic apparatus
DE102010032813A1 (de) * 2010-07-30 2012-02-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils und optoelektronisches Halbleiterbauteil
TWI463620B (zh) 2012-08-22 2014-12-01 矽品精密工業股份有限公司 封裝基板之製法
DE102013111120A1 (de) * 2013-10-08 2015-04-09 Osram Opto Semiconductors Gmbh Halbleiterchip und Verfahren zum Vereinzeln eines Verbundes in Halbleiterchips
US10950747B2 (en) * 2015-07-01 2021-03-16 Sensor Electronic Technology, Inc. Heterostructure for an optoelectronic device
WO2017004497A1 (fr) 2015-07-01 2017-01-05 Sensor Electronic Technology, Inc. Élimination de structure de substrat
US10363629B2 (en) * 2017-06-01 2019-07-30 Applied Materials, Inc. Mitigation of particle contamination for wafer dicing processes
DE102017130131B4 (de) * 2017-12-15 2021-08-19 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen und optoelektronisches Halbleiterbauteil
DE102019108701A1 (de) * 2019-04-03 2020-10-08 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung einer Mehrzahl von Bauteilen, Bauteil und Bauteilverbund aus Bauteilen
CN112993755B (zh) * 2019-11-29 2022-02-18 山东华光光电子股份有限公司 一种半导体激光器芯片及其应用方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910003735B1 (ko) * 1988-12-17 1991-06-10 삼성전자 주식회사 발광장치
US5329529A (en) 1993-04-02 1994-07-12 Thomson Consumer Electronics, Inc. Digital data arbitration apparatus
US5486826A (en) 1994-05-19 1996-01-23 Ps Venture 1 Llc Method and apparatus for iterative compression of digital data
JPH09277595A (ja) 1996-02-13 1997-10-28 Oki Data:Kk 光プリントヘッド
US5684309A (en) * 1996-07-11 1997-11-04 North Carolina State University Stacked quantum well aluminum indium gallium nitride light emitting diodes
DE19640594B4 (de) * 1996-10-01 2016-08-04 Osram Gmbh Bauelement
EP1017113B1 (fr) * 1997-01-09 2012-08-22 Nichia Corporation Dispositif a semi-conducteur au nitrure
US5831277A (en) * 1997-03-19 1998-11-03 Northwestern University III-nitride superlattice structures
JP3395620B2 (ja) * 1997-12-16 2003-04-14 日亜化学工業株式会社 半導体発光素子及びその製造方法
JP2000012959A (ja) * 1998-06-22 2000-01-14 Mitsubishi Electric Corp 半導体発光装置
DE19955747A1 (de) 1999-11-19 2001-05-23 Osram Opto Semiconductors Gmbh Optische Halbleitervorrichtung mit Mehrfach-Quantentopf-Struktur
DE10017337C2 (de) * 2000-04-07 2002-04-04 Vishay Semiconductor Gmbh Verfahren zum Herstellen lichtaussendender Halbleiterbauelemente
JP2003092450A (ja) * 2001-09-19 2003-03-28 Sharp Corp 半導体発光装置
JP2003124151A (ja) * 2001-10-17 2003-04-25 Disco Abrasive Syst Ltd サファイア基板のダイシング方法
US6955976B2 (en) * 2002-02-01 2005-10-18 Hewlett-Packard Development Company, L.P. Method for dicing wafer stacks to provide access to interior structures
US20030189215A1 (en) 2002-04-09 2003-10-09 Jong-Lam Lee Method of fabricating vertical structure leds
JP2004037485A (ja) 2002-06-28 2004-02-05 Mitsubishi Electric Corp 半導体光変調器と半導体光装置
CN100530705C (zh) * 2003-01-31 2009-08-19 奥斯兰姆奥普托半导体有限责任公司 用于制造一个半导体元器件的方法
DE10339985B4 (de) 2003-08-29 2008-12-04 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement mit einer transparenten Kontaktschicht und Verfahren zu dessen Herstellung
JP4195352B2 (ja) * 2003-09-10 2008-12-10 三星エスディアイ株式会社 発光素子基板およびそれを用いた発光素子
JP3801160B2 (ja) * 2003-09-11 2006-07-26 セイコーエプソン株式会社 半導体素子、半導体装置、半導体素子の製造方法、半導体装置の製造方法及び電子機器
US20050205883A1 (en) * 2004-03-19 2005-09-22 Wierer Jonathan J Jr Photonic crystal light emitting device
TWI232604B (en) 2004-07-23 2005-05-11 Supernova Optoelectronics Corp Manufacturing method of metal reflection layer for gallium nitride based light-emitting diode
JP2006054246A (ja) * 2004-08-10 2006-02-23 Disco Abrasive Syst Ltd ウエーハの分離方法
TWI235511B (en) 2004-11-03 2005-07-01 Chipmos Technologies Inc Method of manufacturing light emitting diode package and structure of the same
TWI251355B (en) 2004-12-22 2006-03-11 Opto Tech Corp A LED array package structure and method thereof
TWI251357B (en) 2005-06-21 2006-03-11 Epitech Technology Corp Light-emitting diode and method for manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007124737A1 *

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CN101432900B (zh) 2012-05-02
DE102006033502A1 (de) 2007-11-15
US20090218587A1 (en) 2009-09-03
KR20090013218A (ko) 2009-02-04
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US20110186904A1 (en) 2011-08-04
WO2007124737A1 (fr) 2007-11-08
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