EP1975941B1 - Halbleiterspeicher, System und Betriebsverfahren für den Halbleiterspeicher - Google Patents
Halbleiterspeicher, System und Betriebsverfahren für den Halbleiterspeicher Download PDFInfo
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- EP1975941B1 EP1975941B1 EP08101064A EP08101064A EP1975941B1 EP 1975941 B1 EP1975941 B1 EP 1975941B1 EP 08101064 A EP08101064 A EP 08101064A EP 08101064 A EP08101064 A EP 08101064A EP 1975941 B1 EP1975941 B1 EP 1975941B1
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- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
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Definitions
- the present invention relates to a semiconductor memory having dynamic memory cells and to a system and operating method thereof.
- DRAMs having a partial self-refresh mode have been developed (for example, see Japanese Unexamined Patent Application Publication No. 2003-68075 ).
- a DRAM of this type has a function to change the size of a partial refresh area for which a refresh operation is executed during the self refresh mode. Further, in portable equipment having various functions, the volume of retained data is different for each operating function.
- the DRAMs having a self refresh mode and pseudo SRAMs which internally execute a refresh operation automatically have an oscillator which generates a refresh request periodically.
- the partial refresh area is set by rewriting bit values in a mode register by a setting command.
- the refresh request occurs asynchronously with supply timing of the setting command. Accordingly, when timing of changing the partial refresh area by the setting command the timing of occurrence of the refresh request overlap, there is a risk that the refresh operation is not executed in the area where the refresh operation should be operated. Thus, data retained in the memory cells disappear. In other words, the semiconductor memory malfunctions.
- a semiconductor memory comprising: a plurality of memory blocks each having dynamic memory cells; a refresh set circuit which sets partial refresh information indicating enabling/disabling of a refresh operation for each of the memory blocks according to an external input, and outputs the set partial refresh information as a partial set signal; a refresh request generation circuit which outputs periodically a refresh request signal corresponding to the memory block for which enabling is indicated by the partial set signal; a refresh address counter which generates in response to the refresh request signal a refresh address signal indicating the memory cell for which the refresh operation is executed; and an operation control circuit which executes the refresh operation for one of the memory blocks in response to the refresh request signal; characterized by a filter circuit which masks the partial set signal from the refresh set circuit and outputs the partial set signal indicating enabling of the refresh operation for all of the memory blocks to the refresh request generation circuit during a period in which the partial refresh information is changed by the external input.
- a system comprising the above semiconductor memory and a controller.
- an operating method of a semiconductor memory including a plurality of memory blocks each having dynamic memory cells and operating in response to an access request signal from an outside and a refresh request signal generated inside, the method comprising: setting partial refresh information indicating enabling/disabling of a refresh operation for each of the memory blocks according to an external input, and outputting the set partial refresh information as a partial set signal; outputting periodically a refresh request signal corresponding to the memory block for which enabling is indicated by the partial set signal; generating in response to the refresh request signal a refresh address signal indicating the memory cell for which the refresh operation is executed; and executing the refresh operation for one of the memory blocks in response to the refresh request signal; characterised by masking the partial set signal so as to enable the refresh operation for all the memory blocks during a period in which the partial refresh information is changed by the external input.
- a refresh set circuit sets partial refresh information indicating enabling/disabling a refresh operation for each of the memory blocks according to an external input, and outputs the set partial refresh information as a partial set signal.
- a refresh request generation circuit outputs periodically a refresh request signal corresponding to a memory block for which enabling is indicated by the partial set signal.
- a refresh address counter generates in response to the refresh request signal a refresh address signal indicating a memory cell for which a refresh operation is executed.
- An operation control circuit executes a refresh operation for one of the memory blocks in response to the refresh request signal.
- a filter circuit masks the partial set signal from the refresh set circuit and outputs a partial set signal indicating enabling of a refresh operation for all of the memory blocks to the refresh request generation circuit during a period in which the partial refresh information is changed by the external input.
- each signal line shown by a heavy line is constituted of a plurality of lines. Part of blocks to which the heavy lines are connected is constituted of a plurality of circuits. Each signal line through which the signal is transmitted is denoted by the same reference symbol as the signal name. Each signal starting with "/" represents negative logic. Each signal ending with “Z” represents positive logic. Each double circle in the drawings represents an external terminal.
- Fig. 1 illustrates a semiconductor memory MEM of a first embodiment.
- the semiconductor memory MEM is, for example, an FCRAM (Fast Cycle RAM) of pseudo SRAM type.
- the pseudo SRAM has memory cells of DRAM and an interface of SRAM, and executes a refresh operation automatically inside the chip.
- the semiconductor memory MEM operates in synchronization with, for example, a clock signal CLK. Note that the present invention is applicable to either of a semiconductor memory of clock asynchronous type and a semiconductor memory of clock synchronous type.
- the memory MEM has a command decoder 10, a mode register 12, a filter circuit FLT, an oscillator 14, frequency dividers 16, 18, a fuse circuit 20, a test circuit 22, a selector 24, an operation control circuit 26 having an arbiter ARB, a refresh address counter 28, an address buffer/latch 30, an address selector 32, a data input/output buffer 34, a data control circuit 36 and a memory core 38 including memory blocks BLK (BLKO-3).
- the memory MEM forms a memory system SYS together with a CPU as shown in Fig. 2 .
- the command decoder 10 receives a command signal CMD for executing an access operation of the memory core 38, and outputs a command recognized according to the logic level of the command signal CMD as a read command signal RD, a write command signal WR or a mode register set signal MRS.
- the read command signal RD and the write command signal WR are an external access request AREQZ for executing an access operation to the memory core 38.
- the command signal CMD is formed by a chip enable signal /CE, an output enable signal /OE, and a write enable signal /WE.
- the mode register 12 is set according to the bit value of an address signal CAD (external input signal) supplied together with the mode register set signal MRS (mode register set command).
- a partial refresh area PREFA is set by the mode register 12. Further, the mode register 12 may set an operating specification of the memory MEM such as burst length BL and data latency CL.
- the partial refresh area PREFA is a memory block BLK for which a refresh operation is executed, and is indicated by partial set signals PSET00, PSET01.
- the partial refresh area PREFA is explained with Fig. 4 .
- the burst length BL is the number of data inputs received by a data terminal DQ in response to one write command WR, and is the number of data outputs output from the data terminal DQ in response to one read command RD.
- the data latency CL is the number of cycles from reception of the read command RD to output of first read data DQ.
- the filter circuit FLT outputs the partial set signals PSET00,01 set in the mode register 12 as the partial set signals PSET0-1. However, while partial refresh information in the latches LT is changed by the mode register set command MRS (external input), the filter circuit FLT masks the partial set signals PSET00,01 from the mode register 12 (latches LT shown in Fig. 3 ), and sets the values of the partial set signals PSETO-1 to values indicating enabling of a refresh operation for all the memory blocks BLKO-3.
- the oscillator 14 outputs an oscillating signal OSC at a predetermined cycle (1 ⁇ s for example).
- the frequency divider 16 (refresh generation circuit) divides the frequency of the oscillating signal OSC and generates a reference refresh request signal RREQ0Z (10 ⁇ s for example) periodically.
- the frequency of the reference refresh request signal RREQ0Z can be changed according to an adjustment signal from the selector 24.
- the frequency divider 18 divides the frequency of the refresh request signal RREQ0Z according to the partial set signals PSET0-1 and generates a refresh request signal RREQZ periodically.
- the oscillator 14 and the frequency dividers 16, 18 operate as a refresh request generation circuit which periodically outputs the refresh request signal RREQZ corresponding to the memory block BLK for which enabling is indicated by the partial set signals PSET0-1.
- the fuse circuit 20 has a fuse programmed for trimming the frequency of the refresh request signal RREQ0Z.
- the trimming is implemented in a test process after electric characteristics of the memory MEM are evaluated by an LSI tester or the like, so as to set the frequency of the refresh request signal RREQ0Z to the optimum.
- the test circuit 22 outputs a test signal for temporarily changing the dividing ratio of the frequency divider 16 regardless of the program state of the fuse circuit 20.
- the test circuit 22 operates while the memory MEM is set to the test mode by the mode register 12 or the like, and retains the value of the address signal CAD supplied together with a test mode command.
- the selector 24 selects the set value of the fuse circuit 20 when the test circuit 22 is not in use, and outputs it as an adjustment signal to the frequency divider 16. Further, the selector 24 masks the set value of the fuse circuit 20 when the test circuit 22 is in use, selects the set value set to the test circuit 22, and outputs the selected value as an adjustment signal to the frequency divider 16. For example, in the test process of the memory MEM, the value of the adjustment signal for setting the frequency of the refresh request signal RREQ0Z to the optimum is obtained using the test circuit 22, and the fuse circuit 20 is programmed according to the obtained value.
- the operation control circuit 26 outputs an operation control signal (word line activation signal WLZ, sense amplifier activation signal LEZ, a column selection signal CLZ and a precharge control signal BRS) so as to cause the memory core 38 to execute a read operation or a write operation in response to the read command signal RD or the write command signal WR, or cause the memory core 38 to execute a refresh operation in response to the refresh request signal RREQZ.
- the read operation, the write operation and the refresh operation are executed in one of the memory blocks BLK0-3.
- the word line activation signal WLZ controls activation timing of a word line WL
- the sense amplifier activation signal LEZ controls activation timing of a sense amplifier SA.
- the column selection signal CLZ controls on/off timing of a column switch CSW
- the precharge control signal BRS controls on/off timing of the precharge circuit PRE.
- the arbiter ARB of the operation control circuit 26 decides which one of them should be given priority. For example, the arbiter ARB gives priority to the refresh request RREQZ when the external access request AREQZ (read command RD or write command WR) and the refresh request RREQZ are received simultaneously, and activates a refresh signal REFZ for a predetermined period. The read operation in response to the read command RD is suspended until the refresh operation in response to the refresh request RREQZ is completed and the refresh signal REFZ is inactivated.
- the refresh operation in response to the refresh request RREQZ is suspended until the read operation is completed.
- the refresh signal REFZ is activated for a predetermined period in response to the completion of the read operation. The same applies to the write command WR.
- the refresh address counter 28 sequentially updates refresh address signals RRAD (RRAD0-5) indicating a memory cell MC for which a refresh operation is executed in response to the refresh request signal RREQZ.
- the refresh address signals RRAD are updated after an internal row address signal IRAD (refresh address) corresponding to the refresh request signal RREQZ is supplied to the memory core 38. Accordingly, it is possible to prevent change of the refresh address signals RRAD when executing a refresh operation, and malfunctioning of the memory core 38 can be prevented.
- the range of the refresh address signals RRAD to be updated changes according to the partial set signals PSET0-1.
- the address buffer/latch 30 receives an address signal AD via an external terminal and outputs the received address as the row address signal RAD and the column address signal CAD.
- the row address signal RAD is supplied for selecting a word line.
- the column address signal CAD is supplied for selecting a plurality of sets of bit lines BL, /BL corresponding to the data terminal DQ formed by a plurality of bits.
- the address selector 32 selects the refresh address signals RRAD for executing a refresh operation while the refresh signal REFZ is activated, selects the row address signal RAD for executing a read operation or write operation while the refresh signal REFZ is inactivated, and outputs the selected signal as the internal row address signal IRAD to the memory core 38.
- the data input/output buffer 34 receives a write data signal via the data terminal DQ, and outputs the received data signal as an internal data signal IDQ. Further, the data input/output buffer 34 receives a read data signal from the memory cells MC, and outputs the received data signal to the data terminal DQ.
- the data control circuit 36 converts the internal data signal IDQ (write data) from serial to parallel, and outputs the converted signal to a data bus DB.
- the data control circuit 36 converts read data on the data bus DB from parallel to serial and outputs the converted data as the internal data signal IDQ to the data bus DB.
- the bit width of the data bus DB is twice the bit width of the data terminal DQ (16 data terminals DQ and a 32-bit data bus).
- the memory core 38 has four memory blocks BLK0-3, a row decoder RDEC, a precharge circuit PRE, a sense amplifier SA, a column switch CSW, a column decoder CDEC, a read amplifier RA and a write amplifier WA.
- Each of the memory blocks BLK0-3 has a plurality of dynamic memory cells MC, a plurality of word lines WL coupled to the memory cells MC arranged in one direction, and a plurality of bit line pairs BL, /BL coupled to the memory cells MC arranged in a direction orthogonal to the one direction.
- the memory cells MC each have a capacitor for retaining data as electric charge and a transfer transistor for coupling one end of the capacitor to one of the bit lines BL (or /BL). The other end of the capacitor is coupled to a precharge voltage line.
- the gate of the transfer transistor is coupled to one of the word lines WL.
- the common bit line pairs BL, /BL are wired through the memory blocks BLK0-3, and the precharge circuit PRE, the sense amplifier SA, and so on are shared by the memory blocks BLK0-3.
- the precharge circuit PRE and the sense amplifier SA may be arranged for each of the memory blocks BLK0-3.
- a part of the column decoder CDEC as well as the read amplifier RA and the write amplifier WA may be arranged commonly for the memory blocks BLK0-3.
- the row address decoder RDEC decodes the internal row address signal IRAD for selecting one of the word lines WL.
- the precharge circuit PRE couples the bit line pairs BL, /BL to the precharge voltage line in synchronization with the precharge control signal BRS while the memory cells MC are not accessed.
- the sense amplifier SA amplifies a difference in signal amounts of data signals read to the bit line pairs BL, /BL.
- the column address decoder CDEC decodes the column address signal CAD for selecting the bit line pair BL, /BL to/from which a data signal is input/output.
- the column switch CSW couples the bit lines BL, /BL corresponding to the column address signal CAD to the read amplifier RA and the write amplifier WA.
- the read amplifier RA amplifies complementary read data output via the column switch CSW during a read access operation.
- the write amplifier WA amplifies complementary write data supplied via the data bus DB and supplies the amplified data to the bit line pairs BL, /BL during a write access operation.
- Fig. 2 illustrates a system SYS of the first embodiment.
- the system SYS is, for example, portable equipment such as a mobile phone, and has a system board SBRD in which a system in package SiP (System in Package) for controlling the operation of the portable equipment is mounted.
- the SiP has the memory MEM shown in Fig. 1 , a memory controller MCNT which accesses the memory MEM, a flash memory FLASH, a flash controller FCNT which accesses the flash memory FLASH, a CPU (system controller) controlling the entire system, and so on.
- the CPU, the memory controller MCNT and the flash controller FCNT are coupled to each other by a system bus SBUS, and operate in synchronization with a system clock signal SCLK.
- the system clock signal SCLK is supplied as the clock signal CLK to the memory MEM or the flash memory FLASH.
- the SiP may be coupled to a higher system via an external bus.
- a program and data stored in the flash memory FLASH are transferred to the memory MEM when powered on. Thereafter, the CPU executes the program transferred to the memory MEM for realizing the function of the system SYS, and reads/writes data retained in the memory MEM.
- the CPU outputs an access request for accessing the memory MEM and a write data signal WDT, and receives a read data signal RDT from the memory MEM. Further, the CPU outputs an access request for accessing the flash memory FLASH.
- the CPU does not output a refresh request, and hence is not able to recognize the timing that the memory MEM executes a refresh operation. In other words, the memory MEM executes the refresh operation automatically without being recognized by the CPU.
- Fig. 3 illustrates details of the mode register 12 and the filter circuit FLT shown in Fig. 1 .
- the mode register 12 in the diagram only illustrates a circuit for setting the partial refresh area PREFA.
- a circuit for setting the burst length BL and the data latency CL is omitted from the diagram.
- the mode register 12 has a delay circuit DLY1 and two latches LT (refresh set circuit) which receives the column address signal CAD (CAD0-1).
- the delay circuit DLY1 delays the mode register set signal MRS and outputs a delay set signal DMRS.
- the two latch circuits LT latch partial refresh information indicated by column address signals CAD0-1 (external input) in synchronization with the delay set signal DMRS, and retains the latched values as values setting the partial refresh area PREFA shown in Fig. 4 .
- the latch circuits LT output the retained values as partial set signals PSET00, PSET10.
- the filter circuit FLT has a pulse width extension circuit PLSE and two AND circuits corresponding to the latches LT respectively.
- the pulse width extension circuit PLSE has a delay circuit DLY2 and a NOR gate.
- the pulse width extension circuit PLSE extends a falling edge of the mode register set signal MRS in pulse form and outputs a signal with inverted logic as an all refresh signal AREFX.
- the all refresh signal AREFX is activated to a low logic level during a period in which the mode register set signal MRS is activated to a high logic level.
- the two AND circuits output the partial set signals PSET00-10 as the partial set signals PSET0-1 while the all refresh signal AREFX is inactivated (high logic level). Further, the AND circuits fix the partial set signals PSET0-1 to low logic levels while the all refresh signal AREFX is activated (low logic level). Thus, the partial set signals PSET0-1 are fixed to low logic levels regardless of the values retained in the latches LT during a predetermined period in which the mode register set command MRS is supplied. Accordingly, during a set period of the latches LT of the mode register 12, all the memory blocks BLKO-3 are set to the partial refresh area PREFA.
- Fig. 4 illustrates the partial refresh area PREFA of the first embodiment.
- the memory blocks BLK indicated by hatching are the partial refresh area PREFA for which execution of the refresh operation is enabled. For the memory blocks BLK indicated by blank spaces, the refresh operation is disabled.
- the memory blocks BLK0-3 are selected by two bits, IRAD4-5, of the row address signal IRAD.
- the memory block BLK0 is selected.
- the memory blocks BLK1 /BLK2/BLK3 are selected respectively.
- Fig. 5 illustrates operations of the mode register 12 and the filter circuit FLT shown in Fig. 3 .
- the partial refresh area PREFA is set to 1/2 in advance. Specifically, the refresh operation is executed to retain the data in the memory blocks BLK0-1.
- the mode register set command MRS By the mode register set command MRS, the partial refresh area PREFA is changed from 1/2 to 1/4.
- the mode register set signal MRS is activated when the chip enable signal /CE, the write enable signal /WE and the output enable signal /OE are at low logic levels ( Fig. 5 (a) ).
- the delay set signal DMRS and the all refresh signal AREFX are output ( Fig. 5 (b, c) ).
- the column address signals CAD0-1 change to levels L, H.
- the column address line CAD0 has a larger load than the column address line CAD1. Accordingly, the change of the address line CAD0 from the level H to the level L is later than the change of the address line CAD1 from the level L to the level H.
- a period of levels H, H occurs ( Fig. 5 (d) ).
- the latches LT shown in Fig. 3 output the levels of the column address signals CAD0-1 as the partial set signals PSET00,10 while the delay set signal DMRS is at a high logic level ( Fig. 5 (e) ), and latch the levels of the column address signals CAD0-1 in synchronization with a falling edge of the delay set signal DMRS ( Fig. 5 (f) ).
- the partial set signals PSET0-1 are output directly from the latches LT shown in Fig. 3 . Accordingly, when levels of the partial set signals PSET0-1 are both a level H, the partial refresh area PREFA is set to "NONE", and the refresh operation for the memory blocks BLK0-3 is disabled temporarily ( Fig. 5 (g) ).
- the frequency divider 1 8 shown in Fig. 1 masks the refresh request signal RREQ0Z received during the period of "NONE", and does not activate the refresh request signal RREQZ ( Fig. 5 (h) ). As a result, the refresh operation in response to the refresh request signal RREQ0Z is not executed.
- the memory block BLK0 is a block for which the refresh operation is executed so as to retain data when the partial refresh area PREFA is changed to 1 /4. Therefore, in the memory cells MC for which the refresh operation is omitted, data are lost until the next refresh operation is executed.
- the all refresh signal AREFX is activated and the partial set signals PSET0-1 are fixed forcibly to low logic levels L regardless of the levels retained in the latches LT ( Fig. 5 (i) ). Accordingly, during this period, the partial refresh area PREFA is set to "ALL" temporarily. Therefore, the refresh request signal RREQZ is output in response to the refresh request signal RREQ0Z, and the refresh operation for the memory blocks BLK is executed ( Fig. 5 (j) ).
- the partial refresh area PREFA is switched from "1/2" to "1 /4" in synchronization with a rising edge of the all refresh signal AREFX ( Fig. 5 (k) ).
- Fig. 6 illustrates an operation of the memory MEM of the first embodiment.
- the frequency divider 18 shown in Fig. 1 outputs the refresh request signal RREQZ in synchronization with the refresh request signal RREQ0Z.
- the refresh address counter 28 shown in Fig. 1 changes the refresh address signals RRAD5-4 sequentially in synchronization with the refresh request signal RREQZ when the partial set signals PSET0-1 are at levels L, L. Then, in synchronization with the refresh request signal RREQZ, the refresh operation for the memory blocks BLK0-3 is executed sequentially.
- Fig. 1 illustrates an operation of the memory MEM of the first embodiment.
- REFBLK indicates the number of the memory block BLK for which the refresh operation is executed.
- the refresh address signals RRAD3-0 are output sequentially as shown in Fig. 9 .
- the lower order bits of the refresh address counter 28 are assigned for selection of the memory blocks BLK0-3, and the higher order bits thereof are assigned for selection of the word line WL in each of the memory blocks BLK0-3. Then, the word line WL coupled to the memory cells MC for which the refresh operation is executed is selected according to the refresh address signals RRAD3-0.
- the memory blocks BLK0-1 are set to the partial refresh area PREFA (1/2).
- the frequency divider 18 divides the refresh request signal RREQ0Z in two and outputs them as the refresh request signal RREQZ.
- the refresh address counter 28 fixes the refresh address signal RRAD5 to a low logic level L when the partial set signals PSET0-1 are at levels H, L. Accordingly, only the refresh address signal RRAD4 changes sequentially in synchronization with the refresh request signal RREQZ. Then, in synchronization with the refresh request signal RREQZ, the refresh operation for the memory blocks BLK0-1 is executed sequentially.
- the frequency divider 18 divides the refresh request signal RREQ0Z into four and outputs them as the refresh request signal RREQZ.
- the refresh address counter 28 fixes the refresh address signals RRAD4-5 to low logic levels L when the partial set signals PSET0-1 are at levels L, H. Accordingly, the refresh operation for the memory block BLK0 is executed sequentially in synchronization with the refresh request signal RREQZ.
- the partial refresh area PREFA is not set (NONE).
- the frequency divider 18 disables output of the refresh request signal RREQZ.
- the refresh address counter 28 holds the refresh address signals RRAD4-5 to low logic levels L or high logic levels H when the partial set signals PSET0-1 are at levels H, H. Accordingly, the refresh operation for all the memory blocks BLK0-3 is disabled. In other words, the refresh block REFBLK does not exist.
- the refresh address counter 28 fixes the logic of at least one bit of the refresh address signals RRAD4-5 according to the partial set signals PSET0-1.
- the generated refresh address signal RRAD changes according to change of the cycle of the refresh request signal RREQZ. Accordingly, the refresh cycle of each memory cell MC becomes constant without depending on the size of the partial refresh area PREFA. Therefore, data retained in the memory cells MC included in the partial refresh area PREFA will not disappear.
- the mode register set command MRS while the mode register set command MRS is set, it is possible to prevent masking of a refresh operation even when the timing of changing the partial refresh information by the mode register 12 and the timing of occurrence of the refresh request signal RREQZ overlap.
- the partial refresh area PREFA is set forcibly to "ALL".
- Fig. 7 illustrates a second embodiment of the present invention.
- the same elements as those explained in the first embodiment are given the same reference signs, and detailed explanation thereof is omitted.
- a refresh address counter 28A is formed instead of the refresh address counter 28 of the first embodiment.
- the frequency divider 18 of the first embodiment is deleted, and a refresh selection circuit 40A is added instead.
- the other structure is the same as in the first embodiment.
- the system SYS of this embodiment has the same structure as in Fig. 2 .
- the partial refresh area PREFA is the same as in Fig. 4 .
- the refresh selection circuit 40A has a function to mask the refresh request signal RREQZ based on the values of the partial set signals PSET0-1 (partial refresh area PREFA) and the refresh address signals RRAD4-5.
- the refresh address counter 28A updates the refresh address signals RRAD (RRAD0-5) sequentially in synchronization with the refresh request signal RREQ0Z regardless of the values of the partial set signals PSET0-1.
- Fig. 8 illustrates details of the refresh selection circuit 40A shown in Fig. 7 .
- the refresh selection circuit 40A has a NAND gate, AND circuits AND1-4, an OR circuit OR1, and a NOR gate.
- the NAND gate activates the refresh mask signal RMSKX to a low level when the partial set signals PSET0-1 indicate "H, H (NONE)".
- the AND circuit AND1 masks the refresh request signal RREQ0Z while the refresh mask signal RMSKX is activated.
- the refresh operation for the memory blocks BLK with blank spaces in the state "NONE" shown in Fig. 4 is masked.
- the AND circuit AND2 outputs a high logic level so as to mask the refresh request signal RREQZ when the partial set signal PSET1 indicates "H” and the refresh address signal RRAD4 is at a high logic level. Specifically, when the partial refresh area PREFA includes "1 /4", the refresh operation for the memory blocks BLK1,3 is disabled.
- the OR circuit OR1 outputs a high logic level when the partial set signal PSET0 or PSET1 is at a high logic level, in other words, the partial refresh area PREFA is other than "ALL".
- the AND circuit AND3 outputs a high logic level so as to mask the refresh request signal RREQZ when the partial refresh area PREFA is set to other than "ALL", and the refresh address signal RRAD5 is at a high logic level. In other words, when the partial refresh area PREFA includes "1/2" or "1 /4", the refresh operation for the memory blocks BLK2,3 is disabled.
- the NOR gate inactivates a refresh enable signal RENZ to a low logic level in response to a high logic level from the AND circuit AND2 or AND3, and activates the refresh enable signal RENZ to a high logic level in response to a low logic level from the AND circuits AND2 and AND3.
- the AND circuit AND4 outputs the refresh request signal RREQ0Z supplied via the AND circuit AND1 as the refresh request signal RREQZ while the refresh enable signal RENZ is activated. Further, the AND circuit AND4 masks an output of the refresh request signal RREQZ in response to the refresh request signal RREQ0Z while the refresh enable signal RENZ is inactivated.
- Fig. 9 illustrates an operation of the memory MEM of the second embodiment.
- the refresh address counter 28A updates the refresh address signals RRAD0-5 sequentially in response to the refresh request signal RREQ0Z.
- the other operation is the same as in the first embodiment ( Fig. 6 ).
- the refresh address signals RRAD0-5 are updated after the internal row address signal IRAD (refresh address) corresponding to the refresh request signal RREQ0Z is supplied to the memory core 38.
- the same effects as in the above-described first embodiment can be obtained.
- some pulses of the reference refresh request signal RREQ0Z are masked according to the partial set signals PSET0-1 and the refresh address signals RRAD4-5, and the rest of the pulses which are not masked are output as the refresh request signal RREQZ.
- Fig. 10 illustrates a third embodiment of the present invention.
- a synchronous circuit SYNC is formed between the filter circuit FLT and the frequency divider 18 and the refresh address counter 28 of the first embodiment.
- the other structure is the same as in the first embodiment.
- the semiconductor memory MEM is, for example, an FCRAM (Fast Cycle RAM) of pseudo SRAM type.
- FCRAM Fast Cycle RAM
- the system SYS of this embodiment has the same structure as in Fig. 2 .
- the partial refresh area PREFA is the same as in Fig. 4 .
- Fig. 11 illustrates details of the mode register 12, the filter circuit FLT and the synchronous circuit SYNC shown in Fig. 10 .
- the mode register 12 and the filter circuit FLT are the same as in the first embodiment ( Fig. 3 ).
- the synchronous circuit SYNC has a pair of master-slave flip-flops MSF/F coupled in series for outputting the partial set signal PSET0, and a pair of master-slave flip-flops MSF/F coupled in series for outputting the partial set signal PSET1.
- Each flip-flop MSF/F receives an input signal during a period in which the refresh request signal RREQ0Z is at a high logic level, latches the value of an input signal received in synchronization with a falling edge of the refresh request signal RREQ0Z, and outputs the latched value.
- the flip-flop MSF/F in the front stage latches partial set signals PS00, PS01 from the AND circuit, and outputs the latched values as partial set signals LPS0, LPS1.
- the flip-flop MSF/F in the rear stage latches the partial set signals LPS0, LPS1 and outputs the latched values as the partial set signals PSET0-1.
- Fig. 12 illustrates operations of the mode register 12, the filter circuit FLT and the synchronous circuit SYNC shown in Fig. 11 .
- the waveforms up to output of the latches LT (PS0, PS1) are the same as in the first embodiment ( Fig. 5 ).
- the refresh request signal RREQ0Z occurs at almost the same timing as a rising edge of the all refresh signal AREFX.
- Timing of supplying the mode register set command MRS to the memory MEM and the timing of occurrence of the refresh request signal RREQ0Z are asynchronous, and hence the state shown in Fig. 12 occurs at a predetermined probability.
- the flip-flops MSF/F in the front stage operate at timing when the partial set signals PS0-1 change from “ALL” to "1 /4" in synchronization with a falling edge of the refresh request signal RREQ0Z.
- the flip-flops MSF/F output the partial set signals LPS0-1 indicating "ALL” or "1 /4" ( Fig. 12 (a) ).
- the flip-flops MSF/F in the front stage output the partial set signals LPS0-1 indicating "1 /4" ( Fig. 12 (b)
- the flip-flops MSF/F in the rear stage output the partial set signals PSET0-1 indicating "ALL” or "1 /4" ( Fig. 12 (d) ).
- the flip-flops MSF/F in the rear stage output the partial set signals PSET0-1 indicating "1 /4" ( Fig. 12 (d) ).
- the partial refresh area PREFA is set to "1 /4" in response to the third refresh request signal RREQ0Z from the mode register set command MRS.
- a period needed for occurrence of the third refresh request signal RREQ0Z is 30 ⁇ s for example.
- the largest cycle of the refresh operation needed for the memory cells MC to retain data is 32 ms for example. Accordingly, the delay of 30 ⁇ s of the refresh operation does not affect the memory operation.
- the partial set signals PSET0-1 are changed after output of pulses of the refresh request signals RREQ0Z, RREQZ in synchronization with the refresh request signal RREQ0Z. Accordingly, it is possible to prevent switching of the partial set signals PSET0-1 while pulses of the refresh request signal RREQZ are output, and to prevent stopping of output of the pulses of the refresh request signal RREQZ in the middle due to the switching.
- the pulse width of the refresh request signal RREQZ is short, the operation control circuit 26 is not able to receive the refresh request signal RREQZ properly, and hence there is a danger that the proper refresh operation cannot be executed.
- the refresh address counter 28 updates the refresh address signals RRAD after the internal row address signal IRAD corresponding to the refresh request signal RREQZ is supplied to the memory core 38. Further, in this embodiment, the refresh address signals RRAD are updated after the partial set signals PSET0-1 are switched ( Fig. 12 (e) ). Accordingly, it is possible to prevent deviation of the refresh address signals RRAD corresponding to the refresh request signals RREQ0Z, RREQZ.
- the same effects as in the above-described first and second embodiments can be obtained.
- this embodiment by synchronizing with the refresh request signal RREQ0Z changing of the partial refresh area PREFA which occurs asynchronously with occurrence of the refresh request signal RREQ0Z, it is possible to prevent that the refresh area PREFA is changed during a switching operation of the frequency divider 18.
- switching the partial set signals PSET0-1 always after the timing of occurrence of the refresh request signal RREQ0Z it is possible to prevent overlap of the timing of switching the partial set signals PSET0-1 and the timing of occurrence of the refresh request signal RREQZ. Consequently, it is possible to prevent the pulse width of the refresh request signal RREQZ output from the frequency divider 18 from becoming narrow, and to prevent malfunctioning of the memory MEM.
- Fig. 13 illustrates a fourth embodiment of the present invention.
- the same synchronous circuit SYNC as that of the third embodiment is formed between the filter circuit FLT and the refresh selection circuit 40A of the second embodiment.
- the semiconductor memory MEM is, for example, an FCRAM (Fast Cycle RAM) of pseudo SRAM type.
- the system SYS of this embodiment has the same structure as in Fig. 2 .
- the partial refresh area PREFA is the same as in Fig. 4 .
- Fig. 14 illustrates a fifth embodiment of the present invention.
- the same elements as those explained in the first and second embodiments are given the same reference signs, and detailed explanation thereof is omitted.
- a mode register 12D and a refresh selection circuit 40D are formed instead of the mode register 12 and the refresh selection circuit 40A of the second embodiment.
- the semiconductor memory MEM is, for example, an FCRAM (Fast Cycle RAM) of pseudo SRAM type.
- the system SYS of this embodiment has the same structure as in Fig. 2 .
- the partial refresh area PREFA is different from that in Fig. 4 .
- the mode register 12D outputs partial selection signals PSEL4-5 for replacing the partial refresh area PREFA. Accordingly, to set the logic values of the partial selection signals PSEL4-5, the mode register 12D receives the column address signal CAD which is two bit larger than in the first and second embodiments.
- the refresh selection circuit 40D recognizes the partial refresh area PREFA according to the partial set signals PSET0-1 and the partial selection signals 4-5, and outputs the refresh request signal RREQZ in synchronization with only the refresh request signal RREQ0Z corresponding to the partial refresh area PREFA.
- Fig. 15 illustrates details of the refresh selection circuit 40D shown in Fig. 14 .
- the refresh selection circuit 40D has logic gates EOR1 , EOR2 coupled to inputs of the AND circuits AND2, AND3 respectively.
- the logic gate EOR1 calculates an exclusive OR of the row address signal RRAD4 and the partial selection signal PSEL4.
- the logic gate EOR2 calculates an exclusive OR of the row address signal RRAD5 and the partial selection signal PSEL5.
- the other structure is the same as the refresh selection circuit 40A ( Fig. 8 ) of the second embodiment.
- Fig. 16 illustrates the partial refresh area PREFA of the fifth embodiment.
- the memory blocks BLK indicated by hatching are the partial refresh area PREFA for which the refresh operation is executed. In the memory blocks BLK indicated by blank spaces, the refresh operation is disabled.
- the partial refresh area PREFA when the partial refresh area PREFA is set to "1/2", the partial refresh area PREFA is set to the memory blocks BLK to which the refresh address signal RRAD5 having the same logic as that of the partial selection signal PSEL5 is assigned. For example, when the partial selection signal PSEL4 is at an L level, the partial refresh area PREFA is set to the memory blocks BLKO-4.
- the partial refresh area PREFA is set to "1 /4"
- the partial refresh area PREFA is set to the memory blocks BLK to which the refresh address signals RRAD4-5 having the same logic as that of the partial selection signals PSEL4-5 are assigned.
- the partial selection signals PSEL4-5 are at an H level, an L level, the partial refresh area PREFA is set to the memory block BLK1.
- the same effects as in the above-described first and second embodiments can be obtained. Further, in this embodiment, in the memory MEM in which the partial refresh area PREFA can be replaced, it is possible to prevent masking of the necessary refresh operation, and to prevent disappearance of data retained in the memory cells MC. That is, malfunctioning of the memory MEM can be prevented.
- Fig. 17 indicates a sixth embodiment of the present invention.
- values (partial refresh area PREFA) set to the latches LT in the mode register 12 ( Fig. 3 ) are supplied not via the address signal CAD but via a dedicated partial set terminal PSET.
- the semiconductor memory MEM is, for example, an FCRAM (Fast Cycle RAM) of pseudo SRAM type.
- the system SYS of this embodiment has the same structure as in Fig. 2 , except that it has a signal line to supply a partial set signal (external input) to the partial set terminal PSET.
- the partial refresh area PREFA is the same as in Fig. 4 .
- the same effects as in the above-described first embodiment can be obtained.
- the flip-flops MSF/F may be operated in synchronization with the oscillating signal OSC.
- Fig. 19 illustrates operations of the mode register 12, the filter circuit FLT, and the synchronization circuit SYNC shown in Fig. 18 .
- the cycle of the oscillating signal OSC is 1 ⁇ s for example, which is one-tenth of the cycle (10 ⁇ s) of the refresh request signal RREQ0Z.
- the filter circuit FLT2 can set the partial set signals PSET0-1 to "1 /4" before the second refresh request signal RREQ0Z occurs.
- the present invention may be applied to a DRAM having a self-refresh mode.
- the DRAM may be either of clock asynchronous type and clock synchronous type.
- the system SYS may be formed by mounting on the system board SBRD an SoC (System on Chip) including at least the CPU, the memory controller MCNT, and the flash controller FCNT.
- SoC System on Chip
- a proposition of the embodiments is to prevent malfunctioning of a semiconductor memory by securely executing a refresh operation even when changing of a partial refresh area and a refresh request overlap.
- a refresh set circuit sets partial refresh information indicating enabling/disabling of a refresh operation for each of the memory blocks according to an external input, and outputs the set partial refresh information as a partial set signal.
- a refresh request generation circuit outputs periodically a refresh request signal corresponding to a memory block for which enabling is indicated by the partial set signal.
- a refresh address counter generates in response to the refresh request signal a refresh address signal indicating a memory cell for which a refresh operation is executed.
- An operation control circuit executes a refresh operation for one of the memory blocks in response to the refresh request signal.
- a filter circuit masks the partial set signal from the refresh set circuit and outputs a partial set signal indicating enabling of a refresh operation for all of the memory blocks to the refresh request generation circuit during a period in which the partial refresh information is changed by the external input.
- the refresh request generation circuit has a refresh generation circuit and a frequency divider.
- the refresh generation circuit generates a reference refresh request signal periodically.
- the frequency divider divides a frequency of the reference refresh request signal according to a value of the partial set signal, and outputs divided signals as the refresh request signal.
- the refresh address counter fixes logic of at least one bit of the refresh address signal according to the partial set signal.
- the refresh request generation circuit has a refresh generation circuit and a refresh selection circuit.
- the refresh selection circuit masks a part of pulses of the reference refresh request signal according to the partial set signal and the refresh address signal, and outputs the rest of the pulses which are not masked as the refresh request signal. Accordingly, in response to the refresh request signal, a refresh operation for only the memory block corresponding to the partial set signal can be executed sequentially.
- the synchronous circuit synchronizes the partial set signal from the filter circuit with the reference refresh request signal and outputs the synchronized signal to the refresh request generation circuit. Accordingly, the partial set signal can be switched always after the timing of occurrence of the reference refresh request signal. In other words, it is possible to prevent overlap of the timing of switching the partial set signal and the timing of occurrence of the refresh request signal. For example, it is possible to prevent masking of pulses of the refresh request signal while being output by switching of the partial set signal. Consequently, the refresh operation can be executed securely, and malfunctioning of the semiconductor memory can be prevented.
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Claims (17)
- Halbleiterspeicher (MEM) mit:einer Vielzahl von Speicherblöcken (BLK0-3), die jeweils dynamische Speicherzellen (MC) haben;einer Auffrischeinstellschaltung (LT), die Partialauffrischinformationen, die ein Freigeben/Sperren einer Auffrischoperation für jeden der Speicherblöcke (BLK0-3) angeben, gemäß einer externen Eingabe einstellt und die eingestellten Partialauffrischinformationen als Partialeinstellsignal (PSET0-1) ausgibt;einer Auffrischaufforderungserzeugungsschaltung, die periodisch ein Auffrischaufforderungssignal (RREQZ) ausgibt, das dem Speicherblock (BLK) entspricht, für den durch das Partialeinstellsignal (PSET0-1) das Freigeben angegeben wird;einem Auffrischadressenzähler (28, 28A), der als Antwort auf das Auffrischaufforderungssignal (RREQZ) ein Auffrischadressensignal (RRAD) erzeugt, das die Speicherzelle (MC) angibt, für die die Auffrischoperation ausgeführt wird; undeiner Operationssteuerschaltung (26), die die Auffrischoperation für einen der Speicherblöcke (BLK0-3) als Antwort auf das Auffrischaufforderungssignal (RREQZ) ausführt; gekennzeichnet durch:eine Filterschaltung (FLT), die das Partialeinstellsignal (PSET0-1) von der Auffrischeinstellschaltung (LT) maskiert und das Partialeinstellsignal (PSET0-1), welches das Freigeben der Auffrischoperation für alle Speicherblöcke (BLK0-3) angibt, an die Auffrischaufforderungserzeugungsschaltung während einer Periode ausgibt, in der die Partialauffrischinformationen durch die externe Eingabe verändert werden.
- Halbleiterspeicher (MEM) nach Anspruch 1, bei dem:die Auffrischaufforderungserzeugungsschaltung umfasst :eine Auffrischerzeugungsschaltung (16), die ein Referenzauffrischaufforderungssignal (RREQOZ) periodisch erzeugt, undeinen Frequenzteiler (18), der eine Frequenz des Referenzauffrischaufforderungssignals (RREQOZ) gemäß einem Wert des Partialeinstellsignals (PSET0-1) teilt und geteilte Signale als Auffrischaufforderungssignal (RREQZ) ausgibt; undder Auffrischadressenzähler (28) die Logik von wenigstens einem Bit des Auffrischadressensignals (RRAD) gemäß dem Partialeinstellsignal (PSET0-1) fixiert.
- Halbleiterspeicher (MEM) nach Anspruch 1, bei dem
die Auffrischaufforderungserzeugungsschaltung umfasst:eine Auffrischerzeugungsschaltung (16), die ein Referenzauffrischaufforderungssignal (RREQOZ) periodisch erzeugt; undeine Auffrischselektionsschaltung (40A, 40D), die einen Teil von Impulsen des Referenzauffrischaufforderungssignals (RREQOZ) gemäß dem Partialeinstellsignal (PSET0-1) und dem Auffrischadressensignal (RRAD4-5) maskiert und den Rest der Impulse, die nicht maskiert sind, als Auffrischaufforderungssignal (RREQZ) ausgibt. - Halbleiterspeicher (MEM) nach Anspruch 1, ferner mit
einer Synchronschaltung (SYNC), die das Partialeinstellsignal (PSET0-1) von der Filterschaltung (FLT) mit dem Referenzauffrischaufforderungssignal (RREQOZ) synchronisiert und das synchronisierte Signal an die Auffrischaufforderungserzeugungsschaltung ausgibt. - Halbleiterspeicher (MEM) nach Anspruch 4, bei dem
die Synchronschaltung (SYNC) ein Paar von Flip-Flops (MSF/F) umfasst, die seriell gekoppelt sind, um das Partialeinstellsignal (PSET0-1) synchron mit dem Referenzauffrischaufforderungssignals (RREQOZ) sequentiell zu verriegeln. - Halbleiterspeicher (MEM) nach Anspruch 4, bei dem
die Synchronschaltung (SYNC) das Partialeinstellsignal (PSET0-1) ausgibt, bevor der Auffrischadressenzähler (28) das Auffrischadressensignal (RRAD) als Antwort auf das Auffrischaufforderungssignal (RREQZ) umschaltet. - Halbleiterspeicher (MEM) nach einem vorhergehenden Anspruch, ferner mit
einem Modusregister (12, 120), in dem eine Operationsspezifikation des Halbleiterspeichers (MEM) gemäß einer externen Eingabe eingestellt ist, bei dem
die Auffrischeinstellschaltung (LT) in dem Modusregister (12, 120) gebildet ist. - Halbleiterspeicher (MEM) nach einem vorhergehenden Anspruch, ferner mit
einem dedizierten Anschluss (PSET), der die Partialauffrischinformationen als externe Eingabe empfängt. - System (SYS), das den Halbleiterspeicher (MEM) nach Anspruch 1 und ferner einen Controller (CPU) umfasst, der eine Zugriffsaufforderung für den Halbleiterspeicher (MEM) ausgibt, bei dem:der Controller (CPU) die Partialauffrischinformationen für den Halbleiterspeicher (MEM) einstellt.
- Operationsverfahren eines Halbleiterspeichers (MEM), der eine Vielzahl von Speicherblöcken (BLK0-3) enthält, die jeweils dynamische Speicherzellen (MC) haben und als Antwort auf ein Zugriffsaufforderungssignal (AREQZ) von außen und ein im Inneren erzeugtes Auffrischaufforderungssignal (RREQZ) arbeiten, welches Verfahren umfasst:Einstellen von Partialauffrischinformationen, die ein Freigeben/Sperren einer Auffrischoperation für jeden der Speicherblöcke (BLK0-3) angeben, gemäß einer externen Eingabe und Ausgeben der eingestellten Partialauffrischinformationen als Partialeinstellsignal (PSET0-1);periodisches Ausgeben eines Auffrischaufforderungssignals (RREQZ), das dem Speicherblock (BLK) entspricht, für den durch die Partialeinstellsignale (PSET0-1) die Freigabe angegeben wird;Erzeugen, als Antwort auf das Auffrischaufforderungssignal (RREQZ), eines Auffrischadressensignals (RRAD), das die Speicherzelle (MC) angibt, für die die Auffrischoperation ausgeführt wird; undAusführen der Auffrischoperation für einen der Speicherblöcke (BLK0-3) als Antwort auf das Auffrischaufforderungssignal (RREQZ); gekennzeichnet durchMaskieren des Partialeinstellsignals (PSET0-1), um die Auffrischoperation für alle Speicherblöcke (BLK0-3) während einer Periode zu ermöglichen, in der die Partialauffrischinformationen durch die externe Eingabe verändert werden.
- Operationsverfahren des Halbleiterspeichers (MEM) nach Anspruch 10, ferner umfassend:periodisches Erzeugen eines Referenzauffrischaufforderungssignals (RREQOZ);Teilen einer Frequenz des Reterenzauffrischaufforderungssignals (RREQOZ) gemäß einem Wert des Partialeinstellsignals (PSET0-1) und Ausgeben geteilter Signale als Auffrischaufforderungssignal (RREQZ); undFixieren der Logik von wenigstens einem Bit des Auffrischadressensignals (RRAD) gemäß dem Partialeinstellsignal (PSET0-1).
- Operationsverfahren des Halbleiterspeichers (MEM) nach Anspruch 10, ferner umfassend:periodisches Erzeugen eines Referenzauffrischaufforderungssignals (RREQOZ);Maskieren einiger Impulse des Referenzauffrischaufforderungssignals (RREQOZ) gemäß dem Partialeinstellsignal (PSET0-1) und dem Auffrischadressensignal (RRAD4-5); undAusgeben des Restes der Impulse, die nicht maskiert sind, als Auffrischaufforderungssignal (RREQZ).
- Operationsverfahren eines Halbleiterspeichers (MEM) nach Anspruch 10, 11 oder 12, ferner mit dem Synchronisieren des Partialeinstellsignals (PSET0-1) mit dem Referenzauffrischaufforderungssignal (RREQOZ).
- Operationsverfahren des Halbleiterspeichers (MEM) nach Anspruch 13, ferner mit dem sequentiellen Verriegeln des Partialeinstellsignals (PSET0-1) synchron mit dem Referenzauffrischaufforderungssignal (RREQOZ).
- Operationsverfahren des Halbleiterspeichers (MEM) nach Anspruch 14, ferner mit dem Ausgeben des Partialeinstellsignals (PSET0-1) vor dem Umschalten des Auffrischadressensignals (RRAD) als Antwort auf das Auffrischaufforderungssignal (RREQZ).
- Operationsverfahren des Halbleiterspeichers (MEM) nach einem der Ansprüche 10 bis 15, ferner mit dem Einstellen der Partialauffrischinformationen in einem Modusregister (12, 12D), in dem eine Operationsspezifikation des Halbleiterspeichers (MEM) eingestellt wird.
- Operationsverfahren des Halbleiterspeichers (MEM) nach einem der Ansprüche 10 bis 16, ferner mit dem Empfangen der Partialauffrischinformationen als externe Eingabe durch einen dedizierten Anschluss (PSET).
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JP3834274B2 (ja) | 1999-12-03 | 2006-10-18 | Necエレクトロニクス株式会社 | 半導体記憶装置及びそのテスト方法 |
JP4749538B2 (ja) | 2000-12-11 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP2003068075A (ja) | 2001-08-28 | 2003-03-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6738861B2 (en) * | 2001-09-20 | 2004-05-18 | Intel Corporation | System and method for managing data in memory for reducing power consumption |
JP4246971B2 (ja) * | 2002-07-15 | 2009-04-02 | 富士通マイクロエレクトロニクス株式会社 | 半導体メモリ |
JP4516483B2 (ja) * | 2005-06-07 | 2010-08-04 | 富士通セミコンダクター株式会社 | 半導体記憶装置及び情報処理システム |
JP2008084426A (ja) * | 2006-09-27 | 2008-04-10 | Fujitsu Ltd | 半導体メモリおよびシステム |
JP4984872B2 (ja) * | 2006-12-15 | 2012-07-25 | 富士通セミコンダクター株式会社 | 半導体メモリ、半導体メモリの動作方法、メモリコントローラおよびシステム |
JP5262246B2 (ja) * | 2008-03-31 | 2013-08-14 | 富士通セミコンダクター株式会社 | 半導体記憶装置およびメモリシステム |
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CN101276640B (zh) | 2010-06-09 |
JP5098391B2 (ja) | 2012-12-12 |
EP1975941A1 (de) | 2008-10-01 |
JP2008243302A (ja) | 2008-10-09 |
CN101276640A (zh) | 2008-10-01 |
KR100918471B1 (ko) | 2009-09-24 |
DE602008003146D1 (de) | 2010-12-09 |
US7646660B2 (en) | 2010-01-12 |
KR20080088383A (ko) | 2008-10-02 |
US20080239854A1 (en) | 2008-10-02 |
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