EP1819982A1 - Mesure electrique de l'epaisseur d'une couche de semiconducteur - Google Patents

Mesure electrique de l'epaisseur d'une couche de semiconducteur

Info

Publication number
EP1819982A1
EP1819982A1 EP05814654A EP05814654A EP1819982A1 EP 1819982 A1 EP1819982 A1 EP 1819982A1 EP 05814654 A EP05814654 A EP 05814654A EP 05814654 A EP05814654 A EP 05814654A EP 1819982 A1 EP1819982 A1 EP 1819982A1
Authority
EP
European Patent Office
Prior art keywords
quadrupole
measured
arrangement
measurement
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05814654A
Other languages
German (de)
English (en)
Inventor
Karlheinz Freywald
Giesbert Hoelzer
Siegfried Hering
Uta Kuniss
Appo Van Der Wiel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Publication of EP1819982A1 publication Critical patent/EP1819982A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/02—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness
    • G01B7/06—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness for measuring thickness
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
    • G01N27/04—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
    • G01N27/041—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body

Definitions

  • the invention relates to a method for the electrical measurement of the thickness of semiconductor layers and an associated arrangement that can be used as a test structure, manufactured or manufactured in the normal component process of semiconductor structures using conventional test systems.
  • the trained as a test structure for example, annular arrangement, allows safe measurement and suppression of interfering interactions with adjacent structures.
  • JP-A 10 154 735 shows a special method for measuring thin SOI layers by means of siliconized regions.
  • the process requires special technological steps and is not generally applicable and is not intended or suitable for thicker semiconductor layers and for EPI layers and membranes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Automation & Control Theory (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

L'invention concerne un procédé de mesure électrique de l'épaisseur de couches de semiconducteur (10, 11, 12). Des couches actives sur des plaquettes de silicium sur isolant (SOI), des couches épitaxiales à conduction de type inverse et des épaisseurs de membrane peuvent être mesurées. A cet effet, on utilise une structure d'essai pouvant être mesurée de façon routinière au cours d'un processus de fabrication. Cette structure d'essai (A1 à F1) présente, de préférence, une forme annulaire, permettant d'obtenir un haut niveau de symétrie lors de la propagation du courant de mesure et d'éviter toute interférence avec les structures environnantes. Le "diamètre" de l'ensemble peut être adapté à la gamme d'épaisseurs correspondante de la couche de semiconducteur à mesurer. Cet ensemble peut être évalué au moyen de systèmes d'essai de paramètres UI classiques utilisés habituellement lors d'une fabrication de semiconducteur. L'épaisseur des couches est déterminée par deux mesures quadripolaires successives au niveau de six zones de contact.
EP05814654A 2004-11-16 2005-11-16 Mesure electrique de l'epaisseur d'une couche de semiconducteur Withdrawn EP1819982A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004055181A DE102004055181B3 (de) 2004-11-16 2004-11-16 Verfahren und Anordnung zur elektrischen Messung der Dicke von Halbleiterschichten
PCT/DE2005/002063 WO2006053543A1 (fr) 2004-11-16 2005-11-16 Mesure electrique de l'epaisseur d'une couche de semiconducteur

Publications (1)

Publication Number Publication Date
EP1819982A1 true EP1819982A1 (fr) 2007-08-22

Family

ID=35764705

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05814654A Withdrawn EP1819982A1 (fr) 2004-11-16 2005-11-16 Mesure electrique de l'epaisseur d'une couche de semiconducteur

Country Status (4)

Country Link
US (1) US20080100311A1 (fr)
EP (1) EP1819982A1 (fr)
DE (2) DE102004055181B3 (fr)
WO (1) WO2006053543A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006002753B4 (de) * 2006-01-20 2010-09-30 X-Fab Semiconductor Foundries Ag Verfahren und Anordnung zur Bewertung der Unterätzung von tiefen Grabenstrukturen in SOI-Scheiben
US8906710B2 (en) * 2011-12-23 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Monitor test key of epi profile
CN103235190B (zh) * 2013-04-19 2015-10-28 重庆金山科技（集团）有限公司 一种电阻抗测试方法
US10003149B2 (en) 2014-10-25 2018-06-19 ComponentZee, LLC Fluid pressure activated electrical contact devices and methods
US9577358B2 (en) * 2014-10-25 2017-02-21 ComponentZee, LLC Fluid pressure activated electrical contact devices and methods

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7008274A (fr) * 1970-06-06 1971-12-08
US4218650A (en) * 1978-06-23 1980-08-19 Nasa Apparatus for measuring semiconductor device resistance
JPS5737846A (en) * 1980-08-20 1982-03-02 Nec Corp Measuring device for thickness of semiconductor layer
US4703252A (en) * 1985-02-22 1987-10-27 Prometrix Corporation Apparatus and methods for resistivity testing
WO1994011745A1 (fr) * 1992-11-10 1994-05-26 David Cheng Procede et appareil permettant de mesurer l'epaisseur de films
DE19619686C2 (de) * 1996-04-18 1998-04-09 Fraunhofer Ges Forschung Halbleiter- oder hybridtechnologiebasierte Meßanordnung mit spezieller Impedanzanordnung
US6434217B1 (en) * 2000-10-10 2002-08-13 Advanced Micro Devices, Inc. System and method for analyzing layers using x-ray transmission
JP3928478B2 (ja) * 2002-05-22 2007-06-13 株式会社島津製作所 膜厚測定方法及び膜厚測定装置
US6943571B2 (en) * 2003-03-18 2005-09-13 International Business Machines Corporation Reduction of positional errors in a four point probe resistance measurement
US7212016B2 (en) * 2003-04-30 2007-05-01 The Boeing Company Apparatus and methods for measuring resistance of conductive layers
KR100556529B1 (ko) * 2003-08-18 2006-03-06 삼성전자주식회사 다층 박막의 두께 측정 방법 및 이를 수행하기 위한 장치

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006053543A1 *

Also Published As

Publication number Publication date
US20080100311A1 (en) 2008-05-01
DE112005003278A5 (de) 2007-09-27
DE102004055181B3 (de) 2006-05-11
WO2006053543A1 (fr) 2006-05-26

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