EP1643650A2 - Procédé et appareil pour la conversion analogique-numérique - Google Patents

Procédé et appareil pour la conversion analogique-numérique Download PDF

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Publication number
EP1643650A2
EP1643650A2 EP05108645A EP05108645A EP1643650A2 EP 1643650 A2 EP1643650 A2 EP 1643650A2 EP 05108645 A EP05108645 A EP 05108645A EP 05108645 A EP05108645 A EP 05108645A EP 1643650 A2 EP1643650 A2 EP 1643650A2
Authority
EP
European Patent Office
Prior art keywords
signal
digital
analog
converter
useful signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP05108645A
Other languages
German (de)
English (en)
Other versions
EP1643650A3 (fr
EP1643650B1 (fr
Inventor
Harald Tschentscher
Berthold Fehrenbacher
Christian Wenzel-Benner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
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Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1643650A2 publication Critical patent/EP1643650A2/fr
Publication of EP1643650A3 publication Critical patent/EP1643650A3/fr
Application granted granted Critical
Publication of EP1643650B1 publication Critical patent/EP1643650B1/fr
Expired - Fee Related legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1071—Measuring or testing
    • H03M1/1076—Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Definitions

  • the invention relates to a method for operating a converter arrangement for analog-to-digital conversion and to a converter arrangement for carrying out the method.
  • useful signals output by useful signal sources are input to at least one analog / digital converter of the converter arrangement and converted by the latter into a series of digital values.
  • connection lines on a route between the useful signal source and the converter arrangement are defective or interrupted, so that the analogue useful signal does not reach the converter arrangement, so that the digital values output by the converter do not correspond to the useful signal. It is therefore necessary to check these connection lines.
  • Known method for checking the connection line between a useful signal source and the Transducer assemblies employ a noise source having a high internal resistance that generates and outputs a noise level.
  • the interference signal level is superimposed on the useful signal, whereby an overlay signal is obtained, which is converted in the transducer arrangement into a digital signal.
  • the interference signal level is selected outside of a previously known or predetermined interval of possible useful signal levels.
  • the internal resistance of the interfering signal source is chosen to be much larger than the internal resistance of the useful signal source, so that during normal operation of the transducer assembly, if the connection line to Nutzsignalttle is error-free, the interfering signal does not significantly distort the useful signal and consequently the result of the conversion of the beat signal in the analogue Digital converter is not or not significantly different from that which would be obtained even when converting the pure, not superimposed useful signal.
  • a disadvantage of this technique is that the interval of the useful signal levels must be smaller than the level interval correctly processable by the converter. The resolution of the converter is therefore not optimally utilized under normal operating conditions. In addition, additional circuit elements may be required to ensure that the useful signal applied to the converter is always within the allowable interval at all times.
  • connection lines between Nutzsignaluzen and the transducer assembly are also verifiable, if the useful signal is not subject to permissible level restrictions, that is, if it can assume any level that the converter is capable of correctly converting.
  • the wanted signal may temporarily also assume levels that extend beyond the interval of the correctly changeable levels in both directions, which simplifies any preprocessing of the analogue useful signal before the conversion.
  • a transducer arrangement for carrying out the method according to the invention may comprise two or more analog / digital converters, of which z. B. one superimposed with the first noise level useful signal and the second with the second noise level superimposed useful signal receives. If both convert at the same time received beat signal levels, a loss of the useful signal is directly apparent from a discrepancy of the conversion results.
  • the transition time required by the payload to go from one of the two noise levels to the other is generally different from zero.
  • the two beat signals are sequentially and executed within a time shorter than said transition time. If, under these conditions, the difference between the first and the second digital value exceeds the limit, the cause may be only a lack of the useful signal due to defective lines, but not a change in the level of the useful signal. In this way, erroneous error messages are avoided.
  • the error message can basically be transferred directly to a responsible circuit component such as a control unit. However, it can also initially be entered into an error register, from which it can be read out at any later time from the circuit component if necessary.
  • the method according to the invention is carried out with recording of the operation of the analog / digital converter. This is particularly advantageous if an initial check of the connecting lines is sufficient when starting the operation of the converter arrangement. In order to ensure permanent monitoring during the operation of the converter arrangement, the method according to the invention can also advantageously be carried out cyclically during the operation of the analog / digital converter.
  • the error message is output in step (f) of claim 1 only when repeated execution of steps (a) to ( e) of claim 1 is determined at a predetermined number of successive executions of step (e) that the difference exceeds the limit.
  • a converter arrangement according to the invention may preferably include a memory which stores the digital values, as long as the digital values of subsequent circuit components are not needed immediately. Thus, the digital values can be read from memory as needed.
  • an error register may be provided for storing the error message in the transducer assembly when the comparator determines that the difference between the digital signals is a predetermined one Exceeds limit. This is particularly advantageous if data losses can occur in the following circuit components due to unforeseen reasons. In such cases, the digital signals or the error messages can be read out again at any time from the memory or the error register.
  • a transducer arrangement 1 according to the invention is shown in FIG.
  • the heart of the transducer assembly 1 is an analog / digital converter 2 with an input 3 and an output 4.
  • a connecting line 5 opens the transducer assembly 1 with an external useful signal source 18.
  • the useful signal source 18 has a low internal resistance 19 of a few ohms on.
  • a low-pass filter 15 is provided, which is formed from a capacitor 16 and a resistor 17.
  • the transducer assembly 1 includes except the analog / digital converter 2, two noise sources 6 and 8, two switches 10 and 11, a control unit 12, a capacitor 13, a memory 14, a comparator 20 and an error register 21.
  • a first interference signal source 6 has an internal resistance 7, while the second interference signal source 8 has an internal resistance 9.
  • the two internal resistances 7, 9 are on the order of about 500 k ⁇ .
  • the switch 10 the first interfering signal source 6 can be selectively connected to the connecting line 5, while the interfering signal source 8 can be connected to the switch 11 optionally with the connecting line 5.
  • the switches 10, 11 are actuated by the control unit 12.
  • the capacitor 13 is connected to the connection line 5 with a first connection between the interference sources 6, 8 and the input 3 of the analog / digital converter 2 and is grounded to a second connection.
  • An input of the memory 14 is connected to the output 4 of the analog / digital converter 2.
  • An output of the memory 14 is connected to a first input of the comparator 20 connected to the control unit 12, to an output of the comparator 20, the error register 21 is connected.
  • the control unit 12 controls the switches 10, 11 in such a way that the interference signal sources 6, 8 are alternately connected to the connection line 5 and thus each interference signal level generated by them is alternately superimposed on the useful signal on the connection line 5 to a respective superposition signal. In this case, the interference signal levels generated by the interference signal sources 6, 8 are different from each other.
  • These superposition signals initially cause an alternating charge of the capacitor 13, whereby a stabilization of the heterodyne signals on the connecting line 5 is achieved before they pass through the input 3 of the analog / digital converter 2 in the analog / digital converter 2 and there from this in Digital values are converted.
  • the digital values are output by the analog / digital converter 2 through the output 4 and stored in the memory 14. From the memory 14, the digital values of subsequent, not shown here, and responsible for circuit components can be read out as needed.
  • the control unit 12 controls the comparator 20 such that it respectively reads out pairs of first and second digital signals, each of which has been generated in direct succession, from the memory 14 and compares them with each other.
  • the comparator 20 first forms the difference between the two digital signals, and if this difference exceeds a predetermined limit, the comparator 20 outputs an error message which is stored in the error register 21. From the error register 21, this error message can be read out as required by subsequent circuit components.
  • Fig. 2 shows a voltage-time diagram, in which, inter alia, the useful signal 22 and the two voltage applied to the connecting line 5 noise level 23 and 24 are registered.
  • the time-varying useful signal 22 can assume any voltage level over time t.
  • the speed at which the useful signal 22 can change its level is limited by the low-pass filter 15.
  • the switches 10, 11 respectively switched after elapse of the period .DELTA.t, so that the marked in Fig. 2 noise signal levels 23, 24 alternately during the same length of time .DELTA.t on the connecting line 5 abut.
  • the two interference signal levels 23, 24 can therefore also be understood as a single interfering signal with a rectangular oscillating course.
  • the interference signal levels 23, 24 are seen as pure, not superimposed signals, which corresponds to the case of an interruption of the connecting line 5.
  • the two interference signal levels 23, 24 respectively correspond to constant voltage values U 1 and U 2 for superposition with the useful signal 22, wherein the voltage value U 1 of the first interference signal level is higher than the voltage value U 2 of the second interference signal level 24.
  • the connecting line 5 is not interrupted, that is, the useful signal 22 enters the transducer assembly 1.
  • the useful signal 22 is alternately superimposed on one of the noise signal 23, 24 generated by the interference voltage sources 6, 8.
  • the overlay signal levels 25, 26 resulting from these overlays are also shown in the diagram of FIG. 2. From the superposition of the useful signal 22 with the interference signal level 23 results in the superposition signal level 25, from the superposition of the interference signal level 24 with the useful signal 22 of the superposition signal level 26.
  • the input signal of the analog / digital converter 2 is made up piece by piece from the overlay signals 25 and 26 together.
  • the superposition signals 25, 26 are shown at an exaggerated distance from the useful signal 22 in order to clarify the facts. Because the internal resistances 7, 9 of the interference signal sources 6, 8 are in the range of 500 k ⁇ while the internal resistance 19 of the useful voltage source 18 is only a few ohms, the voltage difference between the signals 22, 25, 26 is in reality very small. In practice, it is preferably smaller than the resolution of the analog-to-digital converter 2, so that the first and second beat signals 25 and 26 provide mostly the same conversion results.
  • the superposition signal 25 in FIG. 2 assumes the voltage value U 2 of the interference signal level 24 at time t 1 , so that the voltage level present at the input of the analog / digital converter 2 can not be distinguished from the level that occurs when the line is interrupted 5 anläge.
  • the time interval ⁇ t 'lying between the times t 1 and t 2 is therefore essential longer than the period .DELTA.t, after which is switched between the noise levels 23, 24. Because of the sufficiently small time interval .DELTA.t is thus excluded that the overlay signals 25, 26 change within the short period of time .DELTA.t to take within this time once the voltage value U 1 and once the voltage value U 2 , or in other words, because the derivative dU (t) / dt of the curve for the useful signal 22 is too small after the time t for it.
  • the comparator 20 recognizes an interruption of the connection line 5: As explained above, the comparator 20 compares digital signals which are obtained after conversion of two directly successive beat signals 25, 26. The superposition signals 25, 26 follow one another at a time interval of ⁇ t. For the sake of simplicity, let it be assumed that the comparator 20 compares the digital signal obtained after converting the beat signal 25 at time t 1 to that digital signal which is obtained by ⁇ t later at time t 2 'after converting the respective beat signal 26. The comparison is to determine the difference between these digital signals. This difference corresponds to the voltage difference .DELTA.U 'shown in FIG.
  • connection line 5 is interrupted and the useful signal 22 no longer enters the transducer assembly 1 and no superposition signals 25, 26 are generated, but instead the interference signal level 23, 24 is not superimposed by the analog / digital converter 2 are converted, then at time t 1, the voltage level U 1 of the non-superimposed interfering signal 23 and at time t 2 ', the voltage level U 2 of the non-superimposed interfering signal 24 is converted.
  • the difference between the conversion results at times t 1 and t 2 'determined by the comparator 20 now corresponds to the significantly greater voltage difference ⁇ U between the two voltage levels U 1 and U 2 of the non-superimposed interference signals 23 and 24.
  • the comparator 20 To exclude any noise effects of the signals the comparator 20 a limit .DELTA.U G predetermined whose amount is just below the amount of the difference .DELTA.U between the voltages U 1 and U 2 is selected.
  • the error message is output to the error register 21 by the comparator 20 only when the difference between the digital signals determined by the comparator 20 exceeds this limit ⁇ U G.
  • the comparator 20 Based on the occurrence of the limit .DELTA.U G crossing voltage difference .DELTA.U the comparator 20 thus detects the faultiness of the connecting line 5, because in the case of the error-free connection line 5 such a large voltage difference .DELTA.U because of the much too low rate of change of the overlay signals 25, 25 within the short enough chosen Period ⁇ t can never occur.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
EP20050108645 2004-09-30 2005-09-20 Procédé et appareil pour la conversion analogique-numérique Expired - Fee Related EP1643650B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE200410048194 DE102004048194A1 (de) 2004-09-30 2004-09-30 Verfahren und Anordnung zum Analog/Digital-Wandeln

Publications (3)

Publication Number Publication Date
EP1643650A2 true EP1643650A2 (fr) 2006-04-05
EP1643650A3 EP1643650A3 (fr) 2007-03-14
EP1643650B1 EP1643650B1 (fr) 2008-03-05

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EP20050108645 Expired - Fee Related EP1643650B1 (fr) 2004-09-30 2005-09-20 Procédé et appareil pour la conversion analogique-numérique

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EP (1) EP1643650B1 (fr)
DE (2) DE102004048194A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013013939A1 (fr) * 2011-07-25 2013-01-31 Robert Bosch Gmbh Dispositif et procédé pour la surveillance continue d'une liaison électrique et d'un convertisseur analogique-numérique
EP2232663B1 (fr) 2007-12-05 2018-11-07 Solaredge Technologies Ltd. Mécanismes de sécurité, procédés d'éveil et d'arrêt dans des installations de puissance réparties

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6396426B1 (en) * 1998-10-05 2002-05-28 Texas Instruments Incorporated Embedded mechanism offering real-time self failure detection for an analog to digital converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6396426B1 (en) * 1998-10-05 2002-05-28 Texas Instruments Incorporated Embedded mechanism offering real-time self failure detection for an analog to digital converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2232663B1 (fr) 2007-12-05 2018-11-07 Solaredge Technologies Ltd. Mécanismes de sécurité, procédés d'éveil et d'arrêt dans des installations de puissance réparties
EP2232663B2 (fr) † 2007-12-05 2021-05-26 Solaredge Technologies Ltd. Mécanismes de sécurité, procédés d'éveil et d'arrêt dans des installations de puissance réparties
WO2013013939A1 (fr) * 2011-07-25 2013-01-31 Robert Bosch Gmbh Dispositif et procédé pour la surveillance continue d'une liaison électrique et d'un convertisseur analogique-numérique

Also Published As

Publication number Publication date
EP1643650A3 (fr) 2007-03-14
DE502005003065D1 (de) 2008-04-17
DE102004048194A1 (de) 2006-04-06
EP1643650B1 (fr) 2008-03-05

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