EP1597759A1 - Relaxation d'une couche mince a une temperature elevee apres son transfert - Google Patents

Relaxation d'une couche mince a une temperature elevee apres son transfert

Info

Publication number
EP1597759A1
EP1597759A1 EP04715982A EP04715982A EP1597759A1 EP 1597759 A1 EP1597759 A1 EP 1597759A1 EP 04715982 A EP04715982 A EP 04715982A EP 04715982 A EP04715982 A EP 04715982A EP 1597759 A1 EP1597759 A1 EP 1597759A1
Authority
EP
European Patent Office
Prior art keywords
layer
strained
substrate
vitreous
previous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04715982A
Other languages
German (de)
English (en)
Inventor
Bruno Ghyselen
Carlos Mazure
Emmanuel Arene
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of EP1597759A1 publication Critical patent/EP1597759A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the present invention relates to the formation of a relaxed or pseudo-relaxed layer on a substrate, the relaxed layer being in a material selected from among semiconductor materials, in order to form a final structure intended for electronics, optics or Optronics such as for example a semiconductor-on-insulator structure.
  • the present invention comprises in particular the formation of a layer strained on and by the relaxed layer.
  • a Si layer strained by a relaxed or pseudo-relaxed SiGe layer may in this respect achieve advantageous properties such as charge carrier mobility about 100% more significant than that present within a relaxed Si layer.
  • a layer is "relaxed” if the crystalline material of which it is composed has a mesh parameter approximately identical to its nominal mesh parameter, in other words to the mesh parameter of the material in its bulk form in equilibrium.
  • strained is applied to any layer of crystalline material whose crystalline structure is elastically strained in tension or in compression during crystal growth, such as epitaxy, forcing its mesh parameter to be appreciably different from the nominal mesh parameter of this material.
  • the technique is known of forming a relaxed layer on a substrate, particularly by implementing a method comprising the following steps;
  • a semiconductor-on-insulator structure can be made in this way, in which the semiconductor thickness is constituted at least partly by said thin relaxed layer and the insulating layer being usually formed during a step intermediate to step (1) and to step (2).
  • a known technique is the use of a donor substrate constituted by a carrier substrate and a buffer layer, the buffer layer containing plastic deformations so that the over-epitaxied thin layer is relaxed of all strain.
  • Such processes are for example described in the documents US 2002/0072130 and WO 99/53539.
  • a buffer layer is often long and costly to obtain.
  • the donor substrate does not include a buffer layer and the step (1) then consists in growing the thin layer in such a way that it is strained by the donor substrate.
  • a SiGe layer will be grown directly ' on a Si substrate, to a thickness such that the SiGe layer is strained overall.
  • a first technique of relaxing the SiGe layer described particularly in the document by B. Hollander et al. entitled "Strain relaxation of pseudomorphic Si ⁇ -x Ge x /Si(100) heterostructures after hydrogen or helium ion implantation for virtual substrate fabrication" (in Nuclear and Instruments and Methods in Physics Research B 175-177 (2001) 357- 367) consists in relaxing the SiGe layer, prior to the implementation of step (2), by implanting hydrogen or helium ions in the Si substrate at a set depth.
  • the strained layer thus seems to relax by means of the layer of glass turned viscous at the treatment temperature.
  • One advantage of this technique would be to use a layer of BPSG with a fairly low viscosity temperature TG (of the order of 625°C).
  • the viscosity of the BPSG layer obtained at these temperatures may have undesired effects, particularly on the structure of the treated wafer.
  • transistors are made in the relaxed or pseudo- relaxed SiGe layer or in a strained Si layer epitaxied on the relaxed or pseudo-relaxed SiGe layer, at a temperature above TQ, some of the strains may relax by means of the layer of glass turned viscous, removing strains from the Si layer and adding strains in the SiGe layer.
  • the present invention attempts to overcome this difficulty by proposing a method for forming a relaxed or pseudo-relaxed layer on a substrate, the relaxed layer being in a material selected from among semiconductor materials, comprising the following steps: a) growing on a donor substrate an elastically strained layer constituted by at least a material chosen from among semiconductor materials; b) forming on the strained layer, or on a receiver substrate, a vitreous layer made of a material which is viscous above a viscosity temperature of more than about 900°C; c) bonding a receiver substrate to the strained layer via the vitreous layer formed in step (b); d) removing the donor substrate, so as to form a structure comprising the receiver substrate, the vitreous layer and the strained layer; e) thermal treating the structure at a temperature close to or higher than the viscosity temperature, so as to relax at least a part of the elastic constraints in the strained layer.
  • the method further comprises a final step of crystal growth, on the structure, of a material chosen from among semiconductor materials, is implemented;
  • the step (b) comprises the two sequential operations: b1) growing a layer of semiconductor material on the strained layer; b2) applying controlled treatment to convert at least part of the layer formed in step (b1), into a material which is viscous above the viscosity temperature, thus forming the vitreous layer;
  • the method further comprises, prior to step (c), a formation of a bonding layer on at least one of the two bonding surfaces;
  • the bonding layer is of SiO 2 ;
  • the removal of substance at step (d) is essentially carried out by detachment at the level of an embrittlement zone present in the donor substrate, at a depth close to the thickness of the surface layer, by input of energy; - the method further comprises, prior to step (c), the formation of the embrittlement zone by implantation of atom species in the donor substrate;
  • step (a) further comprises, prior to step (a), a step of formation of the donor substrate comprising the following operations:
  • step (d) comprises selective chemical etching
  • step (b) the vitreous layer formed in step (b) is electrically insulating
  • the vitreous layer formed in step (b) is of Si ⁇ 2 ;
  • the donor substrate is of Si; and the strained layer is of Si ⁇ - x Ge x
  • the donor substrate comprises a Si bulk holding substrate (1-1 ) and a buffer structure (1-2, 1-3) adapting the lattice parameter from Si to
  • the strained layer comprises a Si strained layer (2-1) and a S . x Ge x strained layer (2-2) with x > z;
  • the layer grown at step (b1 ) is in Si and the controlled treatment applied during step (b2) is a controlled thermal oxidization treatment for transforming at least a portion of the Si of the layer formed during step (b1 ) into Si0 2 , thereby forming the SiO 2 vitreous layer;
  • step (e) comprises thermal treatment above about 900°C;
  • the vitreous layer formed at step (b) is electrically insulating and the structure formed is therefore a semiconductor-on-insulator structure, the semiconductor thickness of which comprises the strained layer which has been relaxed or pseudo-relaxed in step (e); - steps of preparing for the manufacturing of components and/or steps of manufacturing components in the strained layer or in a possibly over-epitaxied layer.
  • Figures 2a to 2i show the different steps in a second method according to the invention.
  • Figure 3 shows an example of a source wafer, with layers to be transferred grown on a buffer structure in SiGe.
  • a first objective of the present invention consists in forming a useful relaxed or pseudo-relaxed layer on a substrate.
  • a "useful layer” according to the invention is a layer intended to receive components for electronics, optics, or Optronics during treatments subsequent to the implementation of the method according to the invention.
  • a second objective of the present invention consists in forming on the relaxed or pseudo-relaxed layer a useful layer of strained material.
  • a third objective of the present invention is to make it possible to retain an at least relative relaxation strength of an initially strained layer, during high temperature thermal treatments.
  • Thermal treatments of this kind may be applied during epitaxial growth on the relaxed Si ⁇ -X G X layer, or during other processes, such as for example the making of components in the Si ⁇ -x Ge x layer and/or in an over- epitaxied layer, such as a strained Si layer.
  • the method according to the invention comprises the three main steps (1), (2) and (3) previously mentioned.
  • the wafer 10 is constituted by a donor substrate 1 and a strained Si ⁇ -x Ge x layer 2.
  • the latter is constituted entirely by monocrystalline Si which has the first mesh parameter.
  • This donor substrate 1 is then to advantage obtained by Czochralski growth.
  • the latter is a pseudo-substrate comprising an upper Si layer (not shown in figure 1), having an interface with the strained layer 2 and having a first mesh parameter at its interface with the strained layer 2.
  • the first mesh parameter of the upper layer is to advantage the nominal mesh parameter of Si, so that it is in a relaxed state.
  • the upper layer has additionally a sufficiently large thickness to be able to impose its mesh parameter on the overlying strained layer 2, without the latter significantly influencing the crystalline structure of the upper layer of the donor substrate 1.
  • the latter has a crystalline structure with a low density of structural defects, such as dislocations.
  • the strained layer 2 is constituted only by a single thickness of Si-i -x Ge x .
  • the concentration of Ge in this strained layer 2 is preferentially above 17%, i.e. a value of x above 0.17.
  • the material selected to constitute this strained layer 2 thus has a second nominal mesh parameter which is appreciably higher than the first mesh parameter.
  • the strained layer 2 formed is then strained elastically in compression by the donor substrate 1 , in other words it is strained from having a mesh parameter appreciably lower than the second nominal mesh parameter of the material of which it is composed, and therefore from having a mesh parameter close to the first mesh parameter.
  • the strained layer 2 has moreover preferentially an approximately constant atomic element composition.
  • the strained layer 2 is to advantage formed on the donor substrate 1 by crystal growth, such as epitaxy, using known techniques such as for example LPD, Chemical Vapour Deposition (CVD) and Molecular Beam Epitaxy (MBE).
  • crystal growth such as epitaxy
  • CVD Chemical Vapour Deposition
  • MBE Molecular Beam Epitaxy
  • crystalline materials constituting the donor substrate 1 and the strained layer 2 (in the vicinity of its interface with the carrier substrate 1) such that they have a sufficiently small difference between their first and their second respective nominal mesh parameters.
  • this difference in mesh parameter is typically between about 0.5% and about 1.5%, but can also have more significant values.
  • the strained layer 2 it is preferable for the strained layer 2 to be of approximately constant thickness, so that it presents approximately constant intrinsic properties and/or to facilitate the future bonding with the receiver substrate 5 (as shown in figure 1 e).
  • This critical elastic strain thickness depends mainly on the material selected for the strained layer 2 and on said mesh parameter difference with the donor substrate 1.
  • the man skilled in the art will refer to the prior art to learn the value of the critical elastic strain thickness of the material which he selects for the strained layer 2 formed on the donor substrate 1.
  • a typical thickness of between about 200A and 2000A will be chosen, preferentially between 200A and 500A adapting particularly the growth parameters.
  • the strained layer 2 therefore has a mesh parameter approximately in the vicinity of that of its growth substrate 1 and has internal elastic strains in compression.
  • a vitreous layer 4 is formed on the strained layer 2 or on the receiver substrate 7 .
  • the material constituting the vitreous layer 4 is such that it becomes viscous above a viscosity temperature TG.
  • a material is chosen for the composition of this vitreous layer 4, which has a high T G temperature, of about 900°C minimum.
  • This high viscosity temperature will make it possible to prevent the vitreous layer 4 from becoming viscous during high temperature thermal treatments, and in this way to prevent particularly the structure 30 or 40 (with reference to figures 1 h and 1 i) formed at method end to have a part of its crystallographic structure modified with this vitreous layer 4 turned viscous.
  • a single thermal treatment at a temperature around or above TQ will however be applied during the method according to the invention (with reference to figure 1 h) so as to relax the strained layer 2.
  • the material of the vitreous layer 4 can be one of the following materials: SiO 2 , SiO x N y .
  • the T G of the vitreous layer is changed typically between a T G of roughly that of SiO 2 (which may vary around 1150°C) and a T G of roughly that of Si 3 N (which is above 1500°C).
  • the TQ values of the vitreous layer 4 if they depend essentially on the material of the vitreous layer, may also fluctuate depending on the conditions in which it has been formed.
  • Doping elements may thus be added to the principal gaseous elements contained in the vitrification atmosphere, such as boron and phosphorus which may have the capacity to reduce the T G .
  • vitreous layer 4 it is preferable for the vitreous layer 4 to be deposited before the germanium contained in the strained layer 2 can diffuse into the atmosphere, or even into the receiver substrate 7, particularly when the assembly is subjected to high temperature thermal treatment, such as
  • RTA annealing treatment or a sacrificial oxidation treatment.
  • the following steps are implemented: (b1 ) with reference to figure 1 b, growing a layer 3 of semiconductor material on the strained layer 2; then
  • step (b2) with reference to figure 1c, applying a controlled treatment to convert at least part of the layer formed in step (b1) into a material which is viscous above the viscosity temperature, thus forming the vitreous layer 4.
  • the material chosen for the layer 3 is to advantage Si so as not to modify the strain in the strained layer 2.
  • the thickness of the formed layer 3 is typically between 5A and about 5000A, more particularly between 10 ⁇ A and about 1000A.
  • the crystal growth at step (b1 ) of the layer 3 is preferentially implemented before diffusion of the Ge, in other words shortly after:
  • the preferential method for growing the layer 3 is a growth in situ directly in continuation of the growth of the strained layer 2.
  • the growth technique used at step (b1) may be an epitaxy technique LPD, CVD, or MBE.
  • the vitreous layer 4 may be obtained by thermal treatment in an atmosphere with a preset composition.
  • a Si layer 3 may be subject at step (b2) to a controlled thermal oxidation treatment in order to convert this layer 3 into a vitreous layer 4 of Si0 2 .
  • the oxidising treatment parameters such as the temperature, duration, oxygen concentration, the other gases of the oxidising atmosphere, etc.
  • a dry oxygen or water vapour atmosphere will preferably be used, at a pressure equal to or above 1 atm.
  • this control may be achieved by playing on one or more other parameters, in combination or not with the time parameter.
  • the vitreous layer 4 and in replacement of said two steps (b1 ) and (b2) referenced by figures 1b and 1c respectively, there is applied, immediately after the growth of the strained layer 2 (in order to prevent the diffusion of the Ge), a deposition of atom species constituted by the vitreous material using atom species deposition means.
  • a deposition of atom species constituted by the vitreous material using atom species deposition means is applied, immediately after the growth of the strained layer 2 (in order to prevent the diffusion of the Ge), a deposition of atom species constituted by the vitreous material using atom species deposition means.
  • vitreous layer 4 alternative to the previous one, it is possible:
  • steps are shown of lifting the strained layer 2 and the vitreous layer 4 from the donor substrate 1 so as to transfer them to a receiver substrate 7.
  • the method according to the invention implements a technique composed of two main sequential steps:
  • the receiver substrate 7 is bonded to the vitreous layer 4.
  • an optional step of forming a bonding layer on the surface of the receiver substrate 7 may be implemented, this bonding layer having binding properties, at ambient temperature or at higher temperatures, with the material of the vitreous layer 4.
  • forming a layer of Si0 2 on the receiver substrate 7 may improve the quality of bonding, particularly if the vitreous layer 4 is SiO 2 .
  • This bonding layer of Si0 2 is then obtained to advantage by deposition of atom species of Si0 2 or by thermal oxidation of the surface of the receiver substrate 7 if its surface is Si.
  • a bonding surface preparation step is to advantage applied, prior to the bonding, in order to render these surfaces as smooth and as clean as possible.
  • Adapted chemical treatments for cleaning the bonding surfaces may be applied, such as light chemical etching, RCA treatment, ozonised baths, flushing operations, etc.
  • Mechanical or mecano-chemical treatments may also be applied, such as polishing, abrasion, Chemical Mechanical Planarisation (CMP) or atom species bombardment.
  • CMP Chemical Mechanical Planarisation
  • Bonding as such is achieved by bringing the bonding surfaces into contact with each other.
  • the bonds are preferentially molecular in nature making use of the hydrophilic properties of the bonding surfaces.
  • the two structures to be bonded may previously be subject to immersion operations in baths, such as for example flushing in deionised water.
  • the bonded assembly may additionally be annealed in order to reinforce the bonds, for example modifying the nature of the bonds, such as covalent bonds or other bonds.
  • vitreous layer 4 is of SiO 2
  • annealing may enhance the bonds, particularly if a bonding layer of SiO 2 has been formed prior to bonding on the receiver substrate 7.
  • bonding techniques reference may be made particularly to the document entitled "Semiconductor Wafer Bonding" (Science and technology, Interscience Technology) by Q. Y. Tong, U. G ⁇ sele and Wiley.
  • this embrittlement zone 6 is a zone approximately parallel to the bonding surface and has brittleness in the bonds between the lower part 1A of the donor substrate 1 and the upper part 1 B of the donor substrate 1 , these brittle bonds being able to be broken under an input of energy, such as thermal or mechanical energy.
  • a technique called Smart-Cut® is applied which comprises firstly an implantation of atom species in the donor substrate 1 , at the level of the embrittlement zone 6.
  • the species implanted may be hydrogen, helium, a mix of these two species or other light species.
  • Implantation takes place preferably just prior to bonding.
  • the implantation energy is selected so that the species, implanted through the surface of the vitreous layer 4, pass through the thickness of the vitreous layer 4, the thickness of the strained layer 2 and a set thickness of the upper part 1 B of the receiver substrate 1.
  • the strained layer 2 It is preferable to implant sufficiently deeply in the donor substrate 1 for the strained layer 2 not to be subjected to damage during the step of detaching the donor substrate 1.
  • the depth of implant in the donor substrate is thus typically about 1000A.
  • the brittleness of the bonds in the embrittlement zone 6 is found principally by the choice made in proportioning the implanted species, the proportioning being thus typically between 10 16 cm “2 and 10 17 cm “2 , and more exactly between about 2.10 16 cm -2 and about 7.10 16 cm “2 . Detachment at the level of this embrittlement zone 6 is then usually effected by input of mechanical and/or thermal energy.
  • the embrittlement layer 6 is here obtained before the formation of the strained layer 2, and at the time of formation of the donor substrate 1.
  • Making the embrittlement layer comprises the following main operations: ⁇ forming a porous layer on a carrier substrate 1A of Si; o growing a Si layer 1B on the porous layer.
  • the carrier substrate 1A-porous layer- Si layer 1B assembly then constitutes the donor substrate 1 , and the porous layer then constitutes the embrittlement zone 6 of the donor substrate 1.
  • An input of energy such as an input of thermal and/or mechanical energy, at the level of the porous embrittlement zone 6, then leads to a detachment of the carrier substrate 1 A from the layer 1 B.
  • a strained layer 2 and a possible other part of a donor substrate and/or other layers may be reformed on the removed part 1A, preferably after the surface of the removed part 1A has been polished.
  • finish material is removed allowing the remaining part 1 B to be removed. Finish techniques such as polishing, abrasion, Chemical
  • CMP Mechanical Planarization
  • thermal RTA annealing sacrificial oxidation
  • chemical etching taken alone or in combination can be applied to remove this part 1 B and to perfect the stack (reinforcing the bonding interface, eliminating roughness, curing defects, etc.).
  • a selective chemical etching taken in combination or not with mechanical means, is applied at least at the step end.
  • solutions based on KOH, NH 4 OH (ammonium hydroxide), TMAH, EDP or HNO 3 or solutions currently being studied combining agents such as HNO 3 , HN0 2 H 2 O 2 , HF, H 2 S0 4 , H 2 SO 2 , CH3COOH, H 2 0 2 , and H 2 O may to advantage be employed in order to etch the Si part 1B selectively in respect of the strained Si- ⁇ -x Ge x layer 2.
  • the material or materials of the donor substrate 1 to be removed may for example be etched possibly selectively, according to an "etch- back" process.
  • This technique consists in etching the donor substrate 1 from the back side, in other words from the free surface of the donor substrate 1.
  • Dry etching operations may also be applied to remove the material, such as plasma etching or sputter etching.
  • the etching operation or operations may additionally be only chemical or electro-chemical or photo-electrochemical.
  • the etching operation or operations may be preceded by or followed by a mechanical attack on the donor substrate 1 , such as grinding, polishing, mechanical etching or sputtering with atom species.
  • the etching or etching operations may be accompanied by a mechanical attack, such as polishing possibly combined with action by mechanical abrasives in a CMP process.
  • All the above-mentioned techniques for removing material from the donor substrate 1 are proposed by way of example in the present document, but do not in anyway constitute a restriction, since the invention extends to all types of techniques able to remove material from the donor substrate 1 , in accordance with the method according to the invention.
  • figure 1g after removal of substance a structure is obtained comprising the receiver substrate 7, the vitreous layer 4 and the strained layer 2.
  • thermal treatment is then applied at a temperature close to or above the viscosity temperature TQ.
  • the main purpose of this thermal treatment is to relax the strains in the strained layer 2.
  • thermal treatment at a temperature above or around the viscosity temperature of the vitreous layer 4, will cause the latter layer to turn viscous, which will allow the strained layer 2 to relax at its interface with the vitreous layer 4, leading to decompression of at least some of its internal strains.
  • the vitreous layer 4 is of SiO 2 , obtained by thermal oxidation
  • thermal treatment at about 1050°C minimum, preferentially at about 1200°C minimum, for a preset time will cause a relaxation or pseudo-relaxation of the strained layer 2.
  • the thermal treatment lasts typically from a few seconds to several hours.
  • the strained layer 2 therefore becomes a relaxed layer 2'.
  • Other effects of the thermal treatment on the structure may be sought, apart from the relaxation of the strained layer 2.
  • a second objective sought when the thermal treatment is applied may additionally be to obtain a bonding reinforcement anneal between the receiver substrate 7 and the vitreous layer 4.
  • the temperature selected for the thermal treatment is above or around the viscosity temperature of the vitreous layer 4, the latter, turned temporarily viscous, may create particular and stronger adhesion bonds with the receiver substrate 7.
  • This structure 30 is a Silicon Germanium On Insulator (SGOI) structure where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer 4 of SiO 2 .
  • SGOI Silicon Germanium On Insulator
  • the layer of relaxed Si 1-x Ge ⁇ 2' of this structure then presents a surface having a surface roughness compatible with a growth of another crystalline material.
  • a light surface treatment, such as polishing, adapted to Si ⁇ - x Ge x may possibly be applied to improve the surface properties.
  • a Si layer 11 is then grown on the relaxed Si ⁇ . x Ge x 2' layer with a thickness appreciably less than the critical strain thickness of the material of which it is composed, and which is therefore strained by the relaxed Si ⁇ _ x Ge x
  • This structure 40 is a Si/SGOI structure where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer 4 of SiO 2 .
  • the method is the same on the whole as that described with reference to figures 1 a to 1 i, with the exception of the step of conversion of the layer 3 into a vitreous layer 4 which is here implemented in such a way that the whole layer 3 is not converted.
  • This inserted layer 5 is made in such a way that it has a typical thickness of around 10 nm at all events very much less than that of the strained layer 2.
  • the strained layer 2 will seek to reduce its internal elastic strain energy by using the properties of viscosity of the vitreous layer 4 turned viscous, and, given that the inserted layer 5 is of less thickness relative to the overlying strained layer 2, the strained layer 2 will impose its relaxation requirement on the inserted layer 5.
  • the strained layer 2 thus forces the inserted layer 5 at least partially to strain.
  • the strained layer 2 then becomes a relaxed layer 2' at least partially.
  • the structure formed is then a structure 30 composed of relaxed Si ⁇ -x Ge x /strained Si/vitreous layer 4/receiver substrate 7.
  • This structure 30 is a SG/SOI structure, where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer 4 of SiO 2 .
  • This structure is a strained SOI structure, where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer " 4 of Si0 2 .
  • a Si layer may be grown, with reference to figure 2i, repeated on the relaxed layer 2' so as to form a strained Si layer 11 , approximately identical to the one in figure 1 i.
  • the structure formed is then a structure 40 composed of strained Si/relaxed Si ⁇ - x Ge x /strained Si/vitreous layer 4/receiver substrate 7.
  • This structure 40 is a Si/SG/SOI structure, where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer 4 of Si0 2 .
  • the thermal treatment to relax the strains of the strained layer 2 is carried out at a temperature and for a time period greater respectively than a temperature and a reference time period beyond which the Ge diffuses in the Si, the Ge contained in the strained layer 2 may diffuse into the inserted strained layer 5'. This is why it is preferable to implement the relaxation of the strained SiGe layer 2 before the repeat epitaxy of the strained Si layer 11.
  • this diffusion effect if it is appropriately controlled, may be sought after.
  • diffusion can be controlled in such a way that the Ge species are distributed uniformly in the assembly of the two layers 2 and 5, forming a single layer of Si- ⁇ . x Ge x having a substantially uniform Ge concentration.
  • steps with a view to making components may be integrated into or follow this method according to the invention.
  • preparation steps for the making of components may be implemented during the method, and at a temperature of about 900°C minimum without distorting the strain factor of the relaxed layer 2' and of the strained layer 11.
  • Local treatments may for example be undertaken intended to etch patterns in the layers, for example by lithography, by photolithography, by reactive ion etching or by any other etching with pattern masking.
  • patterns such as islets are thus etched into the strained SiGe layer 2 in order to contribute to the effective relaxation of the strained layer 2 when subsequently applying the thermal relaxation treatment.
  • One or more steps for making components, such as transistors, in the strained Si layer 11 (or in the relaxed SiGe layer 2' where the latter is not coated with a strained Si layer 11 ) may particularly be implemented at a temperature of about 900°C minimum without distorting the strain factor of the relaxed layer 2' and of the strained layer 11.
  • component- making steps are implemented during or in continuation of the thermal treatment to relax the strained SiGe layer 2.
  • the strained Si layer epitaxy step is implemented during or in continuation of the component making steps.
  • FIG 3 which represents a source wafer 10 before the formation of the embrittlement zone 6 and the formation of the vitreous layer 4
  • an embodiment of the invention is now presented, different from the various examples previously detailed referring to figure 1 a to 1 i and 2a to 2i by the way of choosing the materials constituting the donor substrate 1 and the strained layer 2.
  • the donor substrate 1 is composed of a holding substrate 1- 1 of Si and a buffer structure composed of a buffer layer 1-2 in SiGe and an upper layer 1-3 in Si ⁇ -z Ge z .
  • the holding substrate 1-1 is preferably in a bulk structure of single- crystal.
  • the buffer layer 1 -2 can for example be constituted of a stacking of layers so that the whole composition of Ge inside the buffer layer 1-2 gradually evoluates from 0% at the interface with the holding substrate 1-2 to 100z% of Ge at the interface with the upper layer 1-3 of Si ⁇ -z Ge z .
  • the upper layer 1-3 has a Ge composition constant in its thickness.
  • the upper layer 1-3 has a thickness sufficiently important to assign its lattice parameter to the overlied layer.
  • the upper layer 1-3 of Si-i -2 Ge z has a relaxed structure.
  • the buffer structure (composed of the buffer layer 1 -2 and the upper layer 1-3) allows: • an adaptation of the lattice parameter between the holding substrate 1-1 of Si and the nominal lattice parameter of Si- ⁇ -z Ge z of the upper layer 1-3;
  • the strained layer 2 is grown by epitaxy techniques, such as CVD techniques (PECVD, MOCVD).
  • a strained Si layer 2-1 is formed on the donor substrate 1 with a thickness no more than the critical thickness beyond which a such Si layer 2-1 starts to relax its elastic strains.
  • a Si ⁇ -x Ge x strained layer 2-2 is then formed on the last Si strained layer 2-1 , so as to have a thickness less than the critical thickness of Si- ⁇ _ x Ge x beyond which the elastic strains start to relax.
  • the strained layer 2 includes the Si strained layer 2-1 and the Si ⁇ -x Ge x layer 2-2, and that the donor substrate 1 comprises the holding substrate 1-1 , the buffer layer 1-2, and the upper layer 1-3 of Si ⁇ -z Ge z
  • the previous examples, (presented referring to the previous figures) of various embodiments of manufacturing a semiconductor-on-insulator structure 30 or 40 can then be easily transposed from the source wafer 10 of the figure 3, the embrittlement zone 6 being formed in the upper layer 1-3 or in the buffer layer 1-2.
  • etch agent as HF:H 2 O 2 :CH 3 COOH (selectivity about 1 :1000 between SiGe and Si).
  • the semiconductor-on-insulator structure finally obtained (not shown) comprises successively a receiving substrate 7, a vitreous layer 4, the S - ⁇ Ge x strained layer 2-2 and the Si strained layer 2-1. Then, a thermal treatment with a temperature close to or greater than the viscosity temperature of the vitreous layer 4 previously formed, is processed.
  • This thermal treatment then relaxes at least partly the Si ⁇ -x Ge x layer 2-2.
  • the relaxed Si ⁇ -x Ge x layer 2-2 imposes then elastic constraint to the top Si strained layer 2-1.
  • Elastic constraints in the Si strained layer 2-1 are then increased by the fact that x- composition of Ge is more important than z-composition.
  • this semiconductor-on-insulator structure is not obtained from a source wafer comprising a buffer structure adapting the parameter to a S -x Ge x , but from a buffer structure adapting the parameter to a Si ⁇ -z Ge z with z ⁇ x.
  • a buffer structure which adapts a lattice parameter to a Si ⁇ _ x Ge x is thicker, comprises more stacking layers, and so is longer and more expansive to manufacture, than a buffer structure which adapts a lattice parameter to a Si ⁇ -z Ge z .
  • One or more epitaxies of whatever kind may be applied to the final structure (structure 30 or 40 referenced in figure 1h, 1i, 2h, 2i), such as an epitaxy of a SiGe or SiGeC layer, or an epitaxy of a strained Si or SiC layer, or successive epitaxies of SiGe or SiGeC layers and Si or strained SiC layers alternately so as to form a multilayer structure.
  • finish treatments comprising for example annealing, may possibly be applied.
  • the present invention restricted to a strained SiGe layer 2, but extends also to a constitution of the strained layer 2 in other types of materials, of the lll-V or ll-VI type, or to other semiconductor materials.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention porte sur un procédé de formation d'une couche exempte de tensions ou d'une couche pseudo-détendue sur un substrat, la couche exempte de tensions étant faite d'un matériau choisi parmi des matériaux semiconducteurs. L'invention comprend les étapes suivantes : a) croissance sur un substrat donneur (1) d'une couche à contrainte élastique (2) constituée d'au moins un matériau choisi parmi les matériaux semiconducteurs ; b) formation sur la couche contrainte (2), ou sur un substrat receveur (7) d'une couche vitreuse (4) faite d'un matériau dont la viscosité se manifeste à une température de viscosité supérieure à environ 900 °C ; c) liaison du substrat receveur (7) à la couche contrainte (2) au moyen de la couche vitreuse (4) réalisée à l'étape b) ; d) extraction du substrat donneur (1) de manière à pouvoir obtenir une structure (20) comprenant le substrat receveur, la couche vitreuse (4) et couche contrainte (2) ; e) application d'un traitement thermique à ladite structure à une température proche ou supérieure à la température de viscosité, de manière à détendre au moins une partie des contraintes exercées dans la couche contrainte (2).
EP04715982A 2003-02-28 2004-03-01 Relaxation d'une couche mince a une temperature elevee apres son transfert Withdrawn EP1597759A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0302519A FR2851848B1 (fr) 2003-02-28 2003-02-28 Relaxation a haute temperature d'une couche mince apres transfert
FR0302519 2003-02-28
PCT/IB2004/000931 WO2004077553A1 (fr) 2003-02-28 2004-03-01 Relaxation d'une couche mince a une temperature elevee apres son transfert

Publications (1)

Publication Number Publication Date
EP1597759A1 true EP1597759A1 (fr) 2005-11-23

Family

ID=32843092

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04715982A Withdrawn EP1597759A1 (fr) 2003-02-28 2004-03-01 Relaxation d'une couche mince a une temperature elevee apres son transfert

Country Status (4)

Country Link
EP (1) EP1597759A1 (fr)
JP (1) JP2006519489A (fr)
FR (1) FR2851848B1 (fr)
WO (1) WO2004077553A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
JP2006140187A (ja) * 2004-11-10 2006-06-01 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
EP1858071A1 (fr) * 2006-05-18 2007-11-21 S.O.I.TEC. Silicon on Insulator Technologies S.A. Procédé de fabrication d'une plaquette de type semi-conducteur sur isolant, et plaquette de type semi-conducteur sur isolant
FR2936903B1 (fr) * 2008-10-07 2011-01-14 Soitec Silicon On Insulator Relaxation d'une couche de materiau contraint avec application d'un raidisseur
CN102203904B (zh) 2008-10-30 2013-11-20 S.O.I.探测硅绝缘技术公司 形成具有减小的晶格应变的半导体材料层、半导体结构、装置的方法及包含具有减小的晶格应变的半导体材料层、半导体结构、装置的工程衬底
US8637383B2 (en) 2010-12-23 2014-01-28 Soitec Strain relaxation using metal materials and related structures
US8536022B2 (en) * 2010-05-19 2013-09-17 Koninklijke Philips N.V. Method of growing composite substrate using a relaxed strained layer
US8916450B2 (en) 2012-08-02 2014-12-23 International Business Machines Corporation Method for improving quality of spalled material layers

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US20020089032A1 (en) * 1999-08-23 2002-07-11 Feng-Yi Huang Processing method for forming dislocation-free silicon-on-insulator substrate prepared by implantation of oxygen
JP4226175B2 (ja) * 1999-12-10 2009-02-18 富士通株式会社 半導体装置およびその製造方法
KR100429869B1 (ko) * 2000-01-07 2004-05-03 삼성전자주식회사 매몰 실리콘 저머늄층을 갖는 ｃｍｏｓ 집적회로 소자 및기판과 그의 제조방법
JP2001284558A (ja) * 2000-03-31 2001-10-12 Fujitsu Ltd 積層半導体基板及びその製造方法並びに半導体装置
JP2004507084A (ja) * 2000-08-16 2004-03-04 マサチューセッツ　インスティテュート　オブ　テクノロジー グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
US6524935B1 (en) * 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
FR2818010B1 (fr) * 2000-12-08 2003-09-05 Commissariat Energie Atomique Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
JP3648466B2 (ja) * 2001-06-29 2005-05-18 株式会社東芝 電界効果トランジスタ、半導体基板、電界効果トランジスタの製造方法及び半導体基板の製造方法
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004077553A1 *

Also Published As

Publication number Publication date
FR2851848A1 (fr) 2004-09-03
JP2006519489A (ja) 2006-08-24
FR2851848B1 (fr) 2005-07-08
WO2004077553A1 (fr) 2004-09-10

Similar Documents

Publication Publication Date Title
US7348260B2 (en) Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US20040192067A1 (en) Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US7736988B2 (en) Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
JP4173884B2 (ja) ゲルマニウム・オン・インシュレータ（ＧｅＯＩ）型ウェーハの製造方法
US6573126B2 (en) Process for producing semiconductor article using graded epitaxial growth
US7018910B2 (en) Transfer of a thin layer from a wafer comprising a buffer layer
KR100829644B1 (ko) 스트레인된 반도체 재료층의 전달 방법
WO2004006311A2 (fr) Transfert d'une couche mince depuis une tranche comprenant une couche tampon
KR20050084568A (ko) 버퍼층이 없는 웨이퍼로부터 완화된 유용층을 형성하는방법
JP4654710B2 (ja) 半導体ウェーハの製造方法
WO2004077553A1 (fr) Relaxation d'une couche mince a une temperature elevee apres son transfert
JP4980049B2 (ja) 遷移後の薄層の緩和
US7452792B2 (en) Relaxation of layers
US20050023610A1 (en) Semiconductor-on-insulator structure having high-temperature elastic constraints
JP5032743B2 (ja) バッファ層を有しないウエハからの緩和された有用層の形成

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050803

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

RIN1 Information on inventor provided before grant (corrected)

Inventor name: ARENE, EMMANUEL

Inventor name: MAZURE, CARLOS

Inventor name: GHYSELEN, BRUNO

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20090623

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SOITEC

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20130625