EP1486846A1 - Switch in bipolar technology - Google Patents

Switch in bipolar technology Download PDF

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Publication number
EP1486846A1
EP1486846A1 EP04300320A EP04300320A EP1486846A1 EP 1486846 A1 EP1486846 A1 EP 1486846A1 EP 04300320 A EP04300320 A EP 04300320A EP 04300320 A EP04300320 A EP 04300320A EP 1486846 A1 EP1486846 A1 EP 1486846A1
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EP
European Patent Office
Prior art keywords
transistor
transistors
type
current
collector
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EP04300320A
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German (de)
French (fr)
Inventor
Joel Concord
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to an integrated switch realized by means of bipolar transistors.
  • Figure 1 shows a classic example of such so-called adaptive switch.
  • the main transistor 1 is a PNP transistor connected in series with a load Q, between an IN input terminal to which a voltage will be applied continuous supply Vcc and a terminal M representing the electrical ground of the circuit.
  • the emitter of transistor 1 is connected to the IN terminal constituting an input terminal of the switch and its collector defines an output OUT terminal, connected to the load Q whose other terminal is to ground M.
  • the rest of the assembly is made up of the adaptive control.
  • This circuit is based on the copying by a transistor 2 (here PNP type) of a fraction of the through current transistor 1.
  • the emitter of transistor 2 is connected to the IN terminal (therefore also at the emitter of transistor 1), and its base is connected to that of transistor 1.
  • the collector of transistor 2 is connected to a current, formed by two NPN 3 and 4 type transistors (defining the source transistor and the transistor respectively mirror copy) whose emitters are connected to ground and whose respective bases are interconnected to the collector of transistor 3 (and therefore to the collector of transistor 2).
  • the bases of transistors 1 and 2 are also connected to the output of the current mirror, on the collector of transistor 4.
  • a polarization resistor R connects the IN terminal to the bases of the transistors 3 and 4.
  • An NPN transistor 5 controlled by a signal ON / OFF activation of the two-state circuit, connects the collector from transistor 2 to ground. When transistor 5 conducts, the current from transistor 2 is flowing to ground and none current is then drawn from the base of transistor 1, which guaranteed its blocking.
  • a disadvantage of the structure of Figure 1 is that transistors 1 and 2 have, between their collectors and transmitters respective, different polarizations. Indeed, the transistor 1 operates in saturated mode with a collector-emitter voltage weak while transistor 2 (unsaturated) sees to its terminals a much higher collector-emitter voltage. This difference in collector-emitter voltage can induce a error of current copying between these two transistors and causing then a significant increase in the consumption of switch on load as at rest. This drawback is encountered especially in integrated technology where the low dimension of the components makes their parameters more sensitive at the polarization conditions.
  • the present invention aims to provide a switch in bipolar technology overcoming the disadvantages of known switches. More particularly, the invention aims to propose a switch in which the feedback report of current is independent of any collector-emitter voltage deviation between the transistors of the mirror.
  • the invention also aims to propose a solution particularly suitable for low consumption systems under integrated form.
  • the invention aims to propose a solution compatible with the addition of a function limiting the output current, among other things to protect the circuit against short circuits at the output or limit the maximum current in charge Q.
  • said current mirror circuit consists of a third second and fourth type bipolar transistor bipolar transistor of the second type connecting the base of the first transistor at a second voltage application terminal power supply, the bases of the third and fourth transistors being interconnected to the collector of the third transistor connecting the collector of the second transistor via of a fifth bipolar transistor of the first type belonging to the bias circuit.
  • the fourth transistor has an emitter surface greater than that of the third transistor.
  • the bias circuit further includes a sixth transistor of the second type connected between said output terminal by its emitter and a seventh bipolar transistor of the second type mounted in current mirror on said third and fourth transistors, the emitter surface of the seventh transistor preferably being identical to that of the third transistor.
  • a starting current source connects the base of the first transistor at the second voltage application terminal Power.
  • a starting assistance circuit injects a current on the collector of the second transistor, the start-up assistance circuit being preferably a resistor in series with an eighth transistor of the first type connected between the input terminal and said collector of the second transistor, the base of the eighth transistor being connected to the base of the first transistor of so as to inject an image current of the output current.
  • an internal current limiting circuit is provided, preferably a resistor inserted between the collectors fifth and third transistors, and a ninth transistor current diversion to ground.
  • the transistors of the first type are PNP transistors, the transistors of the second type being NPN transistors.
  • the transistors of the first type are transistors of the type NPN, the transistors of the second type being transistors of PNP type.
  • Figure 2 shows the electrical diagram of a switch according to an embodiment of the invention.
  • this switch includes a transistor main 1 (here PNP) between two terminals IN and OUT of circuit.
  • PNP transistor main 1
  • this PNP transistor will preferably be of an isolated type, i.e. a component bipolar for which the parasitic elements likely to conduct a leakage current in the substrate in saturation mode have been numbed (for example, a transistor in a insulated pocket).
  • the IN terminal is intended to receive a potential positive supply Vcc while the OUT terminal is intended to be connected to a load Q whose other terminal is connected at mass M (or at a more negative supply potential than the potential Vcc).
  • the collector of transistor 2 is not not directly connected to the collector of transistor 3 but is via a transistor 10, of the same type as transistors 1 and 2 (in the example, PNP), belonging to a transistor bias circuit 6 at the same voltage as transistor 1.
  • This circuit 6 also includes a transistor 11 PNP type mounted as a voltage follower and a transistor 12 NPN type mirror mounted on transistors 3 and 4, the transistors 11 and 12 being in series between the OUT terminal and the mass. More specifically, the emitter of transistor 11 is connected to the OUT terminal and its collector is connected to the collector of transistor 12 whose emitter is grounded. The basis of transistor 11 is connected to its collector and to the base of the transistor 10 whose emitter is connected to the collector of the transistor 2 and whose collector is connected to the collector of the transistor 3. Finally, the base of transistor 12 is connected to bases of transistors 3 and 4.
  • Transistors 10 and 11 are dimensioned so that the ratio of their emitter areas is equal to ratio of the currents crossing them, i.e. as a function of size ratio between transistors 3 and 12. Thus, their base-emitter voltages are equal. It follows that the collector-emitter voltages of transistors 1 and 2 are returned identical. The transistor 2 is now polarized the same so that transistor 1, the feedback ratio is no longer impacted by a difference in collector-emitter voltage of these two transistors and therefore remains constant and equal to 1 / (N-1), where N represents the ratio of the emitter surfaces of the transistors 1 and 2.
  • Transistors 3 and 4 also have surfaces of different emitters, transistor 4 having a surface emitter larger than transistor 3, the ratio of surface of transistor 4 over that of transistor 3 is designated thereafter by M.
  • the transistor 12 preferably has the same size as transistor 3.
  • a current source 7 connects the base of the transistor 1 to ground so as to draw current on this base when the engine starts.
  • the easiest way to make this source of current is a resistor.
  • this resistance is sized to draw a prepolarization current from the transistor 1 on the order of a few microamps.
  • the current source 7 is produced by a transistor assembly.
  • the current supplied by transistor 1 to the load following its prepolarization is amplified by the positive feedback loop internal to the structure, up to the quiescent value corresponding to the output voltage V out divided by l load impedance Q.
  • circuit 6 induces a response time of the switch when the load Q varies greatly.
  • the internal currents are extremely weak or even zero and the transistor 10 is almost non-conductive. Therefore, the current in transistor 1 remains limited to the product of current supplied by source 7 multiplied by the gain of transistor 1 for a more or less long period, necessary for the current of leak to cause priming of the structure and allow the switch to supply current to the load.
  • this reaction time is reduced by injecting a weak current, image of the output current, directly on the collector of the transistor 3.
  • a circuit 8 is therefore provided for injecting current consisting of a resistor R8 in series with a transistor PNP 13 between the IN terminal and the collector of the transistor 3.
  • the base of transistor 13 is connected to the base of transistor 2.
  • the presence of this circuit 8 does not generate consumption problem despite transistor 13 having a collector-emitter voltage different from that of transistor 1.
  • the resistance R8 which is preferably of value high (from a few kiloohms to a few tens of kiloohms) induces a current limitation in transistor 13 making negligible the current supplied by it compared to the current in transistor 2 in normal operation.
  • the internal current consumed by the switch is then equal to I OUT * (M + 2) / (NM) and the efficiency of the switch is equal to (NM) / (N + 2).
  • An advantage of the switch of the invention is that it allows saturation of the main transistor 1 whatever either the conditions (temperature, characteristics of the component, output load).
  • Another advantage of the invention is that consumption of the switch is proportional to the output current and that it generates a weak quiescent current, which makes the structure compatible with low consumption applications.
  • Another advantage of the invention is that the structure is compatible with low voltage applications (up to about 1.5 V) due to the low number of base-emitter voltages between power lines.
  • Another advantage of this switch is that it is can be integrated on a chip in bipolar technology.
  • Figure 3 shows another embodiment of the switch of the invention, equipped with a limitation circuit 9 of internal current.
  • the structure of Figure 3 shows the same elements as those shown in Figure 2.
  • a current limiting resistor R9 is interposed between the collector of transistor 10 and that of transistor 3.
  • This resistor is associated with a PNP type transistor 14 whose emitter is connected to the collector of transistor 10 and the base of which is connected to the collector of transistor 3, the collector of transistor 14 being connected to ground.
  • Circuit 9 limits the output current of the switch to a value I LIM approximately equal to (N / R9) * VBe14, where Vbe14 represents the base-emitter voltage of transistor 14.
  • transistor 14 becomes progressively conductive and part of the current from transistor 10 drifts to ground as soon as the output current reaches approximately the above limit value. Consequently, the output current I OUT of the device is regulated approximately to the value I LIM .
  • transistor 15 of NPN type connecting the terminal IN (by its collector) to the collector of transistor 11 (by its emitter) and whose base is connected to the collector of transistor 10.
  • transistor 10 When transistor 10 begins to saturate under the effect of an increase in its base current, the voltage collector-emitter of transistor 10 decreases and causes the increase in the base-emitter voltage of transistor 15 hence its conduction which therefore allows transistor 12 to draw its collector current not through the base of transistor 10 but by transistor 9, with no significant impact on the limitation of current.
  • Figure 3 also illustrates a variant consisting to replace the short circuit of the base and the collector of the transistor 11 as shown in figure 2 by a resistor R11.
  • the presence of the resistance R11 allows to advance the instant at the start of conduction of transistor 15 without it being necessary to wait for too much saturation of the transistor 10.
  • FIG. 4 illustrates an alternative embodiment of a circuit 9 'for current limitation.
  • this variant consists in removing circuit 9 (therefore directly connecting the collector of transistor 10 to the collector of transistor 3) and to connect a device 9 'upstream of the terminal IN. More precisely, a shunt resistor Rs is inserted between the terminal for applying the potential Vcc and the terminal IN.
  • Two PNP type transistors 16 and 17 are mirrored around the resistor Rs, the emitter of transistor 16 being connected to terminal Vcc while the emitter of transistor 17 is connected to the IN terminal, the respective collectors of the transistors 16 and 17 being connected to two current sources 19 and 20 of the same value, preferably produced by mounting current mirror type transistors, and their base being interconnected to the collector of transistor 17.
  • the collector of transistor 16 is connected to the base of a NPN 18 transistor whose collector is connected to the IN terminal and whose emitter is connected to the collector of transistor 4. The rest of the circuit of figure 3 has not been represented in figure 4.
  • the limiting current of circuit 9 ' is fixed by the emitter area ratio of transistors 16 and 17. In setting this ratio equal to P, the limiting current is the order of Vt * log (P) / Rs, where Vt denotes the thermal potential (approximately 26 mV at 27 ° C).
  • the structure proposed by the invention is dual, that is to say that it can be applied to a negative voltage Vcc by replacing all the PNP transistors by NPN transistors and all NPN transistors by PNP transistors.
  • protection circuit 8 against short-circuits, of circuit 9 for limiting the current, or the load shedding transistor 15 remains optional in depending on the application.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)

Abstract

The switch has a transistor (1) connected between input and output terminals of a circuit. The input terminal receives a positive supply voltage, while the output terminal is connected to a load (Q). A transistor (2) is connected between the input terminal and an input of a current mirror circuit thorough a bias circuit (6) that acts as an output voltage follower of the switch on a collector of the transistor (2).

Description

La présente invention concerne un commutateur intégré réalisé au moyen de transistors bipolaires.The present invention relates to an integrated switch realized by means of bipolar transistors.

Le plus simple pour réaliser un commutateur en technologie bipolaire est d'utiliser un transistor en régime saturé, la chute de tension à ses bornes (collecteur-émetteur) étant ainsi minimale. On peut alors transférer le maximum de puissance possible vers une charge à alimenter, connectée en série avec ce transistor bipolaire. Pour placer un transistor en régime de saturation, il faut lui imposer un certain courant de base de telle sorte que le gain (rapport du courant de collecteur sur le courant de base) soit forcé à une valeur inférieure au gain minimum de ce transistor en régime linéaire.The easiest way to make a switch in technology bipolar is to use a transistor in saturated mode, the voltage drop across its terminals (collector-emitter) being thus minimal. We can then transfer the maximum power possible to a load to be supplied, connected in series with this bipolar transistor. To place a transistor in regime of saturation, you have to impose a certain basic current of such that the gain (ratio of the collector current to the base current) is forced to a value lower than the gain minimum of this transistor in linear regime.

Une difficulté réside dans le fait qu'en fixant un courant de base déterminé, la consommation intrinsèque au commutateur (liée à son courant de base) reste constante, même pour une charge variable. Cela rend notamment ce type de montage inadapté à des applications à faible consommation.One difficulty is that by setting a determined base current, the intrinsic consumption at switch (linked to its base current) remains constant even for a variable load. This makes this type of assembly in particular unsuitable for low consumption applications.

Pour pallier cet inconvénient, on a déjà proposé des commutateurs en technologie bipolaire permettant de réguler le courant de base du transistor principal en fonction du courant appelé par la charge. To overcome this drawback, we have already proposed switches in bipolar technology to regulate the base current of the main transistor as a function of the current called by the charge.

La figure 1 représente un exemple classique d'un tel commutateur dit adaptatif.Figure 1 shows a classic example of such so-called adaptive switch.

Dans l'exemple représenté, le transistor principal 1 est un transistor PNP connecté, en série avec une charge Q, entre une borne d'entrée IN sur laquelle sera appliquée une tension d'alimentation continue Vcc et une borne M représentant la masse électrique du circuit. L'émetteur du transistor 1 est connecté à la borne IN constituant une borne d'entrée du commutateur et son collecteur définit une borne OUT de sortie, connecté à la charge Q dont l'autre borne est à la masse M.In the example shown, the main transistor 1 is a PNP transistor connected in series with a load Q, between an IN input terminal to which a voltage will be applied continuous supply Vcc and a terminal M representing the electrical ground of the circuit. The emitter of transistor 1 is connected to the IN terminal constituting an input terminal of the switch and its collector defines an output OUT terminal, connected to the load Q whose other terminal is to ground M.

Le reste du montage est constitué par le circuit de commande adaptative. Ce circuit est basé sur la recopie par un transistor 2 (ici de type PNP) d'une fraction du courant traversant le transistor 1. L'émetteur du transistor 2 est connecté à la borne IN (donc aussi à l'émetteur du transistor 1), et sa base est reliée à celle du transistor 1.The rest of the assembly is made up of the adaptive control. This circuit is based on the copying by a transistor 2 (here PNP type) of a fraction of the through current transistor 1. The emitter of transistor 2 is connected to the IN terminal (therefore also at the emitter of transistor 1), and its base is connected to that of transistor 1.

Le collecteur du transistor 2 est relié à un miroir de courant, formé de deux transistors de type NPN 3 et 4 (définissant respectivement le transistor source et le transistor de recopie du miroir) dont les émetteurs sont connectés à la masse et dont les bases respectives sont interconnectées au collecteur du transistor 3 (et donc au collecteur du transistor 2). Les bases des transistors 1 et 2 sont par ailleurs connectées à la sortie du miroir de courant, sur le collecteur du transistor 4. Une résistance de polarisation R relie la borne IN aux bases des transistors 3 et 4.The collector of transistor 2 is connected to a current, formed by two NPN 3 and 4 type transistors (defining the source transistor and the transistor respectively mirror copy) whose emitters are connected to ground and whose respective bases are interconnected to the collector of transistor 3 (and therefore to the collector of transistor 2). The bases of transistors 1 and 2 are also connected to the output of the current mirror, on the collector of transistor 4. A polarization resistor R connects the IN terminal to the bases of the transistors 3 and 4.

Le courant tiré de la base du transistor 1 par le miroir de courant 3-4 est Ib=Ic/(N-1) - où N représente le rapport de surfaces d'émetteurs entre les transistors 1 et 2 - et impose au transistor 1 un régime de saturation avec un gain forcé égal à βf=Ic/Ib=N-1. Ainsi, si N est choisi tel que le gain βf soit inférieur au gain minimum du transistor 1 en régime linéaire, on assure la saturation de ce transistor et le fonctionnement du montage en commutateur. The current drawn from the base of transistor 1 by the current mirror 3-4 is Ib = Ic / (N-1) - where N represents the emitter area ratio between transistors 1 and 2 - and imposes on the transistor 1 a saturation regime with a gain forced equal to βf = Ic / Ib = N-1. So, if N is chosen such that the gain βf is less than the minimum gain of transistor 1 in regime linear, we ensure the saturation of this transistor and the functioning switch mounting.

Un transistor 5 de type NPN, commandé par un signal ON/OFF d'activation du circuit à deux états, relie le collecteur du transistor 2 à la masse. Quand le transistor 5 conduit, le courant issu du transistor 2 est écoulé vers la masse et aucun courant n'est alors tiré de la base du transistor 1, ce qui garanti son blocage.An NPN transistor 5, controlled by a signal ON / OFF activation of the two-state circuit, connects the collector from transistor 2 to ground. When transistor 5 conducts, the current from transistor 2 is flowing to ground and none current is then drawn from the base of transistor 1, which guaranteed its blocking.

Un inconvénient de la structure de la figure 1 est que les transistors 1 et 2 ont, entre leur collecteurs et émetteurs respectifs, des polarisations différentes. En effet, le transistor 1 fonctionne en régime saturé avec une tension collecteur-émetteur faible tandis que le transistor 2 (non saturé) voit à ses bornes une tension collecteur-émetteur nettement supérieure. Cette différence de tension collecteur-émetteur peut induire une erreur de recopie de courant entre ces deux transistors et provoquer alors une augmentation importante de la consommation du commutateur en charge comme au repos. Cet inconvénient se rencontre plus particulièrement en technologie intégrée où la faible dimension des composants rend leurs paramètres plus sensibles aux conditions de polarisation.A disadvantage of the structure of Figure 1 is that transistors 1 and 2 have, between their collectors and transmitters respective, different polarizations. Indeed, the transistor 1 operates in saturated mode with a collector-emitter voltage weak while transistor 2 (unsaturated) sees to its terminals a much higher collector-emitter voltage. This difference in collector-emitter voltage can induce a error of current copying between these two transistors and causing then a significant increase in the consumption of switch on load as at rest. This drawback is encountered especially in integrated technology where the low dimension of the components makes their parameters more sensitive at the polarization conditions.

En pratique, ce phénomène de surconsommation lié à la différence de conditions de polarisation tend à s'accentuer avec l'augmentation de la température de fonctionnement du composant.In practice, this phenomenon of overconsumption linked to difference in polarization conditions tends to increase with increasing the operating temperature of the component.

La présente invention vise à proposer un commutateur en technologie bipolaire s'affranchissant des inconvénients des commutateurs connus. Plus particulièrement, l'invention vise à proposer un commutateur dans lequel le rapport de recopie de courant est indépendant d'un écart éventuel de tension collecteur-émetteur entre les transistors du miroir.The present invention aims to provide a switch in bipolar technology overcoming the disadvantages of known switches. More particularly, the invention aims to propose a switch in which the feedback report of current is independent of any collector-emitter voltage deviation between the transistors of the mirror.

L'invention vise également à proposer une solution particulièrement adaptée à des systèmes basse consommation sous forme intégrée.The invention also aims to propose a solution particularly suitable for low consumption systems under integrated form.

A cet égard, l'invention vise à proposer une solution compatible avec l'adjonction d'une fonction de limitation du courant de sortie, pour entre autres, protéger le circuit contre les courts-circuits en sortie ou limiter le courant maximum dans la charge Q.In this regard, the invention aims to propose a solution compatible with the addition of a function limiting the output current, among other things to protect the circuit against short circuits at the output or limit the maximum current in charge Q.

Pour atteindre ces objets et d'autres, l'invention prévoit un commutateur en technologie bipolaire comprenant :

  • un premier transistor principal d'un premier type reliant une borne d'entrée, destinée à être connectée à une première borne d'application d'une tension d'alimentation continue, à une borne de sortie destinée à être connectée à une charge à alimenter ;
  • un deuxième transistor bipolaire de même type que le premier, connecté entre ladite borne d'entrée et une entrée d'un circuit miroir de courant dont une sortie de recopie est connectée à la base du premier transistor, les bases des premier et deuxième transistors étant interconnectées et le premier transistor ayant une surface d'émetteur supérieure au second ; et
  • un circuit de polarisation du deuxième transistor consistant en la recopie de la tension de sortie du commutateur sur le collecteur de ce deuxième transistor.
    • To achieve these and other objects, the invention provides a switch in bipolar technology comprising:
  • a first main transistor of a first type connecting an input terminal, intended to be connected to a first terminal for applying a DC supply voltage, to an output terminal intended to be connected to a load to be supplied ;
  • a second bipolar transistor of the same type as the first, connected between said input terminal and an input of a current mirror circuit of which a feedback output is connected to the base of the first transistor, the bases of the first and second transistors being interconnected and the first transistor having an emitter surface greater than the second; and
  • a bias circuit of the second transistor consisting of the copying of the output voltage of the switch on the collector of this second transistor.

    • Selon un mode de réalisation de la présente invention, ledit circuit miroir de courant est constitué d'un troisième transistor bipolaire d'un deuxième type et d'un quatrième transistor bipolaire du deuxième type reliant la base du premier transistor à une deuxième borne d'application de la tension d'alimentation, les bases des troisième et quatrième transistors étant interconnectées au collecteur du troisième transistor reliant le collecteur du deuxième transistor par l'intermédiaire d'un cinquième transistor bipolaire du premier type appartenant au circuit de polarisation.According to an embodiment of the present invention, said current mirror circuit consists of a third second and fourth type bipolar transistor bipolar transistor of the second type connecting the base of the first transistor at a second voltage application terminal power supply, the bases of the third and fourth transistors being interconnected to the collector of the third transistor connecting the collector of the second transistor via of a fifth bipolar transistor of the first type belonging to the bias circuit.

    Selon un mode de réalisation de la présente invention, le quatrième transistor a une surface d'émetteur supérieure à celle du troisième transistor.According to an embodiment of the present invention, the fourth transistor has an emitter surface greater than that of the third transistor.

    Selon un mode de réalisation de la présente invention, le circuit de polarisation comporte en outre un sixième transistor du deuxième type connecté entre ladite borne de sortie par son émetteur et un septième transistor bipolaire du deuxième type monté en miroir de courant sur lesdits troisième et quatrième transistors, la surface d'émetteur du septième transistor étant, de préférence, identique à celle du troisième transistor.According to an embodiment of the present invention, the bias circuit further includes a sixth transistor of the second type connected between said output terminal by its emitter and a seventh bipolar transistor of the second type mounted in current mirror on said third and fourth transistors, the emitter surface of the seventh transistor preferably being identical to that of the third transistor.

    Selon un mode de réalisation de la présente invention, une source de courant de démarrage relie la base du premier transistor à la deuxième borne d'application de la tension d'alimentation.According to an embodiment of the present invention, a starting current source connects the base of the first transistor at the second voltage application terminal Power.

    Selon un mode de réalisation de la présente invention, un circuit d'aide au démarrage injecte un courant sur le collecteur du deuxième transistor, le circuit d'aide au démarrage étant de préférence constitué d'une résistance en série avec un huitième transistor du premier type connecté entre la borne d'entrée et ledit collecteur du deuxième transistor, la base du huitième transistor étant connectée à la base du premier transistor de façon à injecter un courant image du courant de sortie.According to an embodiment of the present invention, a starting assistance circuit injects a current on the collector of the second transistor, the start-up assistance circuit being preferably a resistor in series with an eighth transistor of the first type connected between the input terminal and said collector of the second transistor, the base of the eighth transistor being connected to the base of the first transistor of so as to inject an image current of the output current.

    Selon un mode de réalisation de la présente invention, on prévoit un circuit de limitation du courant interne constitué, de préférence, d'une résistance intercalée entre les collecteurs des cinquième et troisième transistors, et d'un neuvième transistor de dérivation du courant vers la masse.According to an embodiment of the present invention, an internal current limiting circuit is provided, preferably a resistor inserted between the collectors fifth and third transistors, and a ninth transistor current diversion to ground.

    Selon un mode de réalisation de la présente invention, les transistors du premier type sont des transistors PNP, les transistors du second type étant des transistors NPN.According to an embodiment of the present invention, the transistors of the first type are PNP transistors, the transistors of the second type being NPN transistors.

    Selon un mode de réalisation de la présente invention, les transistors du premier type sont des transistors de type NPN, les transistors du second type étant des transistors de type PNP.According to an embodiment of the present invention, the transistors of the first type are transistors of the type NPN, the transistors of the second type being transistors of PNP type.

    Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non limitatif en relation avec les figures jointes parmi lesquelles :

  • la figure 1, décrite précédemment, est destinée à exposer l'état de la technique et le problème posé ;
  • la figure 2 représente un premier mode de réalisation d'un commutateur selon la présente invention ;
  • la figure 3 représente un deuxième mode de réalisation d'un commutateur selon l'invention, équipé d'un circuit de limitation du courant interne ; et
  • la figure 4 illustre une variante de réalisation d'un circuit de limitation du courant interne.
    • These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
  • Figure 1, described above, is intended to set out the state of the art and the problem posed;
  • FIG. 2 represents a first embodiment of a switch according to the present invention;
  • FIG. 3 represents a second embodiment of a switch according to the invention, equipped with a circuit for limiting the internal current; and
  • FIG. 4 illustrates an alternative embodiment of a circuit for limiting the internal current.

    • Les mêmes éléments ont été désignés par les mêmes références aux différentes figures. Pour des raisons de clarté, seuls les constituants du circuit qui sont nécessaires à la compréhension de l'invention ont été représentés aux figures et seront décrits par la suite. En particulier, le commutateur selon l'invention peut se voir adjoindre d'autres composants afin d'assurer d'autres fonctions.The same elements have been designated by the same references to the various figures. For reasons of clarity, only the components of the circuit which are necessary for the understanding of the invention have been shown in the figures and will be described later. In particular, the switch according to the invention can be added other components to perform other functions.

    La figure 2 représente le schéma électrique d'un commutateur selon un mode de réalisation de l'invention.Figure 2 shows the electrical diagram of a switch according to an embodiment of the invention.

    Comme précédemment, ce commutateur comporte un transistor principal 1 (ici PNP) entre deux bornes IN et OUT du circuit. En technologie intégrée, ce transistor PNP sera préférentiellement d'un type isolé, c'est-à-dire un composant bipolaire pour lequel les éléments parasites susceptibles de conduire en mode saturation un courant de fuite dans le substrat auront été insensibilisés (par exemple, un transistor dans une poche isolée). La borne IN est destinée à recevoir un potentiel d'alimentation positif Vcc tandis que la borne OUT est destinée à être connectée à une charge Q dont l'autre borne est connectée à la masse M (ou à un potentiel plus négatif d'alimentation que le potentiel Vcc).As before, this switch includes a transistor main 1 (here PNP) between two terminals IN and OUT of circuit. In integrated technology, this PNP transistor will preferably be of an isolated type, i.e. a component bipolar for which the parasitic elements likely to conduct a leakage current in the substrate in saturation mode have been numbed (for example, a transistor in a insulated pocket). The IN terminal is intended to receive a potential positive supply Vcc while the OUT terminal is intended to be connected to a load Q whose other terminal is connected at mass M (or at a more negative supply potential than the potential Vcc).

    Toujours de façon similaire aux circuits connus, on prévoit un montage en miroir de courant par recopie du courant de base du transistor 1. On retrouve donc un transistor 2 de même type que le transistor 1 dont l'émetteur est connecté à la borne IN, dont la base est connectée à la base du transistor 1, ainsi que deux transistors 3 et 4 de type NPN dont les bases sont interconnectées au collecteur du transistor 3 et dont les émetteurs sont connectés à la masse, le collecteur du transistor 4 étant connecté par ailleurs à la base du transistor 1. Un transistor d'allumage-extinction 5 recevant sur sa base un signal ON/OFF a son collecteur relié au collecteur du transistor 3 et son émetteur à la masse.Still similar to the known circuits, we provides for current mirror mounting by current copying base of transistor 1. So we find a transistor 2 of same type as transistor 1 whose emitter is connected to the IN terminal, the base of which is connected to the base of transistor 1, as well as two NPN type transistors 3 and 4 whose bases are interconnected to the collector of transistor 3 and whose emitters are connected to ground, the collector of the transistor 4 being also connected to the base of transistor 1. A ignition-extinction transistor 5 receiving on its base a ON / OFF signal has its collector connected to the transistor collector 3 and its grounded transmitter.

    Selon l'invention, le collecteur du transistor 2 n'est pas connecté directement au collecteur du transistor 3 mais l'est par l'intermédiaire d'un transistor 10, de même type que les transistors 1 et 2 (dans l'exemple, PNP), appartenant à un circuit 6 de polarisation du transistor 2 à la même tension que le transistor 1. Ce circuit 6 comporte également un transistor 11 de type PNP monté en suiveur de tension et un transistor 12 de type NPN monté en miroir sur les transistors 3 et 4, les transistors 11 et 12 étant en série entre la borne OUT et la masse. Plus précisément, l'émetteur du transistor 11 est connecté à la borne OUT et son collecteur est relié au collecteur du transistor 12 dont l'émetteur est à la masse. La base du transistor 11 est reliée à son collecteur et à la base du transistor 10 dont l'émetteur est connecté au collecteur du transistor 2 et dont le collecteur est connecté au collecteur du transistor 3. Enfin, la base du transistor 12 est reliée aux bases des transistors 3 et 4.According to the invention, the collector of transistor 2 is not not directly connected to the collector of transistor 3 but is via a transistor 10, of the same type as transistors 1 and 2 (in the example, PNP), belonging to a transistor bias circuit 6 at the same voltage as transistor 1. This circuit 6 also includes a transistor 11 PNP type mounted as a voltage follower and a transistor 12 NPN type mirror mounted on transistors 3 and 4, the transistors 11 and 12 being in series between the OUT terminal and the mass. More specifically, the emitter of transistor 11 is connected to the OUT terminal and its collector is connected to the collector of transistor 12 whose emitter is grounded. The basis of transistor 11 is connected to its collector and to the base of the transistor 10 whose emitter is connected to the collector of the transistor 2 and whose collector is connected to the collector of the transistor 3. Finally, the base of transistor 12 is connected to bases of transistors 3 and 4.

    Les transistors 10 et 11 sont dimensionnés de sorte que le rapport de leurs surfaces d'émetteurs soit égal au rapport des courants les traversant, c'est-à-dire en fonction du rapport de taille entre les transistors 3 et 12. Ainsi, leurs tensions base-émetteur sont égales. Il en découle que les tensions collecteur-émetteur des transistors 1 et 2 sont rendues identiques. Le transistor 2 étant désormais polarisé de la même façon que le transistor 1, le rapport de recopie n'est plus impacté par une différence de tension collecteur-émetteur de ces deux transistors et reste donc constant et égal à 1/(N-1), où N représente le rapport des surfaces d'émetteurs des transistors 1 et 2. Transistors 10 and 11 are dimensioned so that the ratio of their emitter areas is equal to ratio of the currents crossing them, i.e. as a function of size ratio between transistors 3 and 12. Thus, their base-emitter voltages are equal. It follows that the collector-emitter voltages of transistors 1 and 2 are returned identical. The transistor 2 is now polarized the same so that transistor 1, the feedback ratio is no longer impacted by a difference in collector-emitter voltage of these two transistors and therefore remains constant and equal to 1 / (N-1), where N represents the ratio of the emitter surfaces of the transistors 1 and 2.

    Les transistors 3 et 4 ont également des surfaces d'émetteur différentes, le transistor 4 ayant une surface d'émetteur plus grande que le transistor 3, le rapport de surface du transistor 4 sur celle du transistor 3 est désigné par la suite par M. Par contre, le transistor 12 a, de préférence, la même taille que le transistor 3.Transistors 3 and 4 also have surfaces of different emitters, transistor 4 having a surface emitter larger than transistor 3, the ratio of surface of transistor 4 over that of transistor 3 is designated thereafter by M. On the other hand, the transistor 12 preferably has the same size as transistor 3.

    Pour permettre le démarrage du circuit lors de la mise sous tension, une source de courant 7 relie la base du transistor 1 à la masse de façon à tirer du courant sur cette base au démarrage. La façon la plus simple de réaliser cette source de courant est une résistance. De préférence, cette résistance est dimensionnée pour tirer un courant de prépolarisation du transistor 1 de l'ordre de quelques microampères. En variante, la source de courant 7 est réalisée par un montage à transistors.To allow the circuit to start up when switching on under voltage, a current source 7 connects the base of the transistor 1 to ground so as to draw current on this base when the engine starts. The easiest way to make this source of current is a resistor. Preferably, this resistance is sized to draw a prepolarization current from the transistor 1 on the order of a few microamps. Alternatively, the current source 7 is produced by a transistor assembly.

    Dès le démarrage effectué, le courant que fournit le transistor 1 à la charge suite à sa prépolarisation est amplifié par la boucle de réaction positive interne à la structure, jusqu'à la valeur de repos correspondant à la tension de sortie Vout divisée par l'impédance de la charge Q.As soon as it starts up, the current supplied by transistor 1 to the load following its prepolarization is amplified by the positive feedback loop internal to the structure, up to the quiescent value corresponding to the output voltage V out divided by l load impedance Q.

    La présence du circuit 6 induit un temps de réponse du commutateur lorsque la charge Q varie fortement. En effet, quand le commutateur est actif et en l'absence de charge en sortie, les courants internes sont extrêmement faibles voire nuls et le transistor 10 est quasiment non conducteur. Par conséquent, le courant dans le transistor 1 reste limité au produit du courant fourni par la source 7 multiplié par le gain du transistor 1 pendant un délai plus ou moins long, nécessaire au courant de fuite pour provoquer l'amorçage de la structure et permettre au commutateur de fournir le courant à la charge.The presence of circuit 6 induces a response time of the switch when the load Q varies greatly. When the switch is active and in the absence of output load, the internal currents are extremely weak or even zero and the transistor 10 is almost non-conductive. Therefore, the current in transistor 1 remains limited to the product of current supplied by source 7 multiplied by the gain of transistor 1 for a more or less long period, necessary for the current of leak to cause priming of the structure and allow the switch to supply current to the load.

    Selon un mode de réalisation préféré de l'invention, on diminue ce temps de réaction en injectant un faible courant, image du courant de sortie, directement sur le collecteur du transistor 3. On prévoit donc un circuit 8 d'injection de courant constitué d'une résistance R8 en série avec un transistor de type PNP 13 entre la borne IN et le collecteur du transistor 3. La base du transistor 13 est connectée à la base du transistor 2. La présence de ce circuit 8 n'engendre pas de problème de consommation malgré que le transistor 13 ait une tension collecteur-émetteur différente de celle du transistor 1. En effet, la résistance R8 qui est de préférence de valeur élevée (de quelques kiloohms à quelques dizaines de kiloohms) induit une limitation du courant dans le transistor 13 rendant négligeable le courant fourni par celui-ci par rapport au courant dans le transistor 2 en fonctionnement normal.According to a preferred embodiment of the invention, this reaction time is reduced by injecting a weak current, image of the output current, directly on the collector of the transistor 3. A circuit 8 is therefore provided for injecting current consisting of a resistor R8 in series with a transistor PNP 13 between the IN terminal and the collector of the transistor 3. The base of transistor 13 is connected to the base of transistor 2. The presence of this circuit 8 does not generate consumption problem despite transistor 13 having a collector-emitter voltage different from that of transistor 1. Indeed, the resistance R8 which is preferably of value high (from a few kiloohms to a few tens of kiloohms) induces a current limitation in transistor 13 making negligible the current supplied by it compared to the current in transistor 2 in normal operation.

    En prenant l'exemple d'un rapport de dimension (de surfaces d'émetteurs) entre les transistors 4 et 3 de M (le transistor 12 étant de même taille que le transistor 3), la condition de saturation du transistor 1 devient : βf = (N-M)/M où βf désigne le gain forcé du transistor 1 qui doit être inférieur à son gain minimal en régime linéaire.By taking the example of a dimension ratio (of emitter surfaces) between transistors 4 and 3 of M (transistor 12 being the same size as transistor 3), the saturation condition of transistor 1 becomes: β f = (NM) / M where β f denotes the forced gain of transistor 1 which must be less than its minimum gain in linear regime.

    Avec ces notations, le rapport entre les courants d'entrée et de sortie suit la relation suivante : IIN = IOUT*(1+(M+2)/(N-M)). With these notations, the relationship between the input and output currents follows the following relationship: I IN = I OUT * (1+ (M + 2) / (NM)).

    Le courant interne consommé par le commutateur est alors égal à IOUT*(M+2)/(N-M) et le rendement du commutateur est égal à (N-M)/(N+2).The internal current consumed by the switch is then equal to I OUT * (M + 2) / (NM) and the efficiency of the switch is equal to (NM) / (N + 2).

    Des relations précédentes, on voit que le rapport M fournit un degré de liberté supplémentaire pour ajuster le gain forcé du transistor 1.From the previous relationships, we see that the report M provides additional freedom to adjust gain forced from transistor 1.

    Un avantage du commutateur de l'invention est qu'il permet une saturation du transistor principal 1 quelles que soient les conditions (température, caractéristiques du composant, charge de sortie).An advantage of the switch of the invention is that it allows saturation of the main transistor 1 whatever either the conditions (temperature, characteristics of the component, output load).

    Un autre avantage de l'invention est que la consommation du commutateur est proportionnelle au courant de sortie et qu'il engendre un courant de repos faible, ce qui rend la structure compatible avec des applications basse consommation.Another advantage of the invention is that consumption of the switch is proportional to the output current and that it generates a weak quiescent current, which makes the structure compatible with low consumption applications.

    Un autre avantage de l'invention est que la structure est compatible avec des applications basse tension (jusqu'à environ 1,5 V) en raison du faible nombre de tensions base-émetteur entre les lignes d'alimentation.Another advantage of the invention is that the structure is compatible with low voltage applications (up to about 1.5 V) due to the low number of base-emitter voltages between power lines.

    Un autre avantage de ce commutateur est qu'il est intégrable sur une puce en technologie bipolaire.Another advantage of this switch is that it is can be integrated on a chip in bipolar technology.

    La figure 3 représente un autre mode de réalisation du commutateur de l'invention, équipé d'un circuit 9 de limitation de courant interne. La structure de la figure 3 reprend les mêmes éléments que ceux représentés en figure 2.Figure 3 shows another embodiment of the switch of the invention, equipped with a limitation circuit 9 of internal current. The structure of Figure 3 shows the same elements as those shown in Figure 2.

    Selon ce mode de réalisation, une résistance de limitation de courant R9 est intercalée entre le collecteur du transistor 10 et celui du transistor 3. Cette résistance est associée à un transistor de type PNP 14 dont l'émetteur est connecté au collecteur du transistor 10 et dont la base est connectée au collecteur du transistor 3, le collecteur du transistor 14 étant connecté à la masse. Le circuit 9 limite le courant de sortie du commutateur à une valeur ILIM à peu près égale à (N/R9)*VBe14, où Vbe14 représente la tension base-émetteur du transistor 14. En effet, le transistor 14 devient progressivement conducteur et dérive vers la masse une partie du courant issue du transistor 10 dès que le courant de sortie atteint approximativement la valeur limite ci-dessus. Par conséquent, on régule le courant de sortie IOUT du dispositif approximativement à la valeur ILIM.According to this embodiment, a current limiting resistor R9 is interposed between the collector of transistor 10 and that of transistor 3. This resistor is associated with a PNP type transistor 14 whose emitter is connected to the collector of transistor 10 and the base of which is connected to the collector of transistor 3, the collector of transistor 14 being connected to ground. Circuit 9 limits the output current of the switch to a value I LIM approximately equal to (N / R9) * VBe14, where Vbe14 represents the base-emitter voltage of transistor 14. In fact, transistor 14 becomes progressively conductive and part of the current from transistor 10 drifts to ground as soon as the output current reaches approximately the above limit value. Consequently, the output current I OUT of the device is regulated approximately to the value I LIM .

    Une autre modification par rapport au circuit de la figure 2 est l'adjonction d'un transistor 15 de type NPN reliant la borne IN (par son collecteur) au collecteur du transistor 11 (par son émetteur) et dont la base est reliée au collecteur du transistor 10. Le rôle du transistor 15 est de délester le courant absorbé par le transistor 12 par une autre voie que le transistor 10 lorsque la limitation est active. En effet, quand le courant est limité, la tension de sortie VOUT n'est plus imposée par la tension d'entrée VIN (Vcc) diminuée de la chute de tension dans le transistor 1, mais se trouve imposée par la charge (VOUT=RQ*IIN, où RQ représente la résistance de la charge Q). La tension de sortie peut donc chuter à des potentiels très faibles voire nuls en cas de court-circuit en sortie. Dans de telles conditions, le transistor 11 se bloque et il est donc nécessaire d'écouler le courant absorbé par le transistor 12 par une autre voie que par la base du transistor 10 afin de ne pas affecter le courant issu du transistor 2 et, par conséquent, la valeur de courant de limitation.Another modification with respect to the circuit of FIG. 2 is the addition of a transistor 15 of NPN type connecting the terminal IN (by its collector) to the collector of transistor 11 (by its emitter) and whose base is connected to the collector of transistor 10. The role of transistor 15 is to relieve the current absorbed by transistor 12 by another channel than transistor 10 when the limitation is active. Indeed, when the current is limited, the output voltage V OUT is no longer imposed by the input voltage V IN (Vcc) minus the voltage drop in transistor 1, but is imposed by the load ( V OUT = RQ * I IN , where RQ represents the resistance of the load Q). The output voltage can therefore drop to very low or even zero potentials in the event of an output short circuit. Under such conditions, the transistor 11 is blocked and it is therefore necessary to drain the current absorbed by the transistor 12 by another way than by the base of the transistor 10 so as not to affect the current coming from the transistor 2 and, by Therefore, the limiting current value.

    Lorsque le transistor 10 commence à se saturer sous l'effet d'une augmentation de son courant de base, la tension collecteur-émetteur du transistor 10 diminue et provoque l'augmentation de la tension base-émetteur du transistor 15 d'où sa mise en conduction qui permet donc au transistor 12 de tirer son courant de collecteur non par la base du transistor 10 mais par le transistor 9, sans incidence notable sur la limitation de courant.When transistor 10 begins to saturate under the effect of an increase in its base current, the voltage collector-emitter of transistor 10 decreases and causes the increase in the base-emitter voltage of transistor 15 hence its conduction which therefore allows transistor 12 to draw its collector current not through the base of transistor 10 but by transistor 9, with no significant impact on the limitation of current.

    La figure 3 illustre par ailleurs une variante consistant à remplacer le court-circuit de la base et du collecteur du transistor 11 comme représenté en figure 2 par une résistance R11. La présence de la résistance R11 permet d'avancer l'instant de début de conduction du transistor 15 sans qu'il soit nécessaire d'attendre une saturation trop importante du transistor 10.Figure 3 also illustrates a variant consisting to replace the short circuit of the base and the collector of the transistor 11 as shown in figure 2 by a resistor R11. The presence of the resistance R11 allows to advance the instant at the start of conduction of transistor 15 without it being necessary to wait for too much saturation of the transistor 10.

    La figure 4 illustre une variante de réalisation d'un circuit 9' de limitation de courant.FIG. 4 illustrates an alternative embodiment of a circuit 9 'for current limitation.

    Par rapport au mode de réalisation de la figure 3, cette variante consiste à ôter le circuit 9 (relier donc directement le collecteur du transistor 10 au collecteur du transistor 3) et à connecter un dispositif 9' en amont de la borne IN. Plus précisément, une résistance de shunt Rs est intercalée entre la borne d'application du potentiel Vcc et la borne IN. Deux transistors de type PNP 16 et 17 sont connectés en miroir autour de la résistance Rs, l'émetteur du transistor 16 étant connecté à la borne Vcc tandis que l'émetteur du transistor 17 est connecté à la borne IN, les collecteurs respectifs des transistors 16 et 17 étant connectés à deux sources de courant 19 et 20 de même valeur, préférentiellement réalisées par un montage à transistors de type miroir de courant, et leur base étant interconnectées au collecteur du transistor 17. Par ailleurs, le collecteur du transistor 16 est connecté à la base d'un transistor NPN 18 dont le collecteur est relié à la borne IN et dont l'émetteur est relié au collecteur du transistor 4. Le reste du circuit de la figure 3 n'a pas été représenté en figure 4.Compared to the embodiment of FIG. 3, this variant consists in removing circuit 9 (therefore directly connecting the collector of transistor 10 to the collector of transistor 3) and to connect a device 9 'upstream of the terminal IN. More precisely, a shunt resistor Rs is inserted between the terminal for applying the potential Vcc and the terminal IN. Two PNP type transistors 16 and 17 are mirrored around the resistor Rs, the emitter of transistor 16 being connected to terminal Vcc while the emitter of transistor 17 is connected to the IN terminal, the respective collectors of the transistors 16 and 17 being connected to two current sources 19 and 20 of the same value, preferably produced by mounting current mirror type transistors, and their base being interconnected to the collector of transistor 17. In addition, the collector of transistor 16 is connected to the base of a NPN 18 transistor whose collector is connected to the IN terminal and whose emitter is connected to the collector of transistor 4. The rest of the circuit of figure 3 has not been represented in figure 4.

    Le courant de limitation du circuit 9' est fixé par le rapport de surfaces d'émetteurs des transistors 16 et 17. En posant ce rapport égal à P, le courant de limitation est de l'ordre de Vt*log(P)/Rs, où Vt désigne le potentiel thermique (environ 26 mV à 27°C).The limiting current of circuit 9 'is fixed by the emitter area ratio of transistors 16 and 17. In setting this ratio equal to P, the limiting current is the order of Vt * log (P) / Rs, where Vt denotes the thermal potential (approximately 26 mV at 27 ° C).

    Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaítront à l'homme de l'art. En particulier, les dimensions à donner aux différents transistors et résistances sont à la portée de l'homme du métier à partir des indications fonctionnelles données ci-dessus et de l'application.Of course, the present invention is capable of various variations and modifications that will appear to humans art. In particular, the dimensions to be given to the different transistors and resistors are within the reach of the skilled person from the functional indications given above and from the application.

    De plus, on notera que la structure proposée par l'invention est duale, c'est-à-dire qu'elle peut s'appliquer à une tension Vcc négative en remplaçant tous les transistors PNP par des transistors NPN et tous les transistors NPN par des transistors PNP.In addition, it should be noted that the structure proposed by the invention is dual, that is to say that it can be applied to a negative voltage Vcc by replacing all the PNP transistors by NPN transistors and all NPN transistors by PNP transistors.

    En outre, l'adjonction du circuit 8 de protection contre des courts-circuits, du circuit 9 de limitation du courant, ou du transistor de délestage 15 reste optionnelle en fonction de l'application.In addition, the addition of protection circuit 8 against short-circuits, of circuit 9 for limiting the current, or the load shedding transistor 15 remains optional in depending on the application.

    Claims (9)

    Commutateur en technologie bipolaire comprenant : un premier transistor principal (1) d'un premier type reliant une borne d'entrée (IN), destinée à être connectée à une première borne d'application d'une tension d'alimentation continue (Vcc), à une borne de sortie (OUT) destinée à être connectée à une charge (Q) à alimenter ; un deuxième transistor bipolaire (2) de même type que le premier, connecté entre ladite borne d'entrée et une entrée d'un circuit miroir de courant (3, 4) dont une sortie de recopie est connectée à la base du premier transistor, les bases des premier et deuxième transistors étant interconnectées et le premier transistor ayant une surface d'émetteur supérieure au second,    caractérisé en ce qu'il comporte en outre un circuit (6) de polarisation du deuxième transistor consistant en la recopie de la tension de sortie du commutateur sur le collecteur de ce deuxième transistor.Bipolar technology switch comprising: a first main transistor (1) of a first type connecting an input terminal (IN), intended to be connected to a first terminal for applying a direct supply voltage (Vcc), to an output terminal (OUT) intended to be connected to a load (Q) to be supplied; a second bipolar transistor (2) of the same type as the first, connected between said input terminal and an input of a current mirror circuit (3, 4) of which a feedback output is connected to the base of the first transistor, the bases of the first and second transistors being interconnected and the first transistor having an emitter surface greater than the second, characterized in that it further comprises a circuit (6) for biasing the second transistor consisting in copying the output voltage of the switch onto the collector of this second transistor. Commutateur selon la revendication 1, dans lequel ledit circuit miroir de courant (3, 4) est constitué d'un troisième transistor bipolaire (3) d'un deuxième type et d'un quatrième transistor bipolaire (4) du deuxième type reliant la base du premier transistor (1) à une deuxième borne (M) d'application de la tension d'alimentation, les bases des troisième et quatrième transistors étant interconnectées au collecteur du troisième transistor reliant le collecteur du deuxième transistor par l'intermédiaire d'un cinquième transistor bipolaire (10) du premier type appartenant au circuit de polarisation (6).The switch of claim 1, wherein said current mirror circuit (3, 4) consists of a third bipolar transistor (3) of a second type and of a fourth bipolar transistor (4) of the second type connecting the base of the first transistor (1) to a second application terminal (M) of the supply voltage, the basics of the third and fourth transistors being interconnected with the collector of the third transistor connecting the collector of the second transistor via a fifth bipolar transistor (10) of the first type belonging to the bias circuit (6). Commutateur selon la revendication 2, dans lequel le quatrième transistor (4) a une surface d'émetteur supérieure à celle du troisième transistor (3).The switch of claim 2, wherein the fourth transistor (4) has an upper emitter surface to that of the third transistor (3). Commutateur selon la revendication 2 ou 3, dans lequel le circuit de polarisation comporte en outre un sixième transistor (11) du deuxième type connecté entre ladite borne de sortie (OUT) par son émetteur et un septième transistor bipolaire (12) du deuxième type monté en miroir de courant sur lesdits troisième (3) et quatrième (4) transistors, la surface d'émetteur du septième transistor étant, de préférence, identique à celle du troisième transistor.Switch according to claim 2 or 3, in which the bias circuit further includes a sixth second type transistor (11) connected between said terminal output (OUT) by its emitter and a seventh bipolar transistor (12) of the second type mounted on a current mirror on said third (3) and fourth (4) transistors, the surface of emitter of the seventh transistor being preferably identical to that of the third transistor. Commutateur selon l'une quelconque des revendications 2 à 4, dans lequel une source de courant (7) de démarrage relie la base du premier transistor (1) à la deuxième borne d'application de la tension d'alimentation.Switch according to any one of the claims 2 to 4, in which a starting current source (7) connects the base of the first transistor (1) to the second terminal application of the supply voltage. Commutateur selon l'une quelconque des revendications 2 à 5, dans lequel un circuit (8) d'aide au démarrage injecte un courant sur le collecteur du deuxième transistor (2), le circuit d'aide au démarrage étant de préférence constitué d'une résistance (R8) en série avec un huitième transistor (13) du premier type connecté entre la borne d'entrée (IN) et ledit collecteur du deuxième transistor, la base du huitième transistor étant connectée à la base du premier transistor (1) de façon à injecter un courant image du courant de sortie.Switch according to any one of the claims 2 to 5, in which a circuit (8) for starting assistance injects current into the collector of the second transistor (2), the start-up assistance circuit preferably being constituted a resistor (R8) in series with an eighth transistor (13) of the first type connected between the input terminal (IN) and said collector of the second transistor, the base of the eighth transistor being connected to the base of the first transistor (1) of so as to inject an image current of the output current. Commutateur selon l'une quelconque des revendications 2 à 6, comprenant un circuit de limitation du courant interne constitué, de préférence, d'une résistance (R9) intercalée entre les collecteurs des cinquième (10) et troisième (3) transistors, et d'un neuvième transistor (14) de dérivation du courant vers la masse.Switch according to any one of the claims 2 to 6, including a current limiting circuit internal preferably made up of a resistor (R9) inserted between the collectors of the fifth (10) and third (3) transistors, and a ninth bypass transistor (14) current towards ground. Commutateur selon l'une quelconque des revendications 1 à 7, dans lequel les transistors du premier type sont des transistors PNP, les transistors du second type étant des transistors NPN.Switch according to any one of the claims 1 to 7, in which the transistors of the first type are PNP transistors, the transistors of the second type being NPN transistors. Commutateur selon l'une quelconque des revendications 1 à 7, dans lequel les transistors du premier type sont des transistors de type NPN, les transistors du second type étant des transistors de type PNP.Switch according to any one of the claims 1 to 7, in which the transistors of the first type are NPN type transistors, the second type transistors being PNP type transistors.
    EP04300320A 2003-06-12 2004-06-10 Switch in bipolar technology Withdrawn EP1486846A1 (en)

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    FR0307087A FR2856207A1 (en) 2003-06-12 2003-06-12 BIPOLAR TECHNOLOGY SWITCH
    FR0307087 2003-06-12

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    US4763066A (en) * 1986-09-23 1988-08-09 Huntron Instruments, Inc. Automatic test equipment for integrated circuits

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    FR2856207A1 (en) 2004-12-17
    US6992521B2 (en) 2006-01-31

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