EP0788047B1 - Device for current reference in an integrated circuit - Google Patents

Device for current reference in an integrated circuit Download PDF

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Publication number
EP0788047B1
EP0788047B1 EP97400209A EP97400209A EP0788047B1 EP 0788047 B1 EP0788047 B1 EP 0788047B1 EP 97400209 A EP97400209 A EP 97400209A EP 97400209 A EP97400209 A EP 97400209A EP 0788047 B1 EP0788047 B1 EP 0788047B1
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EP
European Patent Office
Prior art keywords
transistor
resistor
transistors
current
drain
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EP97400209A
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German (de)
French (fr)
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EP0788047A1 (en
Inventor
François Cabinet Ballot-Schmit Tailliet
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STMicroelectronics SA
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STMicroelectronics SA
SGS Thomson Microelectronics SA
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Priority claimed from FR9601168A external-priority patent/FR2744262B1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S323/00—Electricity: power supply or regulation systems
    • Y10S323/907—Temperature compensation of semiconductor

Definitions

  • the invention relates to a reference device for stable current in integrated circuit.
  • Such devices are used in particular in memory circuits, particular for generating timing signals stable necessary for reading or writing memory cells.
  • EP-A-0 052 553 describes a current generator using the threshold difference between two transistors each mounted in a branch of a current mirror device, a resistance being placed in one of the branches to make up for this difference voltage and produce a stable current.
  • the invention therefore relates to a device for intrinsically stable current reference, without feedback to compensate for this or that variation.
  • the invention relates to a integrated circuit current reference device with a reference resistance.
  • the device includes first and second transistor of the same type of conductivity, the first having its grid and its drain connected together to a first resistance terminal, the second having its grid and its drain connected together to a second resistance terminal, and the first transistor having a threshold voltage higher than that of the second transistor, the two transistors being polarized in saturated mode, the source of each of these transistors being polarized at the same potential as the substrate or the box in which the transistor is made.
  • the device maybe transposed from one manufacturing technology to another without simulations.
  • Figure 1 shows the electronic diagram of a integrated circuit current reference device according to the invention.
  • the first transistor T1 has a voltage of threshold higher than that of the second transistor T2.
  • the transistors T1 and T2 are of type N produced in a conventional technology with P substrate.
  • the transistor T2 is then of the native type while the transistor T1 is of the enriched type, in order to fulfill the condition on the threshold voltages (Vt 1 ⁇ Vt 2 ).
  • Their sources are then connected to ground.
  • the substrate P is therefore connected to the same potential as the source of the transistors T1 and T2, which has the effect of eliminating the substrate effect. There is therefore a particularly stable threshold voltage with the supply voltage.
  • a resistor R1 is connected to the drain of the first transistor T1 to call a load current I1.
  • This polarization resistance R1 may very well be directly connected to the supply voltage Vcc, as shown in dotted lines in FIG. 1, or then, a bias circuit CP can be provided.
  • the two transistors T1 and T2 which are mounted as a diode are then in saturated mode and there is on their drain, the threshold voltage of the transistor.
  • the voltage V tN V tNna ' where V tN is the threshold voltage V t1 of the enriched transistor T1, of the order of 0.8 volt and V tNna is the threshold voltage V t2 of the native transistor T2, or about 0.2 volts.
  • This reference current is independent of the temperature. Indeed, according to theory and as verified in practice, the threshold voltages of the native transistor and of the enriched transistor vary in parallel, by two millivolts per degree, so that their difference is practically independent of the temperature.
  • the only variation with the possible temperature of the reference current obtained by the device of the invention can only come from the reference resistance Rr.
  • This technology is that used in Mos technology with low drain doping called "LDD", and corresponding to a first implantation and slightly doped diffusion (N-) before the highly doped diffusion, to obtain a less abrupt junction profile, having better tensile strength.
  • LDD low drain doping
  • N- slightly doped diffusion
  • Variations in characteristics due to the process manufacturing affect all threshold voltages as well as the value of the reference resistance.
  • Vtn-Vtna threshold voltages
  • the variation can only come in process from the variation of the threshold implant dose of the transistor enriched T1, since the thickness of the gate oxide is the same for both transistors and that the threshold variation due to the initial doping operation of the substrate is also found on the transistor native only on the enriched transistor.
  • the variation in resistance with the process is of the same order. In the worst case, the variation of the reference current due to the process is thus of the order of ⁇ 20%, which is satisfactory.
  • the polarization resistance of device could be connected directly to the voltage Vcc supply.
  • the device then has the advantage of operate at very low voltage, since the path critical between supply voltage and ground is given by R1, Rr, T2.
  • the current of load It is then directly dependent on the voltage Vcc supply. If we vary the voltage Vcc supply in a range from 1.6 volts to 6 volts, the charging current of the first transistor will vary greatly, with an annoying effect on the stability of the drain voltage of the first transistor and therefore on the reference current.
  • a bias circuit CP which includes a transistor Mos T3, diode mounted, to impose on the resistance load R1 a transistor threshold voltage higher than the threshold voltage of transistor T1, at place of the supply voltage Vcc.
  • a native P-type transistor to be able to bias the enriched transistor N T1.
  • the tension of threshold of a native P transistor (about 1.5 volts) is indeed higher than the threshold voltage of a enriched N transistor (approximately 0.8 volts).
  • House could very well choose an N-type transistor, more enriched than transistor T1.
  • I1 (V tPna - V tN ) / R1.
  • the reference current Ir (V tN -V tNna ) / Rr is then practically independent of the supply voltage Vcc.
  • resistor R1 is charged from the resistor R2 and the reference resistor Rr is charged from the resistor R1. So that the current is sufficient to bias the entire device, it is therefore necessary to choose resistors with values such as R2 ⁇ R1 ⁇ Rr. And if you want to limit the current consumption of the device, you need high resistances.
  • resistors with values such as R2 ⁇ R1 ⁇ Rr.
  • the technology in drain extension it will be preferable to use the technology in drain extension to achieve the resistances , because it is less bulky (2000 ohms / square) than the source drain technology (typically 50 to 100 ohms / square in P + , 20 to 50 ohms / square in N +).
  • this drain-extension technology is less stable in temperature.
  • FIG. 2 thus represents another electronic diagram of a current reference device in integrated circuit according to an alternative embodiment of the invention, which makes it possible to use resistors of lower values.
  • a Mos transistor T4 is used as a follower to apply to the load resistor R1, a bias voltage independent of the supply voltage.
  • the transistor Mos T4 is of type N and connected between the supply voltage Vcc and the resistor R1.
  • This transistor T4 is controlled on its gate by the voltage imposed by the series connection of a transistor T5 mounted in direct diode (gate and drain connected) and of a transistor T6 mounted in direct diode. These two transistors T5 and T6 are connected in series between the gate of the follower transistor T4 and the ground.
  • the transistor T5 is preferably of the same type as the transistor T4 and with the same threshold voltage (to compensate as we will see).
  • the transistor T6 is of type P and native. It could be of type N. It is only necessary that its threshold voltage is greater than that of transistor T1.
  • a resistor R3 is provided between the supply voltage Vcc and the transistor T5 to bias the transistors T5 and T6 in saturated mode.
  • the transistors T4 and T5 of type N are chosen to be native, in order to have the lowest threshold voltage, which allows the device to operate at the lowest possible supply voltage. In this manner is found on the terminal of the load resistor R1 connected to the transistor T4, the voltage (V F + ASPR TNNA -Vt Nna) is thus V ASPR.
  • the load current of the transistor T1 is therefore (V tPna -Vt tNna ) / R1 and is therefore very stable, as already explained previously.
  • Figure 3 shows a variant of the device in Figure 2, which further improves the stability of the reference current.
  • the resistor R3 is directly supplied by the voltage logic supply to the circuit. If the tension diet varies, for example if it increases, we has an effect on the gate of transistor T4 follower, which will tend to increase the current of reference Ir.
  • a resistor R4 is inserted between the supply voltage Vcc and terminal C of the resistance R3.
  • a branch identical to the branch (T5, T6) is provided between terminal C and earth, comprising two transistors T8 and T9.
  • the T8 transistor is mounted as a diode and identical to transistor T5.
  • the transistor T9 is diode mounted and identical to transistor T6. In the example they are all the same type N enriched and of the same geometry (W / L). Which is important in practice is that two by two, T5 and T8, T6 and T9, are identical to have the compensation expected.
  • This branch (T8, T9) serves as a limiter of the tension at node C, to make this node less dependent on variations in supply voltage Vdd.
  • the node C follows the increase of the supply voltage through the resistor R4. But as soon as node C reaches a potential of the order of 2 x Vt n (sum of the threshold voltages of transistors T8 and T9 in series), the branch T8, T9, tends to maintain this level at node C: the voltage Vc will then move much less, as shown in Figure 4. Indeed T8 and T9 do not have the resistance R3 in their branch, they will pass more current (I) than T5 and T6. Thus the voltage on this branch given by Vt8 + Vt9 + Ron.I, where Ron is the equivalent pass resistance of the two transistors, will always be slightly higher than Vt5 + Vt6 (Vti is the threshold voltage of the transistor Ti).
  • the device shown may very well be made in NMOS technology.
  • a current Ir from which we can obtain other reference currents, by mirrored arrangements of current.
  • Such an assembly is for example shown on the Figure 2: an N-type native T7 transistor is mounted in current mirror with respect to transistor T2: its gate is controlled by the gate of transistor T2.
  • Another reference resistance Rr ' is connected to the drain of transistor T7 on one terminal. The other terminal is connected to the supply voltage Vcc.
  • Vcc supply voltage
  • the current reference device in circuit integrated according to the invention therefore offers great stability. And by design without feedback, it can be transposed from a technology of manufacturing to another without simulations, which is not not the least of its advantages.

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  • Microelectronics & Electronic Packaging (AREA)
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Description

L'invention concerne un dispositif de référence de courant stable en circuit intégré. De tels dispositifs sont notamment utilisés dans les circuits mémoires, en particulier pour générer des signaux de temporisation stables nécessaires à la lecture ou l'écriture des cellules mémoires.The invention relates to a reference device for stable current in integrated circuit. Such devices are used in particular in memory circuits, particular for generating timing signals stable necessary for reading or writing memory cells.

La stabilité en courant est recherchée sur une plage étendue de température de l'ordre de -50°C à +130°C. Par ailleurs, on cherche à concevoir des circuits capables de fonctionner dans une gamme de tension allant de moins de deux volts jusqu'à environ cinq volts. Il faut donc la possibilité de travailler en basse tension (deux volts et moins) tout en assurant la stabilité en tension dans cette gamme. Enfin, les dispersions des caractéristiques dues au procédé de fabrication doivent rester sans effets sur le courant de référence, pour avoir une bonne fiabilité en fabrication.Current stability is sought on a extended temperature range in the range of -50 ° C to + 130 ° C. Furthermore, we are trying to design circuits capable of operating in a range of voltage ranging from less than two volts to approximately five volts. So you have to have the opportunity to work in low voltage (two volts and less) while ensuring the voltage stability in this range. Finally, the dispersions of the characteristics due to the manufacturing must remain without effects on the current of reference, to have a good reliability in manufacturing.

Il a toujours été difficile de faire des dispositifs de référence de courant répondant à ces critères de stabilité, en particulier dans les technologies logiques telles les technologies Mos ou Cmos, parce qu'on ne connaít a priori aucune caractéristique de procédé qui permettrait d'obtenir une telle stabilité en courant.It has always been difficult to make current reference devices meeting these stability criteria, especially in logical technologies such as Mos technologies or Cmos, because we don't know a priori any characteristic of process which would make it possible to obtain such current stability.

Les dispositifs de génération de référence de courant connus en technologie logique sont pour la plupart basés sur la structure de miroir de Wilson. Cependant le courant de référence obtenu est assez dépendant du procédé de fabrication. On connaít un autre type de dispositif décrit dans la demande FR-A-2 737 319. Ce dispositif fournit un courant basé sur la différence entre la tension de seuil VtN d'un transistor enrichi et la tension de seuil VtNna d'un transistor natif de même type de conductivité. Le transistor natif attaque une résistance de référence et le courant de référence est donné par (VtN-VtNna)/R. Ce courant de référence est stabilisé par une boucle de contre-réaction formée par le montage en série d'un transistor Mos de type P et d'un transistor Mos de type N, natif et monté en diode sur la grille du transistor natif qui attaque la résistance de référence. Néanmoins, l'utilisation d'une contre-réaction pour obtenir la stabilité n'est pas une solution très satisfaisante. De plus, dans ce dispositif, la tension de seuil du transistor natif qui attaque la résistance de référence varie avec la tension source-substrat (effet substrat).Current reference generation devices known in logic technology are mostly based on the Wilson mirror structure. However, the reference current obtained is fairly dependent on the manufacturing process. We know another type of device described in application FR-A-2 737 319. This device provides a current based on the difference between the threshold voltage V tN of an enriched transistor and the threshold voltage V tNna of a native transistor with the same type of conductivity. The native transistor drives a reference resistor and the reference current is given by (V tN -V tNna ) / R. This reference current is stabilized by a feedback loop formed by the series connection of a P-type Mos transistor and an N-type Mos transistor, native and diode mounted on the gate of the native transistor which attacks the reference resistance. However, the use of a feedback to obtain stability is not a very satisfactory solution. In addition, in this device, the threshold voltage of the native transistor which attacks the reference resistance varies with the source-substrate voltage (substrate effect).

La demande EP-A-0 052 553 décrit un générateur de courant utilisant la différence de seuil entre deux transistors chacun monté dans une branche d'un dispositif à miroir de courant, une résistance étant placée dans l'une des branches pour rattraper cette différence de tension et produire un courant stable.EP-A-0 052 553 describes a current generator using the threshold difference between two transistors each mounted in a branch of a current mirror device, a resistance being placed in one of the branches to make up for this difference voltage and produce a stable current.

Dans l'invention, une autre structure en circuit intégré a été trouvée pour fournir une référence de courant stable.In the invention, another circuit structure integrated was found to provide a reference of stable current.

L'invention a donc pour objet un dispositif de référence de courant intrinsèquement stable, sans contre-réaction pour compenser telle ou telle variation.The invention therefore relates to a device for intrinsically stable current reference, without feedback to compensate for this or that variation.

Telle que revendiquée, l'invention concerne un dispositif de référence de courant en circuit intégré avec une résistance de référence. Selon l'invention, le dispositif comprend un premier et un deuxième transistor de même type de conductivité, le premier ayant sa grille et son drain reliés ensemble à une première borne de la résistance, le deuxième ayant sa grille et son drain reliés ensemble à une deuxième borne de la résistance, et le premier transistor ayant une tension de seuil supérieure à celle du deuxième transistor, les deux transistors étant polarisés en mode saturé, la source de chacun de ces transistors étant polarisée au même potentiel que le substrat ou le caisson dans lequel le transistor est réalisé.As claimed, the invention relates to a integrated circuit current reference device with a reference resistance. According to the invention, the device includes first and second transistor of the same type of conductivity, the first having its grid and its drain connected together to a first resistance terminal, the second having its grid and its drain connected together to a second resistance terminal, and the first transistor having a threshold voltage higher than that of the second transistor, the two transistors being polarized in saturated mode, the source of each of these transistors being polarized at the same potential as the substrate or the box in which the transistor is made.

On obtient un courant de référence intrinsèquement stable en tension d'alimentation, température et procédé de fabrication. Le dispositif peut-être transposé d'une technologie de fabrication à une autre sans simulations.We obtain an intrinsic reference current stable in supply voltage, temperature and manufacturing process. The device maybe transposed from one manufacturing technology to another without simulations.

D'autres caractéristiques et avantages de l'invention sont détaillés dans la description jointe faite à titre indicatif et non limitatif de l'invention et en référence aux dessins annexés dans lesquels:

  • la figure 1 représente un mode de réalisation d'un dispositif de référence de courant selon l'invention,
  • la figure 2 représente un autre mode de réalisation de l'invention,
  • la figure 3 représente une variante du dispositif de la figure 2 et
  • la figure 4 montre l'évolution de la tension au noeud C du dispositif de la figure 3 en fonction de la tension d'alimentation.
Other characteristics and advantages of the invention are detailed in the attached description given by way of indication and without limitation of the invention and with reference to the appended drawings in which:
  • FIG. 1 represents an embodiment of a current reference device according to the invention,
  • FIG. 2 represents another embodiment of the invention,
  • FIG. 3 represents a variant of the device of FIG. 2 and
  • Figure 4 shows the evolution of the voltage at node C of the device of Figure 3 as a function of the supply voltage.

La figure 1 représente le schéma électronique d'un dispositif de référence de courant en circuit intégré selon l'invention.Figure 1 shows the electronic diagram of a integrated circuit current reference device according to the invention.

Il comporte principalement une résistance de référence Rr qui sera traversée par le courant de référence Ir. Une première borne A de cette résistance est connectée au drain d'un premier transistor Mos T1. Une deuxième borne B de la résistance de référence est connectée au drain d'un deuxième transistor Mos T2. Ces deux transistors ont chacun leur grille reliée à leur drain. Et le premier transistor T1 a une tension de seuil supérieure à celle du deuxième transistor T2.It mainly comprises a resistance of reference Rr which will be crossed by the current of reference Ir. A first terminal A of this resistor is connected to the drain of a first Mos transistor T1. A second terminal B of the reference resistance is connected to the drain of a second Mos T2 transistor. These two transistors each have their gate connected to their drain. And the first transistor T1 has a voltage of threshold higher than that of the second transistor T2.

Dans l'exemple, les transistors T1 et T2 sont de type N réalisés dans une technologie classique à substrat P. Le transistor T2 est alors du type natif tandis que le transistor T1 est du type enrichi, pour remplir la condition sur les tensions de seuil (Vt1<Vt2). Leurs sources sont alors reliées à la masse. Le substrat P est donc relié au même potentiel que la source des transistors T1 et T2, ce qui a pour effet de supprimer l'effet substrat. On a donc une tension de seuil particulièrement stable avec la tension d'alimentation.In the example, the transistors T1 and T2 are of type N produced in a conventional technology with P substrate. The transistor T2 is then of the native type while the transistor T1 is of the enriched type, in order to fulfill the condition on the threshold voltages (Vt 1 <Vt 2 ). Their sources are then connected to ground. The substrate P is therefore connected to the same potential as the source of the transistors T1 and T2, which has the effect of eliminating the substrate effect. There is therefore a particularly stable threshold voltage with the supply voltage.

Une résistance R1 est connectée au drain du premier transistor T1 pour appeler un courant de charge I1. Cette résistance de polarisation R1 peut très bien être reliée directement à la tension d'alimentation Vcc, comme représenté en pointillé sur la figure 1, ou alors, on peut prévoir un circuit de polarisation CP.A resistor R1 is connected to the drain of the first transistor T1 to call a load current I1. This polarization resistance R1 may very well be directly connected to the supply voltage Vcc, as shown in dotted lines in FIG. 1, or then, a bias circuit CP can be provided.

Les deux transistors T1 et T2 qui sont montés en diode sont alors en mode saturé et on retrouve sur leur drain, la tension de seuil du transistor. On retrouve ainsi aux bornes de la résistance de référence Rr, la tension VtN VtNna' où VtN est la tension de seuil Vt1 du transistor enrichi T1, de l'ordre de 0.8 volt et VtNna est la tension de seuil Vt2 du transistor natif T2, soit environ 0.2 volt. Le courant de référence Ir est donc donné par la relation Ir= (VtN-VtNna)/Rr.The two transistors T1 and T2 which are mounted as a diode are then in saturated mode and there is on their drain, the threshold voltage of the transistor. Thus found at the terminals of the reference resistance Rr, the voltage V tN V tNna ' where V tN is the threshold voltage V t1 of the enriched transistor T1, of the order of 0.8 volt and V tNna is the threshold voltage V t2 of the native transistor T2, or about 0.2 volts. The reference current Ir is therefore given by the relation Ir = (V tN -V tNna ) / Rr.

Ce courant de référence est indépendant de la température. En effet, selon la théorie et comme vérifié en pratique, les tensions de seuil du transistor natif et du transistor enrichi varient en parallèle, de deux millivolts par degré, en sorte que leur différence est pratiquement indépendante de la température. La seule variation avec la température possible du courant de référence obtenu par le dispositif de l'invention ne peut venir que de la résistance de référence Rr. On pourra choisir de réaliser cette résistance en technologie dite de drain extension. Cette technologie est celle utilisée en technologie Mos à faible dopage de drain dite "LDD", et correspondant à une première implantation et diffusion peu dopée (N-) avant la diffusion très dopée, pour obtenir un profil de jonction moins abrupt, ayant une meilleure tenue en tension. On peut aussi réaliser la résistance de référence en diffusion de type source/drain de transistor, donc plus dopée (N+ ou P+), plus stable en température.This reference current is independent of the temperature. Indeed, according to theory and as verified in practice, the threshold voltages of the native transistor and of the enriched transistor vary in parallel, by two millivolts per degree, so that their difference is practically independent of the temperature. The only variation with the possible temperature of the reference current obtained by the device of the invention can only come from the reference resistance Rr. We can choose to achieve this resistance in technology called drain extension. This technology is that used in Mos technology with low drain doping called "LDD", and corresponding to a first implantation and slightly doped diffusion (N-) before the highly doped diffusion, to obtain a less abrupt junction profile, having better tensile strength. One can also realize the reference resistance in diffusion of source / drain type of transistor, therefore more doped (N + or P + ), more stable in temperature.

Les variations des caractéristiques dues au procédé de fabrication, affectent toutes les tensions de seuil ainsi que la valeur de la résistance de référence. Pour la différence des tensions de seuil (Vtn-Vtna) du transistor N enrichi T1 et du transistor N natif T2, la variation ne peut provenir en procédé que de la variation de la dose d'implant de seuil du transistor enrichi T1, puisque l'épaisseur de l'oxyde de grille est la même pour les deux transistors et que la variation de seuil due à l'opération de dopage initial du substrat se retrouve aussi bien sur le transistor natif que sur le transistor enrichi. On peut estimer cette variation à ±10%. La variation de la résistance avec le procédé est du même ordre. Dans le pire cas, la variation du courant de référence due au procédé est ainsi de l'ordre de ±20%, ce qui est satisfaisant. Variations in characteristics due to the process manufacturing, affect all threshold voltages as well as the value of the reference resistance. For the difference in threshold voltages (Vtn-Vtna) of enriched N transistor T1 and the native N transistor T2, the variation can only come in process from the variation of the threshold implant dose of the transistor enriched T1, since the thickness of the gate oxide is the same for both transistors and that the threshold variation due to the initial doping operation of the substrate is also found on the transistor native only on the enriched transistor. We can estimate this variation to ± 10%. The variation in resistance with the process is of the same order. In the worst case, the variation of the reference current due to the process is thus of the order of ± 20%, which is satisfactory.

On a vu que la résistance de polarisation du dispositif pouvait être reliée directement à la tension d'alimentation Vcc. Le dispositif a alors l'avantage de fonctionner à très basse tension, puisque le chemin critique entre la tension d'alimentation et la masse est donné par R1, Rr, T2. Cependant, le courant de charge Il est alors directement dépendant de la tension d'alimentation Vcc. Si on fait varier la tension d'alimentation Vcc dans une gamme allant de 1.6 volt à 6 volts, le courant de charge du premier transistor variera fortement, avec une incidence gênante sur la stabilité de la tension de drain du premier transistor et par conséquent sur le courant de référence.We have seen that the polarization resistance of device could be connected directly to the voltage Vcc supply. The device then has the advantage of operate at very low voltage, since the path critical between supply voltage and ground is given by R1, Rr, T2. However, the current of load It is then directly dependent on the voltage Vcc supply. If we vary the voltage Vcc supply in a range from 1.6 volts to 6 volts, the charging current of the first transistor will vary greatly, with an annoying effect on the stability of the drain voltage of the first transistor and therefore on the reference current.

Pour cette raison, dans une première variante représentée à la figure 1, on prévoit d'utiliser un circuit de polarisation CP, qui comprend un transistor Mos T3, monté en diode, pour imposer sur la résistance de charge R1 une tension de seuil de transistor supérieure à la tension de seuil du transistor T1, au lieu de la tension d'alimentation Vcc. Par exemple, on choisit un transistor de type P natif pour pouvoir polariser le transistor N enrichi T1. La tension de seuil d'un transistor P natif (1.5 volts environ) est en effet supérieure à la tension de seuil d'un transistor N enrichi (0.8 volt environ). Mais on pourrait très bien choisir un transistor de type N, plus enrichi que le transistor T1. Dans l'exemple représenté on polarise le transistor T3 de type P en mode saturé au moyen d'une résistance R2 reliée à la tension d'alimentation Vcc.For this reason, in a first variant shown in Figure 1, we plan to use a bias circuit CP, which includes a transistor Mos T3, diode mounted, to impose on the resistance load R1 a transistor threshold voltage higher than the threshold voltage of transistor T1, at place of the supply voltage Vcc. For example, we choose a native P-type transistor to be able to bias the enriched transistor N T1. The tension of threshold of a native P transistor (about 1.5 volts) is indeed higher than the threshold voltage of a enriched N transistor (approximately 0.8 volts). House could very well choose an N-type transistor, more enriched than transistor T1. In the example shown we polarize the P type transistor T3 in saturated mode by means of an R2 resistor connected to the supply voltage Vcc.

On se retrouve alors avec un courant de charge I1 du transistor T1 proportionnel à la différence entre la tension de seuil VtPna d'un transistor P natif et la tension de seuil VtN d'un transistor N enrichi : I1=(VtPna-VtN)/R1. Ainsi, lorsque Vcc varie, la tension de drain du transistor T1 ne varie quasiment plus. Le courant de référence Ir= (VtN-VtNna)/Rr est alors pratiquement indépendant de la tension d'alimentation Vcc.We then find ourselves with a load current I1 of the transistor T1 proportional to the difference between the threshold voltage V tPna of a native P transistor and the threshold voltage V tN of an enriched transistor N: I1 = (V tPna - V tN ) / R1. Thus, when Vcc varies, the drain voltage of the transistor T1 hardly changes any more. The reference current Ir = (V tN -V tNna ) / Rr is then practically independent of the supply voltage Vcc.

En cumulant toutes les variations : tension d'alimentation, température, procédé, on a pu ainsi obtenir avec les valeurs indiquées sur le schéma de la figure 1 et avec des résistances réalisées en drain extension, un courant de référence variant dans un rapport Imax/Imin inférieur à 3.By accumulating all the variations: tension feed, temperature, process, so we could obtain with the values indicated on the diagram of the figure 1 and with resistances made in drain extension, a reference current varying in a Imax / Imin ratio less than 3.

En pratique, il faut noter que la résistance R1 est chargée à partir de la résistance R2 et la résistance de référence Rr est chargée à partir de la résistance R1. Pour que le courant soit suffisant pour polariser l'ensemble du dispositif, il faut donc choisir des résistances de valeurs telles que R2<R1<Rr. Et si on veut limiter la consommation de courant du dispositif, il faut des résistances élevées. Sur la figure 1, on a ainsi retenu les valeurs suivantes : 50 kiloohms pour R2, 200 kiloohms pour R1 et 500 kiloohms pour Rr. Avec de telles valeurs de résistance, il sera préférable d'utiliser la technologie en drain extension pour réaliser les résistances, car elle est moins encombrante (2000 ohms/carré) que la technologie source drain (typiquement 50 à 100 ohms/carré en P+, 20 à 50 ohms/carré en N+). Cependant cette technologie en drain-extension est moins stable en température.In practice, it should be noted that the resistor R1 is charged from the resistor R2 and the reference resistor Rr is charged from the resistor R1. So that the current is sufficient to bias the entire device, it is therefore necessary to choose resistors with values such as R2 <R1 <Rr. And if you want to limit the current consumption of the device, you need high resistances. In Figure 1, we have thus retained the following values: 50 kiloohms for R2, 200 kiloohms for R1 and 500 kiloohms for Rr. With such resistance values, it will be preferable to use the technology in drain extension to achieve the resistances , because it is less bulky (2000 ohms / square) than the source drain technology (typically 50 to 100 ohms / square in P + , 20 to 50 ohms / square in N +). However, this drain-extension technology is less stable in temperature.

Par ailleurs, si on utilise des résistances de valeurs élevées, on augmente la constante de temps du dispositif liée aux capacité parasites de drain. Comme le courant est aussi plus faible, il est aussi plus lent à s'établir. Ceci peut être un inconvénient pour certaines applications.Furthermore, if we use resistors of high values, the time constant of the device linked to parasitic drain capacity. As the current is also weaker, it is also more slow to establish. This can be a disadvantage for some applications.

La figure 2 représente ainsi un autre schéma électronique d'un dispositif de référence de courant en circuit intégré selon une variante de réalisation de l'invention, qui permet d'utiliser des résistances de valeurs plus faibles. Dans cette variante, on utilise un transistor Mos T4 en suiveur pour appliquer à la résistance de charge R1, une tension de polarisation indépendante de la tension d'alimentation. Dans l'exemple le transistor Mos T4 est de type N et connecté entre la tension d'alimentation Vcc et la résistance R1. Ce transistor T4 est commandé sur sa grille par la tension imposée par le montage série d'un transistor T5 monté en diode en direct (grille et drain reliées) et d'un transistor T6 monté en diode en direct. Ces deux transistors T5 et T6 sont connectés en série entre la grille du transistor suiveur T4 et la masse. Le transistor T5 est de préférence de même type que le transistor T4 et avec la même tension de seuil (pour se compenser comme on va le voir). Dans l'exemple le transistor T6 est de type P et natif. Il pourrait être de type N. Il faut seulement que sa tension de seuil soit supérieure à celle du transistor T1. Une résistance R3 est prévue entre la tension d'alimentation Vcc et le transistor T5 pour polariser les transistors T5 et T6 en mode saturé. Enfin, dans l'exemple, les transistors T4 et T5 de type N sont choisis natifs, pour avoir la plus faible tension de seuil, qui permet au dispositif de fonctionner à la plus basse tension d'alimentation possible. De cette manière on retrouve sur la borne de la résistance de charge R1 connectée au transistor T4, la tension (VtNna+FtPna-VtNna) soit donc VtPna. Le courant de charge du transistor T1 est donc (VtPna-VttNna)/R1 et est donc très stable, comme déjà expliqué précédemment.FIG. 2 thus represents another electronic diagram of a current reference device in integrated circuit according to an alternative embodiment of the invention, which makes it possible to use resistors of lower values. In this variant, a Mos transistor T4 is used as a follower to apply to the load resistor R1, a bias voltage independent of the supply voltage. In the example, the transistor Mos T4 is of type N and connected between the supply voltage Vcc and the resistor R1. This transistor T4 is controlled on its gate by the voltage imposed by the series connection of a transistor T5 mounted in direct diode (gate and drain connected) and of a transistor T6 mounted in direct diode. These two transistors T5 and T6 are connected in series between the gate of the follower transistor T4 and the ground. The transistor T5 is preferably of the same type as the transistor T4 and with the same threshold voltage (to compensate as we will see). In the example the transistor T6 is of type P and native. It could be of type N. It is only necessary that its threshold voltage is greater than that of transistor T1. A resistor R3 is provided between the supply voltage Vcc and the transistor T5 to bias the transistors T5 and T6 in saturated mode. Finally, in the example, the transistors T4 and T5 of type N are chosen to be native, in order to have the lowest threshold voltage, which allows the device to operate at the lowest possible supply voltage. In this manner is found on the terminal of the load resistor R1 connected to the transistor T4, the voltage (V F + ASPR TNNA -Vt Nna) is thus V ASPR. The load current of the transistor T1 is therefore (V tPna -Vt tNna ) / R1 and is therefore very stable, as already explained previously.

L'intérêt de cette variante est que dans la résistance R3, on ne consomme que le courant nécessaire pour polariser les transistors T5 et T6, contrairement au schéma de la figure 1 où la résistance R2 doit non seulement polariser le transistor T3, mais aussi fournir assez de courant pour la résistance de polarisation R1 et la résistance de référence Rr. Le schéma de la figure 2 permet en pratique d'autoriser une consommation de courant plus importante dans les résistances R1 et Rr, et permet donc d'abaisser la valeur de ces résistances. On a donc un courant de référence qui pourra s'établir plus rapidement.The advantage of this variant is that in the resistance R3, only the current required is consumed to polarize the transistors T5 and T6, unlike in the diagram of figure 1 where the resistance R2 must not only bias transistor T3, but also provide enough current for the resistance of polarization R1 and the reference resistance Rr. diagram of Figure 2 allows in practice to authorize higher current consumption in resistors R1 and Rr, and therefore makes it possible to lower the value of these resistors. So we have a current of reference that can be established more quickly.

De plus, si les valeurs de résistances sont plus faibles, on est moins gêné sur le plan de l'encombrement pour choisir de réaliser au moins la résistance de référence en technologie source/drain. On améliore aussi la tenue en température du dispositif du fait que les résistances sont plus dopées. On pourrait réaliser la résistance de charge R1 en diffusion source/drain également, mais cela a une moindre incidence sur la stabilité.In addition, if the resistance values are more weak, we are less embarrassed in terms of the space required to choose to carry out at least the reference resistance in source / drain technology. We also improves the temperature resistance of the device fact that the resistors are more doped. We could realize the load resistance R1 in diffusion source / drain also, but this has a lesser impact on stability.

On obtient donc un dispositif très stable. Par contre le fonctionnement en basse tension est dégradé par le transistor suiveur T4 qui ajoute une chute de tension supplémentaire (0.5 volt) dans le chemin critique du montage. En pratique, on a pu vérifier avec les valeurs indiquées sur la figure 2 et une résistance de référence réalisée en diffusion de type source/drain de transistor P que le courant est stable dans une gamme de tension allant de deux volts à 5.5 volts pour une température variant entre -50 et +150°c. Bien entendu, cette deuxième variante fonctionne aussi avec des valeurs de résistances élevées, mais on retrouve alors les mêmes inconvénients (temps de réponse plus lent, encombrement).A very stable device is therefore obtained. By against low voltage operation is degraded by the follower transistor T4 which adds a drop of additional voltage (0.5 volt) in the path critical of the assembly. In practice, we were able to verify with the values indicated in figure 2 and a resistance of reference carried out in source / drain type diffusion of transistor P that the current is stable in a voltage range from two volts to 5.5 volts for a temperature varying between -50 and + 150 ° c. Good heard, this second variant also works with high resistance values, but we find then the same drawbacks (longer response time slow, clutter).

La figure 3 représente une variante du dispositif de la figure 2, qui permet d'améliorer encore la stabilité du courant de référence.Figure 3 shows a variant of the device in Figure 2, which further improves the stability of the reference current.

En effet, dans le dispositif de la figure 2, la résistance R3 est directement alimentée par la tension d'alimentation logique du circuit. Si la tension d'alimentation varie, par exemple si elle augmente, on a une répercussion sur la grille du transistor T4 suiveur, ce qui va tendre à faire augmenter le courant de référence Ir.Indeed, in the device of Figure 2, the resistor R3 is directly supplied by the voltage logic supply to the circuit. If the tension diet varies, for example if it increases, we has an effect on the gate of transistor T4 follower, which will tend to increase the current of reference Ir.

Une amélioration de la stabilité du courant peut être apportée avec le dispositif de la figure 3.Improved current stability can be brought with the device of Figure 3.

Dans ce dispositif une résistance R4 est intercalée entre la tension d'alimentation Vcc et la borne C de la résistance R3. Et une branche identique à la branche (T5, T6) est prévue entre la borne C et la masse, comprenant deux transistor T8 et T9. Le transistor T8 est montée en diode et identique au transistor T5. Le transistor T9 est monté en diode et identique au transistor T6. Dans l'exemple ils sont tous de même type N enrichis et de même géométrie (W/L). Ce qui est important en pratique c'est que deux à deux, T5 et T8, T6 et T9, soient identiques pour avoir la compensation escomptée.In this device a resistor R4 is inserted between the supply voltage Vcc and terminal C of the resistance R3. And a branch identical to the branch (T5, T6) is provided between terminal C and earth, comprising two transistors T8 and T9. The T8 transistor is mounted as a diode and identical to transistor T5. The transistor T9 is diode mounted and identical to transistor T6. In the example they are all the same type N enriched and of the same geometry (W / L). Which is important in practice is that two by two, T5 and T8, T6 and T9, are identical to have the compensation expected.

Cette branche (T8, T9) sert de limiteur de la tension au noeud C, pour rendre ce noeud moins dépendant des variations de la tension d'alimentation Vdd.This branch (T8, T9) serves as a limiter of the tension at node C, to make this node less dependent on variations in supply voltage Vdd.

Quand le dispositif est mis sous tension, le noeud C suit l'augmentation de la tension d'alimentation par le biais de la résistance R4. Mais dès que le noeud C atteint un potentiel de l'ordre de 2 x Vtn (somme des tensions de seuil des transistors T8 et T9 en série), la branche T8, T9, tend à maintenir ce niveau au noeud C : la tension Vc va alors bouger beaucoup moins, comme montré sur la figure 4. En effet T8 et T9 n'ont pas la résistance R3 dans leur branche, ils vont passer plus de courant (I) que T5 et T6. Ainsi la tension sur cette branche donnée par Vt8+Vt9+Ron.I, où Ron est la résistance passante équivalente des deux transistors, sera toujours légèrement supérieure à Vt5+Vt6 (Vti est la tension de seuil du transistor Ti). C'est ce qui permet d'avoir une tension très faible dans la résistance R3. Ainsi cette régulation de la tension au noeud C de la résistance R3 permet de limiter le courant dans la branche (T5,T6). De cette manière, on a une meilleure régulation de la tension de grille du transistor suiveur T4 et de la tension de drain du transistor T5.When the device is powered up, the node C follows the increase of the supply voltage through the resistor R4. But as soon as node C reaches a potential of the order of 2 x Vt n (sum of the threshold voltages of transistors T8 and T9 in series), the branch T8, T9, tends to maintain this level at node C: the voltage Vc will then move much less, as shown in Figure 4. Indeed T8 and T9 do not have the resistance R3 in their branch, they will pass more current (I) than T5 and T6. Thus the voltage on this branch given by Vt8 + Vt9 + Ron.I, where Ron is the equivalent pass resistance of the two transistors, will always be slightly higher than Vt5 + Vt6 (Vti is the threshold voltage of the transistor Ti). This is what makes it possible to have a very low voltage in the resistor R3. Thus this regulation of the voltage at node C of the resistor R3 makes it possible to limit the current in the branch (T5, T6). In this way, there is better regulation of the gate voltage of the follower transistor T4 and of the drain voltage of the transistor T5.

Le dispositif représenté peut très bien être réalisé en technologie NMOS.The device shown may very well be made in NMOS technology.

Sur la figure 3, on a en outre représenté des transistors de mise sous-tension du dispositif.In Figure 3, there are also shown device energizing transistors.

Dans l'exemple, un transistor T10 de type P permet d'appliquer ou non la tension d'alimentation Vcc au dispositif (signal EN=0), tandis qu'un transistor T11 de type N force la sortie à zéro quand le dispositif doit être hors tension (signal EN=1). Mais ces transistors ne sont pas obligatoires.In the example, a P-type transistor T10 allows whether or not to apply the supply voltage Vcc to the device (signal EN = 0), while a transistor T11 type N forces the output to zero when the device must be de-energized (signal EN = 1). But these transistors are not mandatory.

Avec un dispositif selon l'une quelconque des variantes décrites précédemment, on obtient un courant de référence Ir, duquel on peut obtenir d'autres courants de référence, par des montages en miroir de courant. Un tel montage est par exemple montré sur la figure 2 : un transistor T7 de type N et natif est monté en miroir de courant par rapport au transistor T2 : sa grille est commandée par la grille du transistor T2. Une autre résistance de référence Rr' est connectée au drain du transistor T7 sur une borne. L'autre borne est reliée à la tension d'alimentation Vcc. On utilisera de préférence la même technologie de fabrication pour les résistances de référence. On obtient un courant de référence stable Ir'. Notamment, on a pu vérifier en pratique que l'évolution de la tension au drain du transistor T7 avec la tension d'alimentation Vcc est parfaitement parallèle entre 1.6 et 6 volts. Pour la réalisation pratique du dispositif, il est à noter que l'on choisit de préférence un transistor T7 à canal long, par exemple avec une longueur de canal supérieure à 5 microns en technologie 1 micron, pour s'affranchir des effets de canal court qui nuisent à la stabilité en courant en mode saturé (avec un canal long, le courant de saturation ne dépend plus de la tension drain-source).With a device according to any one of variants described above, we obtain a current Ir, from which we can obtain other reference currents, by mirrored arrangements of current. Such an assembly is for example shown on the Figure 2: an N-type native T7 transistor is mounted in current mirror with respect to transistor T2: its gate is controlled by the gate of transistor T2. Another reference resistance Rr ' is connected to the drain of transistor T7 on one terminal. The other terminal is connected to the supply voltage Vcc. We will preferably use the same technology manufacturing for reference resistors. We obtains a stable reference current Ir '. Especially, we have been able to verify in practice that the evolution of voltage at the drain of transistor T7 with the voltage Vcc supply is perfectly parallel between 1.6 and 6 volts. For the practical realization of the device, it should be noted that one preferably chooses a long channel T7 transistor, for example with a channel length greater than 5 microns in technology 1 micron, to get rid of short channel effects which affect current stability in saturated mode (with a long channel, the saturation current does not depend more than the drain-source voltage).

L'invention vient d'être décrite en choisissant des transistors de types de conductivité particuliers. On peut bien entendu choisir des transistors de types de conductivité inversés, sauf à respecter les différents critères exposés. L'ensemble du schéma se déduit aisément, en inversant les types de conductivité et les polarités dans les schémas des figures 1 à 3.The invention has just been described by choosing transistors of particular conductivity types. We can of course choose transistors of types of reverse conductivity, except to respect the different exposed criteria. The whole scheme is deduced easily, by reversing the types of conductivity and the polarities in the diagrams of Figures 1 to 3.

Le dispositif de référence de courant en circuit intégré selon l'invention offre donc une grande stabilité. Et de par sa conception sans contre-réaction, il est transposable d'une technologie de fabrication à l'autre sans simulations, ce qui n'est pas le moindre de ses avantages.The current reference device in circuit integrated according to the invention therefore offers great stability. And by design without feedback, it can be transposed from a technology of manufacturing to another without simulations, which is not not the least of its advantages.

Claims (10)

  1. Integrated circuit current reference device comprising a reference resistor (Rr), characterised in that it comprises first and second MOS transistors of the same conductivity type, the first one (T1) having its gate and drain connected together to first terminal (A) of the reference resistor, the second one (T2) having its gate and drain connected together to a second terminal (B) of the reference resistor, the first transistor having a threshold voltage higher than that of the second transistor and the two transistors being biased in saturated mode, the source of each of these transistors being biased at the same potential as the substrate or well in which the transistor is produced.
  2. Reference device according to Claim 1, characterised in that it comprises a third MOS transistor (T3) with a threshold voltage higher than that of the first transistor and having its gate connected to its drain, so as to apply, to the first transistor, a biasing current (I1) proportional to the difference between the threshold voltages of the said first and third transistors by means of a biasing resistor (R1) connected between the first and third transistors.
  3. Reference device according to Claim 1, characterised in that the biasing circuit comprises a fourth MOS follower transistor (T4), connected in series with a first resistor (R1) in order to bias the first transistor (T1), the said follower transistor being controlled at its gate by the series connection of fifth and sixth MOS transistors, the fifth transistor (T5) having the same conductivity type and the same threshold voltage as the follower transistor and being connected as a diode, and the sixth MOS transistor (T6) having a threshold voltage higher than that of the first transistor (T1) and being connected as a diode, the two transistors being biased in saturated mode by a second resistor (R3) connected between the drain of the transistor T5 and the supply voltage Vcc.
  4. Device according to Claim 3, characterised in that it comprises a third biasing resistor (R4) interposed between the supply voltage and the second resistor (R3) at a node C and a series connection between this node C and the earth of a seventh transistor (T8) connected as a diode and identical to the fifth transistor (T5) and of an eighth transistor (T9) connected as a diode identical to the sixth transistor (T6).
  5. Device according to any one of Claims 1 to 4, characterised in that the reference resistor (Rr) is produced in a diffusion of the extension drain type.
  6. Device according to any one of Claims 1 to 4, characterised in that the reference resistor (Rr) is produced in a diffusion of the source/drain type.
  7. Device according to Claim 5, characterised in that the biasing resistors (R1, R3, R4) are also produced in a diffusion of the source/drain type.
  8. Device according to any one of the preceding claims, characterised in that it also comprises at least one current mirror structure (T7) with respect to the second transistor (T2) in order to obtain another reference current (Ir') in another reference resistor (Rr').
  9. Device according to Claim 8, characterised in that the other reference resistor is produced in the same technology as the first (Rr).
  10. Device according to Claim 8, characterised in that the transistors (T2, T7) used in the current mirror structure are of the long channel type.
EP97400209A 1996-01-31 1997-01-29 Device for current reference in an integrated circuit Expired - Lifetime EP0788047B1 (en)

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FR9601168A FR2744262B1 (en) 1996-01-31 1996-01-31 INTEGRATED CIRCUIT CURRENT REFERENCE DEVICE
FR9601168 1996-01-31
FR9607705A FR2744263B3 (en) 1996-01-31 1996-06-20 INTEGRATED CIRCUIT CURRENT REFERENCE DEVICE
FR9607705 1996-06-20

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Also Published As

Publication number Publication date
DE69700031D1 (en) 1998-11-12
FR2744263A1 (en) 1997-08-01
FR2744263B3 (en) 1998-03-27
EP0788047A1 (en) 1997-08-06
DE69700031T2 (en) 1999-02-25
US5903141A (en) 1999-05-11

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