EP1472737A1 - Cellule dram a 1 transistor sans condensateur et procede de production correspondant - Google Patents

Cellule dram a 1 transistor sans condensateur et procede de production correspondant

Info

Publication number
EP1472737A1
EP1472737A1 EP03737236A EP03737236A EP1472737A1 EP 1472737 A1 EP1472737 A1 EP 1472737A1 EP 03737236 A EP03737236 A EP 03737236A EP 03737236 A EP03737236 A EP 03737236A EP 1472737 A1 EP1472737 A1 EP 1472737A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor material
dielectric
dielectric material
regions
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03737236A
Other languages
German (de)
English (en)
Inventor
Josef Willer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda Flash GmbH
Original Assignee
Qimonda Flash GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qimonda Flash GmbH filed Critical Qimonda Flash GmbH
Publication of EP1472737A1 publication Critical patent/EP1472737A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate

Definitions

  • the present invention relates to a capacitor-free 1-transistor DRAM cell, hereinafter simply referred to as a 1-transistor DRAM cell, and an associated production method.
  • channel region that is not set to a defined potential and that forms a zone that is completely or at least partially depleted of charge carriers during operation of the cell (partially to fully depleted floating body).
  • gate electrode separated from the channel area by a gate dielectric.
  • the MOS transistor structure designed in this way is suitable for storing the charge, which represents a bit.
  • Disadvantages of this embodiment are the use of a comparatively expensive SOI substrate and the necessary compromise between the desired small space requirement of the cell and the gate length that can be realized.
  • the object of the present invention is to provide a space-saving and inexpensive to produce 1-transistor DRAM cell. with which a memory cell array can be produced.
  • the channel region and the source-drain regions are arranged vertically on an edge of a dielectric trench filling.
  • the semiconductor material is delimited by the gate dielectric and the gate electrode arranged above it.
  • the gate electrode is arranged in a recess in the semiconductor material.
  • a memory cell array composed of such 1-transistor DRAM cells comprises in a semiconductor chip a multiplicity of vertically aligned strip-shaped semiconductor regions, in which source-drain regions are implanted in each case in an upper and lower portion and in the middle region in between an undefined potential channel area is present, which is embedded on all sides in a cutting plane coplanar to the plane of the upper side of the semiconductor chip in insulating material.
  • the plane of the upper side of the semiconductor chip is to be understood as a plane that is coplanar with a cell-provided, at least originally flat upper side of an arm used in the manufacture or with the layers of a grown layer structure or applied passivation.
  • FIG. 0 shows an arrangement of the word lines and bit lines of a memory cell array in supervision.
  • Figures 1, 2, 5, 6, and 7 show cross sections through intermediate products of a manufacturing process.
  • Figures 3 and 4 show views of the memory cell array after various steps in the manufacturing process.
  • FIG. 8 shows a cross section through an intermediate product of an alternative manufacturing process.
  • FIG. 0 shows the alignment of the word lines WLj in a schematic view of a memory cell array. x , WL j , WL j + 1 and the bit lines BLi, BLi + i running across them. The positions of two cross sections A and B are also drawn in with dashed lines; these positions correspond to the positions of the cross sections of FIGS. 5 and 6 to be explained below.
  • a cross-point DRAM architecture as shown in FIG. 0 requires an area of 4F 2 per cell.
  • the structure of the cells is explained below using preferred manufacturing processes.
  • the manufacturing process preferably begins with process steps which are known per se from semiconductor technology.
  • a layer as pad oxide 2 and a layer as pad nitride 3 are first applied in the usual way to a semiconductor body 1 or a substrate.
  • trenches that are aligned parallel to one another are then produced in the manner of an STI (shallow trench isolation).
  • STI shallow trench isolation
  • the trenches are filled with an oxide or another dielectric material 4. If necessary, close suitable measures for planarization, such as B. CMP (chemical mechanical polishing).
  • the p-wells and n-wells for CMOS components of the control peripherals are preferably also produced. As usual, this can be done by implanting boron or phosphorus and healing the implants.
  • the dielectric material 4 in the trenches is removed in the upper region of the trenches, so that an electrically conductive layer 5 can be introduced there up to the upper edge of the trenches.
  • These electrically conductive layers 5, which each run in strips in the trenches, are laterally in contact with the semiconductor material of the semiconductor body 1 or substrate.
  • polysilicon is used for the electrically conductive layers 5 and this polysilicon is slightly oxidized on the top of the layers, the volume of the layer portion 6 concerned increasing. An oxide mask is formed in this way.
  • the nitride of the pad nitride layer 3 is then removed. The etching attack can be partially protected with photomask technology, which is particularly useful in the area of the control periphery.
  • Spacers of a mask for self-aligned structuring of the active trenches to be subsequently produced are preferably produced by means of a renewed deposition of nitride or TEOS.
  • These active trenches are intended, on the one hand, to limit the semiconductor material on the flanks of the trench fillings made of dielectric material 4 and, on the other hand, to accommodate the gate electrodes required for driving the channel regions.
  • an n + implantation for example using arsenic
  • an implantation of phosphorus can also be used to produce an LDD (lightly doped drain).
  • LDD lightly doped drain
  • the lower limit 12 of the upper source-drain regions 10 and the lower limit 13 of the lower source-drain regions 9 are shown in dashed lines.
  • the lower limit 13 of the implantation introduced for the lower source-drain regions 9 is preferably so deep that a continuous lower source-drain region 9 is designed in the manner of a ground plate. However, it may also be sufficient to insert the implantation in question only approximately up to the dashed line 13a shown as an alternative.
  • the upper limit 14 of the lower source-drain region 9 and the lower limit 12 of the upper source-drain region 10 enclose the respective channel region 11. In the manufacture of the lower doped regions 9, this channel region 11 is z. B.
  • strip-shaped photoresist masks 15 are then applied to the top in order to first remove the insulating material present on the top, in particular the layer portion 6, preferably produced by oxidation of polysilicon, and then the electrically conductive hige layer 5 and to remove the semiconductor material of the semiconductor body 1 in the areas between the strips of the photoresist mask.
  • the lateral boundaries of the upper source-drain regions 10 are also shown in dashed lines as hidden contours.
  • FIG. 4 shows the top view according to FIG. 3 after the strip-shaped mask of the layer portion 6 made of oxidized polysilicon or another material has been removed in this area and the walls of the now enlarged recesses 8 between the trench fillings and the surface of the semiconductor material a thin dielectric layer 18, preferably an oxide layer, was coated on the flanks of the trench fillings.
  • This dielectric layer 18 is provided as a gate dielectric on the semiconductor material on the flanks of the trench fillings.
  • the gate electrodes 16 are made in the recesses so that they partially overlap a trench filling.
  • the gate electrodes 16 are covered on both sides with respect to their longitudinal directions with insulating spacer elements 17.
  • the electrically conductive layers 5 are removed in the area between the strips of the photoresist mask 15, so that a conductive connection between the areas of the individual cells is only present in the bottom area of the trenches.
  • FIG. 5 This structure is shown in FIG. 5 in a cross section, which assumes the position of cross section A in FIG. 0, although FIG. 5 only shows an intermediate product in which the bit lines have not yet been produced.
  • the two gate electrodes 16 are for the two opposite flanks of the dielectric material 4 arranged channel regions 11 are provided, each in the active trenches produced between the trench fillings are arranged electrically separated from one another.
  • the sides of the gate electrodes 16 are with the spacers 17, z. B. isolated from nitride.
  • a strip-shaped layer 19 made of polysilicon, tungsten or tungsten silicide and a hard mask layer 20 for structuring the gate electrodes can also be applied to the gate electrodes 16.
  • FIG. 6 A cross section through the memory cell array in the position of section B shown in FIG. 0 is shown in FIG. 6 for this intermediate product. It can be seen there that the material of the gate electrodes 16 is also present in the area between the individual memory cells in the longitudinal direction of the trenches and is structured there in the same way.
  • the stripe-shaped structured gate electrodes 16 thus form the word lines, each of which connects a stripe of memory cells arranged along a trench filling.
  • the electrically conductive layer 5 is absent in the areas between the individual memory cells.
  • the portions of semiconductor material on the flanks of the regions made of dielectric material 4 are missing between the individual memory cells.
  • the source-drain regions and channel regions of the individual cells are thus interrupted in the longitudinal direction of the word lines and are thus limited to the individual cells.
  • a first passivation (preferably a nitride) is deposited, and the remaining openings are filled with an insulation layer 21 (preferably BPSG [borophosphosilicate glass]).
  • These method steps also include opening at least partially self-aligned contact holes in connection with the bit lines 22 to be produced.
  • the bit lines 22 are on the electrically conductive layers 5 applied and contacted, so that here an electrically conductive connection to the upper source-drain regions 10 is made.
  • contact holes filled with polysilicon in connection with aluminum conductor tracks or to use a copper-based metallization scheme which is also known per se.
  • FIG. 8 shows an alternative exemplary embodiment in cross section, in which the dielectric layer 18 provided for the gate dielectric is removed in the region between the gate electrodes 16. Boundaries 24 of the lower source-drain regions 9, which are continuous here as a grounding plate, are thus exposed there. Contact hole fillings 23, 25 for the electrically conductive layers 5 or these exposed interfaces 24 of the lower source-drain regions 9 are introduced into the corresponding openings above them.
  • the material of the contact hole fillings comes e.g. B. polysilicon in question. This material is leveled at the top and structured with a suitable photo mask technique as required.
  • the bit lines are then produced (not shown in FIG. 8) and run transverse to the word lines.
  • bit lines are applied to the contact hole fillings 25 of the grounding plate in an electrically insulated manner and structured in strips in such a way that the electrically conductive layers 5 of the cells are connected.
  • any number of similar conductor strips with contact on the relevant contact hole fillings 25 for connecting the grounding plate can be produced between the bit lines and in parallel therewith.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Selon l'invention, la zone de canal (11) et les zones de source et de drain (9, 10) sont disposées verticalement au niveau d'un flanc de remplissage de tranchée (4) diélectrique. Sur la face opposée, le matériau semi-conducteur est délimité par le diélectrique de grille (18) et par l'électrode de grille (16) qui est disposée dans un évidement pratiqué dans le matériau semi-conducteur. Un champ de cellules de mémoire comprend une pluralité de zones semi-conductrices striées, dirigées verticalement, dans lesquelles sont implantées en haut et en bas, des zones de source et de drain, entre lesquelles se trouve une zone de canal noyée de tous côtés dans un matériau isolant et se présentant sous forme de corps flottant.
EP03737236A 2002-02-06 2003-01-23 Cellule dram a 1 transistor sans condensateur et procede de production correspondant Withdrawn EP1472737A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10204871 2002-02-06
DE10204871A DE10204871A1 (de) 2002-02-06 2002-02-06 Kondensatorlose 1-Transistor-DRAM-Zelle und Herstellungsverfahren
PCT/DE2003/000181 WO2003067661A1 (fr) 2002-02-06 2003-01-23 Cellule dram a 1 transistor sans condensateur et procede de production correspondant

Publications (1)

Publication Number Publication Date
EP1472737A1 true EP1472737A1 (fr) 2004-11-03

Family

ID=27618354

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03737236A Withdrawn EP1472737A1 (fr) 2002-02-06 2003-01-23 Cellule dram a 1 transistor sans condensateur et procede de production correspondant

Country Status (8)

Country Link
US (2) US7034336B2 (fr)
EP (1) EP1472737A1 (fr)
JP (1) JP2005517299A (fr)
KR (1) KR100649782B1 (fr)
CN (1) CN100359695C (fr)
DE (1) DE10204871A1 (fr)
TW (1) TWI230455B (fr)
WO (1) WO2003067661A1 (fr)

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US20060177980A1 (en) 2006-08-10
WO2003067661A1 (fr) 2003-08-14
TWI230455B (en) 2005-04-01
US7341904B2 (en) 2008-03-11
CN100359695C (zh) 2008-01-02
US7034336B2 (en) 2006-04-25
CN1628386A (zh) 2005-06-15
TW200304217A (en) 2003-09-16
KR100649782B1 (ko) 2006-11-27
KR20040086345A (ko) 2004-10-08
JP2005517299A (ja) 2005-06-09
US20050064659A1 (en) 2005-03-24

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