EP1472737A1 - Capacitor-less 1-transistor dram cell and method for producing the same - Google Patents

Capacitor-less 1-transistor dram cell and method for producing the same

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Publication number
EP1472737A1
EP1472737A1 EP03737236A EP03737236A EP1472737A1 EP 1472737 A1 EP1472737 A1 EP 1472737A1 EP 03737236 A EP03737236 A EP 03737236A EP 03737236 A EP03737236 A EP 03737236A EP 1472737 A1 EP1472737 A1 EP 1472737A1
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EP
European Patent Office
Prior art keywords
semiconductor material
dielectric
dielectric material
regions
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP03737236A
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German (de)
French (fr)
Inventor
Josef Willer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda Flash GmbH
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Qimonda Flash GmbH
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Publication date
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Publication of EP1472737A1 publication Critical patent/EP1472737A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate

Definitions

  • the present invention relates to a capacitor-free 1-transistor DRAM cell, hereinafter simply referred to as a 1-transistor DRAM cell, and an associated production method.
  • channel region that is not set to a defined potential and that forms a zone that is completely or at least partially depleted of charge carriers during operation of the cell (partially to fully depleted floating body).
  • gate electrode separated from the channel area by a gate dielectric.
  • the MOS transistor structure designed in this way is suitable for storing the charge, which represents a bit.
  • Disadvantages of this embodiment are the use of a comparatively expensive SOI substrate and the necessary compromise between the desired small space requirement of the cell and the gate length that can be realized.
  • the object of the present invention is to provide a space-saving and inexpensive to produce 1-transistor DRAM cell. with which a memory cell array can be produced.
  • the channel region and the source-drain regions are arranged vertically on an edge of a dielectric trench filling.
  • the semiconductor material is delimited by the gate dielectric and the gate electrode arranged above it.
  • the gate electrode is arranged in a recess in the semiconductor material.
  • a memory cell array composed of such 1-transistor DRAM cells comprises in a semiconductor chip a multiplicity of vertically aligned strip-shaped semiconductor regions, in which source-drain regions are implanted in each case in an upper and lower portion and in the middle region in between an undefined potential channel area is present, which is embedded on all sides in a cutting plane coplanar to the plane of the upper side of the semiconductor chip in insulating material.
  • the plane of the upper side of the semiconductor chip is to be understood as a plane that is coplanar with a cell-provided, at least originally flat upper side of an arm used in the manufacture or with the layers of a grown layer structure or applied passivation.
  • FIG. 0 shows an arrangement of the word lines and bit lines of a memory cell array in supervision.
  • Figures 1, 2, 5, 6, and 7 show cross sections through intermediate products of a manufacturing process.
  • Figures 3 and 4 show views of the memory cell array after various steps in the manufacturing process.
  • FIG. 8 shows a cross section through an intermediate product of an alternative manufacturing process.
  • FIG. 0 shows the alignment of the word lines WLj in a schematic view of a memory cell array. x , WL j , WL j + 1 and the bit lines BLi, BLi + i running across them. The positions of two cross sections A and B are also drawn in with dashed lines; these positions correspond to the positions of the cross sections of FIGS. 5 and 6 to be explained below.
  • a cross-point DRAM architecture as shown in FIG. 0 requires an area of 4F 2 per cell.
  • the structure of the cells is explained below using preferred manufacturing processes.
  • the manufacturing process preferably begins with process steps which are known per se from semiconductor technology.
  • a layer as pad oxide 2 and a layer as pad nitride 3 are first applied in the usual way to a semiconductor body 1 or a substrate.
  • trenches that are aligned parallel to one another are then produced in the manner of an STI (shallow trench isolation).
  • STI shallow trench isolation
  • the trenches are filled with an oxide or another dielectric material 4. If necessary, close suitable measures for planarization, such as B. CMP (chemical mechanical polishing).
  • the p-wells and n-wells for CMOS components of the control peripherals are preferably also produced. As usual, this can be done by implanting boron or phosphorus and healing the implants.
  • the dielectric material 4 in the trenches is removed in the upper region of the trenches, so that an electrically conductive layer 5 can be introduced there up to the upper edge of the trenches.
  • These electrically conductive layers 5, which each run in strips in the trenches, are laterally in contact with the semiconductor material of the semiconductor body 1 or substrate.
  • polysilicon is used for the electrically conductive layers 5 and this polysilicon is slightly oxidized on the top of the layers, the volume of the layer portion 6 concerned increasing. An oxide mask is formed in this way.
  • the nitride of the pad nitride layer 3 is then removed. The etching attack can be partially protected with photomask technology, which is particularly useful in the area of the control periphery.
  • Spacers of a mask for self-aligned structuring of the active trenches to be subsequently produced are preferably produced by means of a renewed deposition of nitride or TEOS.
  • These active trenches are intended, on the one hand, to limit the semiconductor material on the flanks of the trench fillings made of dielectric material 4 and, on the other hand, to accommodate the gate electrodes required for driving the channel regions.
  • an n + implantation for example using arsenic
  • an implantation of phosphorus can also be used to produce an LDD (lightly doped drain).
  • LDD lightly doped drain
  • the lower limit 12 of the upper source-drain regions 10 and the lower limit 13 of the lower source-drain regions 9 are shown in dashed lines.
  • the lower limit 13 of the implantation introduced for the lower source-drain regions 9 is preferably so deep that a continuous lower source-drain region 9 is designed in the manner of a ground plate. However, it may also be sufficient to insert the implantation in question only approximately up to the dashed line 13a shown as an alternative.
  • the upper limit 14 of the lower source-drain region 9 and the lower limit 12 of the upper source-drain region 10 enclose the respective channel region 11. In the manufacture of the lower doped regions 9, this channel region 11 is z. B.
  • strip-shaped photoresist masks 15 are then applied to the top in order to first remove the insulating material present on the top, in particular the layer portion 6, preferably produced by oxidation of polysilicon, and then the electrically conductive hige layer 5 and to remove the semiconductor material of the semiconductor body 1 in the areas between the strips of the photoresist mask.
  • the lateral boundaries of the upper source-drain regions 10 are also shown in dashed lines as hidden contours.
  • FIG. 4 shows the top view according to FIG. 3 after the strip-shaped mask of the layer portion 6 made of oxidized polysilicon or another material has been removed in this area and the walls of the now enlarged recesses 8 between the trench fillings and the surface of the semiconductor material a thin dielectric layer 18, preferably an oxide layer, was coated on the flanks of the trench fillings.
  • This dielectric layer 18 is provided as a gate dielectric on the semiconductor material on the flanks of the trench fillings.
  • the gate electrodes 16 are made in the recesses so that they partially overlap a trench filling.
  • the gate electrodes 16 are covered on both sides with respect to their longitudinal directions with insulating spacer elements 17.
  • the electrically conductive layers 5 are removed in the area between the strips of the photoresist mask 15, so that a conductive connection between the areas of the individual cells is only present in the bottom area of the trenches.
  • FIG. 5 This structure is shown in FIG. 5 in a cross section, which assumes the position of cross section A in FIG. 0, although FIG. 5 only shows an intermediate product in which the bit lines have not yet been produced.
  • the two gate electrodes 16 are for the two opposite flanks of the dielectric material 4 arranged channel regions 11 are provided, each in the active trenches produced between the trench fillings are arranged electrically separated from one another.
  • the sides of the gate electrodes 16 are with the spacers 17, z. B. isolated from nitride.
  • a strip-shaped layer 19 made of polysilicon, tungsten or tungsten silicide and a hard mask layer 20 for structuring the gate electrodes can also be applied to the gate electrodes 16.
  • FIG. 6 A cross section through the memory cell array in the position of section B shown in FIG. 0 is shown in FIG. 6 for this intermediate product. It can be seen there that the material of the gate electrodes 16 is also present in the area between the individual memory cells in the longitudinal direction of the trenches and is structured there in the same way.
  • the stripe-shaped structured gate electrodes 16 thus form the word lines, each of which connects a stripe of memory cells arranged along a trench filling.
  • the electrically conductive layer 5 is absent in the areas between the individual memory cells.
  • the portions of semiconductor material on the flanks of the regions made of dielectric material 4 are missing between the individual memory cells.
  • the source-drain regions and channel regions of the individual cells are thus interrupted in the longitudinal direction of the word lines and are thus limited to the individual cells.
  • a first passivation (preferably a nitride) is deposited, and the remaining openings are filled with an insulation layer 21 (preferably BPSG [borophosphosilicate glass]).
  • These method steps also include opening at least partially self-aligned contact holes in connection with the bit lines 22 to be produced.
  • the bit lines 22 are on the electrically conductive layers 5 applied and contacted, so that here an electrically conductive connection to the upper source-drain regions 10 is made.
  • contact holes filled with polysilicon in connection with aluminum conductor tracks or to use a copper-based metallization scheme which is also known per se.
  • FIG. 8 shows an alternative exemplary embodiment in cross section, in which the dielectric layer 18 provided for the gate dielectric is removed in the region between the gate electrodes 16. Boundaries 24 of the lower source-drain regions 9, which are continuous here as a grounding plate, are thus exposed there. Contact hole fillings 23, 25 for the electrically conductive layers 5 or these exposed interfaces 24 of the lower source-drain regions 9 are introduced into the corresponding openings above them.
  • the material of the contact hole fillings comes e.g. B. polysilicon in question. This material is leveled at the top and structured with a suitable photo mask technique as required.
  • the bit lines are then produced (not shown in FIG. 8) and run transverse to the word lines.
  • bit lines are applied to the contact hole fillings 25 of the grounding plate in an electrically insulated manner and structured in strips in such a way that the electrically conductive layers 5 of the cells are connected.
  • any number of similar conductor strips with contact on the relevant contact hole fillings 25 for connecting the grounding plate can be produced between the bit lines and in parallel therewith.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to a capacitor-less 1-transistor dram cell, wherein a channel region (11) and the source/drain region (9, 10) are disposed vertically on a flank of a dielectric trench fill (4). On the opposite side, the semiconductor material is limited by the gate dielectric (18) and the gate electrode (16) that is disposed in a recess of the semiconductor material. A memory cell array comprises a plurality of vertically aligned strip-shaped semiconductor regions in which source/drain regions are implanted at the top and at the bottom, and in between which a channel region which is fully embedded in an insulating material is disposed as a floating body.

Description

Beschreibungdescription
Kondensatorlose 1-Transistor-DRAM-Zelle und HerstellungsverfahrenCapacitorless 1-transistor DRAM cell and manufacturing process
Die vorliegende Erfindung betrifft eine kondensatorlose 1-Transistor-DRAM-Zelle, im Folgenden einfach als 1-Transis- tor-DRAM-Zelle bezeichnet, und ein zugehöriges Herstellungsverfahren.The present invention relates to a capacitor-free 1-transistor DRAM cell, hereinafter simply referred to as a 1-transistor DRAM cell, and an associated production method.
Von S. Okhonin, M. Nagoga, J. M. Sallese und P. Fazan von der Ecole Polytechnique Federale de Lausanne (Preprint und Präsentation auf der IEEE-SOI-Konferenz, ISS/EPFL 2001) wurde eine Ausführung von DRAM-Zellen im Sub-lOOnm-Bereich vorge- schlagen, bei der die Speicherzelle als Transistorstruktur in der Body-Siliziumschicht eines SOI-Substrates angeordnet ist. Dieses Konzept verzichtet auf eine Ausbildung eines eigens für jede Zelle vorgesehenen Kondensators. Das Halbleitermaterial, das den Source-Bereich, den Kanalbereich und den Drain- Bereich umfasst, ist hier allseits von Si02 als elektrisch isolierendem Material eingeschlossen. Es ist so ein nicht auf definiertes Potential gelegter Kanalbereich vorhanden, der im Betrieb der Zelle eine vollständig oder zumindest teilweise an Ladungsträgern verarmte Zone bildet (partially to fully depleted floating body) . Auf der Oberseite befindet sich eine von dem Kanalbereich durch ein Gate-Dielektrikum getrennte Gateelektrode .S. Okhonin, M. Nagoga, JM Sallese and P. Fazan of the Ecole Polytechnique Federale de Lausanne (preprint and presentation at the IEEE-SOI conference, ISS / EPFL 2001) developed a DRAM cell version in the sub-100m - Proposed area in which the memory cell is arranged as a transistor structure in the body silicon layer of an SOI substrate. This concept dispenses with the formation of a capacitor provided specifically for each cell. The semiconductor material, which comprises the source region, the channel region and the drain region, is enclosed here on all sides by SiO 2 as an electrically insulating material. There is a channel region that is not set to a defined potential and that forms a zone that is completely or at least partially depleted of charge carriers during operation of the cell (partially to fully depleted floating body). On the top there is a gate electrode separated from the channel area by a gate dielectric.
Die so ausgebildete MOS-Transistorstruktur ist zur Speiche- rung der Ladung geeignet, die ein Bit darstellt. Nachteile dieser Ausführung sind die Verwendung eines vergleichsweise teuren SOI-Substrates und der notwendige Kompromiss zwischen einem angestrebten geringen Platzbedarf der Zelle und der realisierbaren Gatelänge.The MOS transistor structure designed in this way is suitable for storing the charge, which represents a bit. Disadvantages of this embodiment are the use of a comparatively expensive SOI substrate and the necessary compromise between the desired small space requirement of the cell and the gate length that can be realized.
Aufgabe der vorliegenden Erfindung ist es, eine platzsparende und kostengünstig herstellbare 1-Transistor-DRAM-Zelle anzu- geben, mit der ein Speicherzellenfeld hergestellt werden kann.The object of the present invention is to provide a space-saving and inexpensive to produce 1-transistor DRAM cell. with which a memory cell array can be produced.
Diese Aufgabe wird mit der 1-Transistor-DRAM-Zelle mit den Merkmalen des Anspruches 1, mit der Anordnung aus 1 -Transistor-DRAM-Zellen mit den Merkmalen des Anspruches 4 bzw. mit dem Verfahren mit den Merkmalen des Anspruches 7 gelöst. Ausgestaltungen ergeben sich aus den jeweiligen abhängigen Ansprüchen.This object is achieved with the 1-transistor DRAM cell with the features of claim 1, with the arrangement of 1-transistor DRAM cells with the features of claim 4 or with the method with the features of claim 7. Refinements result from the respective dependent claims.
Bei der (kondensatorlosen) 1-Transistor-DRAM-Zelle sind der Kanalbereich und die Source-Drain-Bereiche vertikal an einer Flanke einer dielektrischen Grabenfüllung angeordnet. Auf der der Grabenfüllung gegenüberliegenden Seite ist das Halblei - termaterial durch das Gate-Dielektrikum und die darüber angeordnete Gateelektrode begrenzt. Die Gateelektrode ist in einer Aussparung des Halbleitermateriales angeordnet.In the (capacitorless) 1-transistor DRAM cell, the channel region and the source-drain regions are arranged vertically on an edge of a dielectric trench filling. On the side opposite the trench filling, the semiconductor material is delimited by the gate dielectric and the gate electrode arranged above it. The gate electrode is arranged in a recess in the semiconductor material.
Ein Speicherzellenfeld aus derartigen 1-Transistor-DRAM- Zellen umfasst in einem Halbleiterchip eine Vielzahl von vertikal ausgerichteten streifenförmigen Halbleiterbereichen, in denen jeweils in einem oberen und unteren Anteil Source- Drain-Bereiche implantiert sind und in dem mittleren Bereich dazwischen ein nicht auf definiertes Potential gelegter Ka- nalbereich vorhanden ist, der in einer zu der Ebene der Oberseite des Halbleiterchips koplanaren Schnittebene allseits in isolierendes Material eingebettet ist. Dabei ist als Ebene der Oberseite des Halbleiterchips eine Ebene zu verstehen, die koplanar ist zu einer mit den Zellen versehenen, zumin- dest ursprünglich ebenen Oberseite eines bei der Herstellung verwendeten afers oder zu den Ebenen einer aufgewachsenen Schichtstruktur oder aufgebrachten Passivierung .A memory cell array composed of such 1-transistor DRAM cells comprises in a semiconductor chip a multiplicity of vertically aligned strip-shaped semiconductor regions, in which source-drain regions are implanted in each case in an upper and lower portion and in the middle region in between an undefined potential channel area is present, which is embedded on all sides in a cutting plane coplanar to the plane of the upper side of the semiconductor chip in insulating material. The plane of the upper side of the semiconductor chip is to be understood as a plane that is coplanar with a cell-provided, at least originally flat upper side of an arm used in the manufacture or with the layers of a grown layer structure or applied passivation.
Es folgt eine genauere Beschreibung von Beispielen der 1- Transistor-DRAM-Zelle und bevorzugter Herstellungsverfahren anhand der Figuren 0 bis 8. Die Figur 0 zeigt eine Anordnung der Wortleitungen und Bit- leitungen eines Speicherzellenfeldes in Aufsicht.The following is a more detailed description of examples of the 1-transistor DRAM cell and preferred production methods using FIGS. 0 to 8. FIG. 0 shows an arrangement of the word lines and bit lines of a memory cell array in supervision.
Die Figuren 1, 2, 5, 6, und 7 zeigen Querschnitte durch Zwi- schenprodukte eines Herstellungsverfahrens.Figures 1, 2, 5, 6, and 7 show cross sections through intermediate products of a manufacturing process.
Die Figuren 3 und 4 zeigen Aufsichten auf das Speicherzellenfeld nach verschiedenen Schritten des Herstellungsverfahrens.Figures 3 and 4 show views of the memory cell array after various steps in the manufacturing process.
Die Figur 8 zeigt einen Querschnitt durch ein Zwischenprodukt eines alternativen Herstellungsverfahrens.FIG. 8 shows a cross section through an intermediate product of an alternative manufacturing process.
In der Figur 0 ist in einer schematisierten Aufsicht auf ein Speicherzellenfeld die Ausrichtung der Wortleitungen WLj.x, WLj, WLj+1 und der darüber quer verlaufend geführten Bitleitun- gen BLi, BLi+i dargestellt. Mit gestrichelten Linien sind noch die Positionen zweier Querschnitte A und B eingezeichnet; diese Positionen entsprechen den Positionen der Querschnitte der nachfolgend zu erläuternden Figuren 5 und 6. Eine Cross- Point-DRAM-Architektur gemäß der Darstellung der Figur 0 kommt mit einem Flächenbedarf von 4F2 pro Zelle aus.FIG. 0 shows the alignment of the word lines WLj in a schematic view of a memory cell array. x , WL j , WL j + 1 and the bit lines BLi, BLi + i running across them. The positions of two cross sections A and B are also drawn in with dashed lines; these positions correspond to the positions of the cross sections of FIGS. 5 and 6 to be explained below. A cross-point DRAM architecture as shown in FIG. 0 requires an area of 4F 2 per cell.
Die Struktur der Zellen wird im Folgenden anhand bevorzugter Herstellungsverfahren erläutert. Der Herstellungsprozess be- ginnt vorzugsweise mit Verfahrensschritten, die an sich aus der Halbleitertechnologie bekannt sind. Gemäß dem in der Figur 1 dargestellten Querschnitt werden auf einem Halbleiterkörper 1 oder einem Substrat zunächst in der üblichen Weise eine Schicht als Padoxid 2 und eine Schicht als Padnitrid 3 aufgebracht. Es werden dann mittels einer geeigneten Fotomaskentechnik Gräben, die parallel zueinander ausgerichtet sind, nach Art einer STI (shallow trench isolation) hergestellt. Dazu wird das Halbleitermaterial im Bereich der Maskenöffnungen ausgeätzt.The structure of the cells is explained below using preferred manufacturing processes. The manufacturing process preferably begins with process steps which are known per se from semiconductor technology. According to the cross section shown in FIG. 1, a layer as pad oxide 2 and a layer as pad nitride 3 are first applied in the usual way to a semiconductor body 1 or a substrate. Using a suitable photo mask technique, trenches that are aligned parallel to one another are then produced in the manner of an STI (shallow trench isolation). For this purpose, the semiconductor material in the area of the mask openings is etched out.
Die Gräben werden mit einem Oxid oder einem anderen dielektrischen Material 4 gefüllt. Gegebenenfalls schließen sich geeignete Maßnahmen zur Planarisierung, wie z. B. CMP (chemi- cal mechanical polishing) an. Es werden vorzugsweise noch die p-Wannen und n-Wannen für CMOS-Bauelemente der Ansteuerperipherie hergestellt. Das kann wie üblich durch Bor- bzw. Phos- phorimplantation und Ausheilung der Implantate geschehen.The trenches are filled with an oxide or another dielectric material 4. If necessary, close suitable measures for planarization, such as B. CMP (chemical mechanical polishing). The p-wells and n-wells for CMOS components of the control peripherals are preferably also produced. As usual, this can be done by implanting boron or phosphorus and healing the implants.
Das dielektrische Material 4 in den Gräben wird im oberen Bereich der Gräben entfernt, so dass dort jeweils eine elektrisch leitfähige Schicht 5 bis zum oberen Rand der Gräben eingebracht werden kann. Diese jeweils streifenförmig in den Gräben verlaufenden elektrisch leitfähigen Schichten 5 stehen seitlich mit dem Halbleitermaterial des Halbleiterkörpers 1 oder Substrates in Kontakt. Für die nachfolgenden Verfahrens- schritte ist es zweckmäßig, wenn für die elektrisch leitfähi- gen Schichten 5 Polysilizium verwendet wird und dieses Polysilizium an der Oberseite der Schichten etwas oxidiert wird, wobei sich das Volumen des betreffenden Schichtanteiles 6 vergrößert. Auf diese Weise wird eine Oxidmaske ausgebildet. Es wird dann das Nitrid der Padnitridschicht 3 entfernt. Der Ätzangriff kann teilweise mit Fotomaskentechnik geschützt sein, was insbesondere im Bereich der Ansteuerperipherie nützlich ist.The dielectric material 4 in the trenches is removed in the upper region of the trenches, so that an electrically conductive layer 5 can be introduced there up to the upper edge of the trenches. These electrically conductive layers 5, which each run in strips in the trenches, are laterally in contact with the semiconductor material of the semiconductor body 1 or substrate. For the subsequent method steps, it is expedient if polysilicon is used for the electrically conductive layers 5 and this polysilicon is slightly oxidized on the top of the layers, the volume of the layer portion 6 concerned increasing. An oxide mask is formed in this way. The nitride of the pad nitride layer 3 is then removed. The etching attack can be partially protected with photomask technology, which is particularly useful in the area of the control periphery.
Vorzugsweise mittels einer erneuten Abscheidung von Nitrid oder TEOS werden Distanzelemente (spacer) einer Maske für eine selbstjustierte Strukturierung der nachfolgend herzustellenden aktiven Gräben hergestellt. Diese aktiven Gräben sind dafür vorgesehen, zum einen das Halbleitermaterial an den Flanken der Grabenfüllungen aus dielektrischem Material 4 zu begrenzen und zum anderen die für die Ansteuerung der Kanal - bereiche erforderlichen Gateelektroden aufzunehmen.Spacers of a mask for self-aligned structuring of the active trenches to be subsequently produced are preferably produced by means of a renewed deposition of nitride or TEOS. These active trenches are intended, on the one hand, to limit the semiconductor material on the flanks of the trench fillings made of dielectric material 4 and, on the other hand, to accommodate the gate electrodes required for driving the channel regions.
Für die bezüglich des Halbleiterkörpers oder Substrates oberen Source-Drain-Bereiche wird zunächst eine n+- Implantation (z. B. mittels Arsen) eingebracht; gegebenenfalls kann mit einer Implantation von Phosphor noch ein LDD (lightly doped drain) hergestellt werden. Entsprechend der Darstellung in Figur 2 ergibt sich so die Struktur, bei der unter den Distanzelementen 7 das Halbleitermaterial stehen geblieben ist und zwischen diesen Anteilen des Halbleitermaterials an den Flanken zweier gegenüberliegender Grabenfüllungen die Aussparung 8 vorhanden ist. In den jeweiligen oberen Anteilen sind durch die Implantation die oberen Source-Drain-Bereiche 10 ausgebildet. Es werden dann noch entsprechende Implantationen für die unteren Source- Drain-Bereiche 9 eingebracht.For the upper source-drain regions with respect to the semiconductor body or substrate, an n + implantation (for example using arsenic) is first introduced; if necessary, an implantation of phosphorus can also be used to produce an LDD (lightly doped drain). According to the illustration in FIG. 2, the structure thus results in which the semiconductor material has remained under the spacer elements 7 and the recess 8 is present between these portions of the semiconductor material on the flanks of two opposite trench fillings. The upper source-drain regions 10 are formed in the respective upper portions by the implantation. Appropriate implantations for the lower source-drain regions 9 are then introduced.
Die untere Grenze 12 der oberen Source-Drain-Bereiche 10 und die untere Grenze 13 der unteren Source-Drain-Bereiche 9 sind gestrichelt eingezeichnet. Die untere Grenze 13 der für die unteren Source-Drain-Bereiche 9 eingebrachten Implantation ist vorzugsweise so tief vorhanden, dass ein durchgehender unterer Source-Drain-Bereich 9 nach Art einer Erdungsplatte (ground plate) ausgebildet ist. Es mag aber auch genügen, die betreffende Implantation nur etwa bis zu der als Alternative eingezeichneten gestrichelten Linie 13a einzubringen. Die obere Grenze 14 des unteren Source-Drain-Bereiches 9 und die untere Grenze 12 des oberen Source-Drain-Bereiches 10 schließen den jeweiligen Kanalbereich 11 ein. Bei der Herstellung der unteren dotierten Bereiche 9 wird dieser Kanalbereich 11 z. B. durch vorheriges Abscheiden einer geeignet strukturierten Nitridschicht an den Wänden der Aussparung 8 abgedeckt und so vor einem Eindringen des Dotierstoffes geschützt. Die seitlichen Anteile des unteren Source-Drain-Bereiches 9 entstehen durch eine Diffusion des eingebrachten Dotierstoffes beim Ausheilen der Implantate.The lower limit 12 of the upper source-drain regions 10 and the lower limit 13 of the lower source-drain regions 9 are shown in dashed lines. The lower limit 13 of the implantation introduced for the lower source-drain regions 9 is preferably so deep that a continuous lower source-drain region 9 is designed in the manner of a ground plate. However, it may also be sufficient to insert the implantation in question only approximately up to the dashed line 13a shown as an alternative. The upper limit 14 of the lower source-drain region 9 and the lower limit 12 of the upper source-drain region 10 enclose the respective channel region 11. In the manufacture of the lower doped regions 9, this channel region 11 is z. B. covered by prior deposition of a suitably structured nitride layer on the walls of the recess 8 and thus protected against penetration of the dopant. The lateral portions of the lower source-drain region 9 result from diffusion of the introduced dopant when the implants heal.
Gemäß der schematisierten Aufsicht, die in der Figur 3 dargestellt ist, werden dann streifenförmige Fotolackmasken 15 auf die Oberseite aufgebracht, um zunächst das auf der Oberseite vorhandene isolierende Material, insbesondere den, vorzugsweise durch Oxidation von Polysilizium hergestellten, Schichtanteil 6, zu entfernen und dann die elektrisch leitfä- hige Schicht 5 und das Halbleitermaterial des Halbleiterkörpers 1 in den Bereichen zwischen den Streifen der Fotolackmaske zu entfernen. In der Figur 3 sind noch die seitlichen Begrenzungen der oberen Source-Drain-Bereiche 10 als verdeck- te Konturen gestrichelt eingezeichnet.According to the schematic top view shown in FIG. 3, strip-shaped photoresist masks 15 are then applied to the top in order to first remove the insulating material present on the top, in particular the layer portion 6, preferably produced by oxidation of polysilicon, and then the electrically conductive hige layer 5 and to remove the semiconductor material of the semiconductor body 1 in the areas between the strips of the photoresist mask. In FIG. 3, the lateral boundaries of the upper source-drain regions 10 are also shown in dashed lines as hidden contours.
In der Figur 4 ist die Aufsicht gemäß der Figur 3 dargestellt, nachdem die aus oxidiertem Polysilizium oder auch einem anderen Material hergestellte streifenförmige Maske des Schichtanteils 6 in diesem Bereich entfernt wurde und die Wände der nunmehr vergrößerten Aussparungen 8 zwischen den Grabenfüllungen sowie die Oberfläche des Halbleitermateriales an den Flanken der Grabenfüllungen mit einer dünnen dielektrischen Schicht 18, vorzugsweise einer Oxidschicht, überzo- gen wurde. Auf dem Halbleitermaterial an den Flanken der Grabenfüllungen ist diese dielektrische Schicht 18 als Gate- Dielektrikum vorgesehen.FIG. 4 shows the top view according to FIG. 3 after the strip-shaped mask of the layer portion 6 made of oxidized polysilicon or another material has been removed in this area and the walls of the now enlarged recesses 8 between the trench fillings and the surface of the semiconductor material a thin dielectric layer 18, preferably an oxide layer, was coated on the flanks of the trench fillings. This dielectric layer 18 is provided as a gate dielectric on the semiconductor material on the flanks of the trench fillings.
Die Gateelektroden 16 sind in den Aussparungen hergestellt, und zwar so, dass sie eine Grabenfüllung teilweise überlappen. Die Gateelektroden 16 sind beidseitig bezüglich ihrer Längsrichtungen mit isolierenden Distanzelementen 17 bedeckt. Die elektrisch leitfähigen Schichten 5 sind im Bereich zwischen den Streifen der Fotolackmaske 15 entfernt, so dass ei- ne leitfähige Verbindung zwischen den Bereichen der einzelnen Zellen nur noch im Bodenbereich der Gräben vorhanden ist.The gate electrodes 16 are made in the recesses so that they partially overlap a trench filling. The gate electrodes 16 are covered on both sides with respect to their longitudinal directions with insulating spacer elements 17. The electrically conductive layers 5 are removed in the area between the strips of the photoresist mask 15, so that a conductive connection between the areas of the individual cells is only present in the bottom area of the trenches.
In der Figur 5 ist diese Struktur in einem Querschnitt dargestellt, der die Position des Querschnittes A in der Figur 0 einnimmt, wobei in der Figur 5 allerdings erst ein Zwischenprodukt gezeigt ist, bei dem die Bitleitungen noch nicht hergestellt sind. Auf den Oberseiten der Grabenfüllungen aus dielektrischem Material 4 befinden sich hier Anteile der elektrisch leitfähigen Schichten 5, die jeweils allseits auf einzelne Zellen begrenzt sind. Es ist hier auch erkennbar, dass die beiden Gateelektroden 16, die für die an zwei einander gegenüberliegenden Flanken des dielektrischen Materiales 4 angeordneten Kanalbereiche 11 vorgesehen sind, jeweils in den zwischen den Grabenfüllungen hergestellten aktiven Gräben elektrisch voneinander getrennt angeordnet sind. Die Seiten der Gateelektroden 16 sind mit den Distanzelementen 17, z. B. aus Nitrid isoliert. Auf den Gateelektroden 16 können noch eine streifenförmige Schicht 19 aus Polysilizium, Wolfram oder Wolframsilizid und eine Hartmaskenschicht 20 zur Strukturierung der Gateelektroden aufgebracht sein.This structure is shown in FIG. 5 in a cross section, which assumes the position of cross section A in FIG. 0, although FIG. 5 only shows an intermediate product in which the bit lines have not yet been produced. On the upper sides of the trench fillings made of dielectric material 4 there are portions of the electrically conductive layers 5, which are limited on each side to individual cells. It can also be seen here that the two gate electrodes 16 are for the two opposite flanks of the dielectric material 4 arranged channel regions 11 are provided, each in the active trenches produced between the trench fillings are arranged electrically separated from one another. The sides of the gate electrodes 16 are with the spacers 17, z. B. isolated from nitride. A strip-shaped layer 19 made of polysilicon, tungsten or tungsten silicide and a hard mask layer 20 for structuring the gate electrodes can also be applied to the gate electrodes 16.
Ein Querschnitt durch das Speicherzellenfeld in der Position des in der Figur 0 eingezeichneten Schnittes B ist in der Figur 6 für dieses Zwischenprodukt dargestellt. Es ist dort erkennbar, dass das Material der Gateelektroden 16 auch im Bereich zwischen den einzelnen Speicherzellen in der Längsrich- tung der Gräben vorhanden und dort gleichartig strukturiert ist. Die streifenförmig strukturierten Gateelektroden 16 bilden so die Wortleitungen, die jeweils einen Streifen von längs einer Grabenfüllung angeordneten Speicherzellen miteinander verbinden. Die elektrisch leitfähige Schicht 5 fehlt in den Bereichen zwischen den einzelnen Speicherzellen. Zwischen den einzelnen Speicherzellen fehlen die Anteile aus Halbleitermaterial an den Flanken der Bereiche aus dielektrischem Material 4. Die Source-Drain-Bereiche und Kanalbereiche der einzelnen Zellen sind also in der Längsrichtung der Wortlei- tungen unterbrochen und so auf die einzelnen Zellen begrenzt.A cross section through the memory cell array in the position of section B shown in FIG. 0 is shown in FIG. 6 for this intermediate product. It can be seen there that the material of the gate electrodes 16 is also present in the area between the individual memory cells in the longitudinal direction of the trenches and is structured there in the same way. The stripe-shaped structured gate electrodes 16 thus form the word lines, each of which connects a stripe of memory cells arranged along a trench filling. The electrically conductive layer 5 is absent in the areas between the individual memory cells. The portions of semiconductor material on the flanks of the regions made of dielectric material 4 are missing between the individual memory cells. The source-drain regions and channel regions of the individual cells are thus interrupted in the longitudinal direction of the word lines and are thus limited to the individual cells.
Gemäß dem in der Figur 7 dargestellten Querschnitt schließen sich noch weitere Verfahrensschritte an, die aber an sich aus der Halbleitertechnologie bekannt sind. Es wird zunächst eine erste Passivierung (vorzugsweise ein Nitrid) abgeschieden, und die verbliebenen Öffnungen werden mit einer Isolationsschicht 21 (vorzugsweise BPSG [Borphosphorsilikatglas] ) aufgefüllt. Zu diesen Verfahrensschritten gehört auch das Öffnen von zumindest teilweise selbstjustierten Kontaktlöchern in Verbindung mit den herzustellenden Bitleitungen 22. Als Material für die Bitleitungen ist z. B. Wolfram geeignet. Die Bitleitungen 22 sind auf den elektrisch leitfähigen Schichten 5 aufgebracht und kontaktiert, so dass hier eine elektrisch leitfähige Verbindung zu den oberen Source-Drain-Bereichen 10 hergestellt ist. Es ist aber auch möglich, mit Polysilizium gefüllte Kontaktlöcher in Verbindung mit Aluminiumleiterbah- nen einzusetzen oder ein ebenfalls an sich bekanntes, auf Kupfer basierendes Metallisierungsschema einzusetzen.According to the cross section shown in FIG. 7, further method steps follow, but which are known per se from semiconductor technology. First, a first passivation (preferably a nitride) is deposited, and the remaining openings are filled with an insulation layer 21 (preferably BPSG [borophosphosilicate glass]). These method steps also include opening at least partially self-aligned contact holes in connection with the bit lines 22 to be produced. B. tungsten suitable. The bit lines 22 are on the electrically conductive layers 5 applied and contacted, so that here an electrically conductive connection to the upper source-drain regions 10 is made. However, it is also possible to use contact holes filled with polysilicon in connection with aluminum conductor tracks or to use a copper-based metallization scheme which is also known per se.
In der Figur 8 ist im Querschnitt ein alternatives Ausführungsbeispiel dargestellt, bei dem die für das Gate-Dielek- trikum vorgesehene dielektrische Schicht 18 in dem Bereich zwischen den Gateelektroden 16 entfernt ist. Es sind dort also jeweils Grenzflächen 24 der hier als Erdungsplatte durchgehenden unteren Source-Drain-Bereiche 9 freigelegt. Kontaktlochfüllungen 23, 25 für die elektrisch leitfähigen Schichten 5 bzw. diese freigelegten Grenzflächen 24 der unteren Source- Drain-Bereiche 9 sind in die entsprechenden Öffnungen darüber eingebracht. Als Material der Kontaktlochfüllungen kommt z. B. Polysilizium in Frage. Dieses Material wird an der Oberseite eingeebnet und nach Bedarf mit einer geeigneten Fo- tomaskentechnik strukturiert. Es werden dann (in der Figur 8 nicht eingezeichnet) die Bitleitungen quer zu den Wortleitungen verlaufend hergestellt. Die Bitleitungen werden zu den Kontaktlochfüllungen 25 der Erdungsplatte elektrisch isoliert aufgebracht und streifenförmig so strukturiert, dass die elektrisch leitfähigen Schichten 5 der Zellen angeschlossen werden. Zwischen den Bitleitungen und parallel dazu kann eine im Prinzip beliebige Anzahl ähnlicher Leiterstreifen mit Kontakt auf den betreffenden Kontaktlochfüllungen 25 zum An- schluss der Erdungsplatte hergestellt werden. BezugszeichenlisteFIG. 8 shows an alternative exemplary embodiment in cross section, in which the dielectric layer 18 provided for the gate dielectric is removed in the region between the gate electrodes 16. Boundaries 24 of the lower source-drain regions 9, which are continuous here as a grounding plate, are thus exposed there. Contact hole fillings 23, 25 for the electrically conductive layers 5 or these exposed interfaces 24 of the lower source-drain regions 9 are introduced into the corresponding openings above them. The material of the contact hole fillings comes e.g. B. polysilicon in question. This material is leveled at the top and structured with a suitable photo mask technique as required. The bit lines are then produced (not shown in FIG. 8) and run transverse to the word lines. The bit lines are applied to the contact hole fillings 25 of the grounding plate in an electrically insulated manner and structured in strips in such a way that the electrically conductive layers 5 of the cells are connected. In principle, any number of similar conductor strips with contact on the relevant contact hole fillings 25 for connecting the grounding plate can be produced between the bit lines and in parallel therewith. LIST OF REFERENCE NUMBERS
1 Halbleiterkörper1 semiconductor body
2 Padoxid 3 Padnitrid2 pad oxide 3 pad nitride
4 Bereich (Grabenfüllung) aus dielektrischem Material4 area (trench filling) made of dielectric material
5 elektrisch leitfähige Schicht5 electrically conductive layer
6 Schichtanteil6 shifts
7 Distanzelement 8 Aussparung7 spacer 8 recess
9 unterer Source-Drain-Bereich9 lower source-drain region
10 oberer Source-Drain-Bereich10 upper source-drain region
11 Kanalbereich11 channel area
12 untere Grenze der oberen Source-Drain-Bereiche 13 untere Grenze der unteren Source-Drain-Bereiche12 lower limit of the upper source-drain regions 13 lower limit of the lower source-drain regions
13a untere Grenze der unteren Source-Drain-Bereiche13a lower limit of the lower source-drain regions
14 obere Grenze der unteren Source-Drain-Bereiche14 upper limit of the lower source-drain regions
15 Fotolackmaske15 photoresist mask
16 Gateelektrode 17 Distanzelement16 gate electrode 17 spacer
18 dielektrische Schicht18 dielectric layer
19 streifenförmige Schicht19 stripe-shaped layer
20 Hartmaskenschicht20 hard mask layer
21 Isolationsschicht 22 Bitleitung21 insulation layer 22 bit line
23 Kontaktlochfüllung23 contact hole filling
24 Grenzfläche24 interface
25 Kontaktlochfüllung 25 contact hole filling

Claims

Patentansprüche claims
1. Kondensatorlose 1-Transistor-DRAM-Zelle, bei der in Halbleitermaterial ein Kanalbereich zwischen dotierten Be- reichen für Source und Drain angeordnet ist, diese Bereiche so in dielektrisches Material eingebettet sind, dass der Kanalbereich ohne angelegtes elektrisches Potential zumindest teilweise an Ladungsträgern verarmt ist, und eine Gateelektrode über dem Kanalbereich und von diesem durch ein Gate-Dielektrikum isoliert angeordnet ist, d a d u r c h g e k e n n z e i c h n e t , dass an einer Oberseite eines Halbleiterkörpers (1) oder Substrates ein Bereich aus dielektrischem Material (4) ausgebildet ist, der Kanalbereich (11) an einer Flanke des Bereiches aus dielektrischem Material (4) angeordnet ist, die Source-Drain-Bereiche (9, 10) sich in vertikaler Richtung bezüglich der Oberseite beidseitig an den Kanalbereich (11) anschließen, die Gateelektrode (16) auf einer von dem Bereich aus dielektrischem Material (4) abgewandten Seite des Kanalbereiches (11) und von diesem durch eine als Gate-Dielektrikum vorgesehene dielektrische Schicht (18) getrennt angeordnet ist und die Gateelektrode (16) mit einer Wortleitung verbunden ist und ein bezüglich des Halbleiterkörpers (1) oder Substrates oberer Source-Drain-Bereich (10) mit einer Bitleitung verbunden ist.1. Capacitor-free 1-transistor DRAM cell in which a channel region is arranged between doped regions for source and drain in semiconductor material, these regions are embedded in dielectric material in such a way that the channel region is at least partially depleted of charge carriers without an applied electrical potential , and a gate electrode is arranged above the channel region and insulated therefrom by a gate dielectric, characterized in that a region made of dielectric material (4) is formed on an upper side of a semiconductor body (1) or substrate, the channel region (11) a gate of the region made of dielectric material (4), the source-drain regions (9, 10) adjoin the channel region (11) on both sides in the vertical direction with respect to the top, the gate electrode (16) on one of the region made of dielectric material (4) facing away from the channel region (11) and d is arranged separately by a dielectric layer (18) provided as a gate dielectric and the gate electrode (16) is connected to a word line and an upper source-drain region (10) with respect to the semiconductor body (1) or substrate is connected to a bit line ,
2. 1-Transistor-DRAM-Zelle nach Anspruch 1, bei der das Halbleitermaterial des Kanalbereiches (11) in einer zu der Oberseite koplanaren Schnittebene nach allen Seiten hin durch dielektrisches Material begrenzt ist .2. 1-transistor DRAM cell according to claim 1, in which the semiconductor material of the channel region (11) is delimited on all sides in a sectional plane coplanar by dielectric material.
3. 1 -Transistor-DRAM-Zelle nach Anspruch 2, bei der das Halbleitermaterial des Kanalbereiches (11) in einer zu der Oberseite koplanaren Schnittebene in Richtungen, die zu der Grenze zwischen dem Halbleitermaterial des Kanalbereiches (11) und dem Bereich aus dielektrischem Material (4) parallel verlaufen, Abmessungen besitzt, die in der Nähe der Gateelektrode (16) geringer sind als in der Nähe des Bereiches aus dielektrischem Material (4) .3. 1-transistor DRAM cell according to claim 2, wherein the semiconductor material of the channel region (11) in a cutting plane coplanar to the top in directions leading to the boundary between the semiconductor material of the channel region (11) and the region made of dielectric material (4) is parallel, has dimensions which are smaller in the vicinity of the gate electrode (16) than in the vicinity of the region made of dielectric material (4).
4. Anordnung aus 1-Transistor-DRAM-Zellen nach einem der Ansprüche 1 bis 3, bei der an der Oberseite des Halbleiterkörpers (1) oder Substrates mehrere im Abstand zueinander angeordnete Bereiche aus dielektrischem Material (4) vorhanden sind, zwischen diesen Bereichen aus dielektrischem Material (4) jeweils das Halbleitermaterial bis auf Anteile entfernt ist, die an den Flanken der Bereiche aus dielektrischem Material (4) vorhanden und für Kanalbereiche (11) und Source-Drain- Bereiche (9, 10) vorgesehen sind, so dass zwischen diesen verbliebenen Anteilen des Halbleitermateriales jeweils eine Aussparung (8) vorhanden ist, und die Gateelektroden (16) in diesen Aussparungen (8) angeordnet sind.4. Arrangement of 1-transistor DRAM cells according to one of claims 1 to 3, in which on the upper side of the semiconductor body (1) or substrate there are several regions of dielectric material (4) arranged at a distance from one another, between these regions dielectric material (4) the semiconductor material is removed to the extent that is present on the flanks of the regions made of dielectric material (4) and is provided for channel regions (11) and source-drain regions (9, 10), so that between a recess (8) is provided for each of the remaining portions of the semiconductor material, and the gate electrodes (16) are arranged in these recesses (8).
5. Anordnung nach Anspruch 4, bei der an der Oberseite über den Bereichen aus dielektrischem Material (4) elektrisch leitfähige Schichten (5) vorhanden sind und diese elektrisch leitfähigen Schichten (5) jeweils zwei an einander gegenüberliegenden Flanken des betreffenden Bereiches aus dielektrischem Material (4) vorhandene, bezüglich des Halbleiterkörpers (1) oder Substrates obere Source-Drain- Bereiche (10) miteinander verbinden.5. Arrangement according to claim 4, in which there are electrically conductive layers (5) on the upper side above the regions made of dielectric material (4) and these electrically conductive layers (5) each have two opposite flanks of the relevant region made of dielectric material ( 4) connect existing source-drain regions (10), which are upper with respect to the semiconductor body (1) or substrate.
6. Anordnung nach Anspruch 4 oder 5, bei der die bezüglich des Halbleiterkörpers (1) oder Substrates unteren Source-Drain-Bereiche (9) als durchgehender dotierter Be- reich nach Art einer Erdungsplatte ausgebildet sind. 6. Arrangement according to claim 4 or 5, in which the lower source-drain regions (9) with respect to the semiconductor body (1) or substrate are designed as a continuous doped region in the manner of an earthing plate.
7. Verfahren zur Herstellung einer 1-Transistor-DRAM-Zelle, bei dem in Halbleitermaterial zwei dotierte Bereiche als Source und Drain im Abstand zueinander hergestellt werden, über einem dazwischen als Kanalbereich vorgesehenen Halbleitermaterial und durch ein Gate-Dielektrikum davon getrennt eine Gateelektrode angeordnet wird und der Kanalbereich auf der von der Gateelektrode abgewandten Seite durch dielektrisches Material begrenzt wird, d a d u r c h g e k e n n z e i c h n e t , dass in einem ersten Schritt in einer Oberseite eines Halbleiterkörpers (1) oder Substrates mindestens ein Graben hergestellt wird, in einem zweiten Schritt der Graben mit dielektrischem Mate- rial (4) und einer oberen elektrisch leitfähigen Schicht (5) in Kontakt mit dem angrenzenden Halbleitermaterial gefüllt wird, in einem dritten Schritt eine Implantation von Dotierstoff. in einen bezüglich des Halbleiterkörpers (1) oder Substrates oberen Anteil des Halbleitermateriales, der mit der elektrisch leitfähigen Schicht (5) verbunden ist, zur Ausbildung eines oberen Source-Drain-Bereiches (10) eingebracht wird, in einem vierten Schritt in geringem Abstand zu einer Flanke der Grabenfüllung eine Aussparung (8) in dem Halbleitermate- rial hergestellt wird, so dass ein bezüglich der Oberseite vertikaler Streifen aus Halbleitermaterial an der Flanke des Bereiches aus dielektrischem Material (4) stehen bleibt, in einem fünften Schritt eine Implantation von Dotierstoff in einen bezüglich des Halbleiterkörpers (1) oder Substrates un- teren Anteil des Halbleitermateriales an der Flanke des Bereiches aus dielektrischem Material (4) zur Ausbildung eines unteren Source-Drain-Bereiches (9) eingebracht wird, in einem sechsten Schritt eine als Gate-Dielektrikum vorgesehene dielektrische Schicht (18) auf das Halbleitermaterial an der Flanke des Bereiches aus dielektrischem Material (4) aufgebracht wird, in einem siebenten Schritt eine Gateelektrode (16) in der Aussparung (8) angeordnet und als Anteil einer Wortleitung strukturiert wird und in einem achten Schritt ein von der Gateelektrode (16) iso- lierter elektrischer Anschluss an die elektrisch leitfähige Schicht (5) als Anteil einer Bitleitung hergestellt wird.7. A method for producing a 1-transistor DRAM cell, in which two doped regions are produced as a source and drain at a distance from one another in semiconductor material, a gate electrode is arranged separately from a semiconductor material provided as a channel region therebetween and separated by a gate dielectric and the channel region on the side facing away from the gate electrode is delimited by dielectric material, characterized in that in a first step, at least one trench is produced in an upper side of a semiconductor body (1) or substrate, in a second step the trench is made with dielectric material (4) and an upper electrically conductive layer (5) is filled in contact with the adjacent semiconductor material, in a third step an implantation of dopant. In a fourth step, a portion of the semiconductor material, which is connected to the electrically conductive layer (5) and which is connected to the electrically conductive layer (5), is introduced in a fourth step at a small distance A recess (8) is produced in the semiconductor material on one flank of the trench filling, so that a strip of semiconductor material that is vertical with respect to the upper side remains on the flank of the region of dielectric material (4), in a fifth step an implantation of dopant in a portion of the semiconductor material which is lower with respect to the semiconductor body (1) or substrate is introduced on the flank of the region made of dielectric material (4) to form a lower source-drain region (9), in a sixth step one as a gate dielectric provided dielectric layer (18) on the semiconductor material on the flank of the region of dielectri chemical material (4) is applied, in a seventh step a gate electrode (16) is arranged in the recess (8) and structured as part of a word line and in an eighth step an electrical connection to the electrically conductive layer (5) is isolated from the gate electrode (16) as part a bit line is produced.
8. Verfahren nach Anspruch 7 zur Herstellung einer Anordnung aus 1-Transistor-DRAM-Zellen, bei dem in dem ersten Schritt parallel zueinander verlaufende Gräben hergestellt werden, in dem zweiten Schritt die Gräben mit dielektrischem Material (4) und einer jeweiligen oberen elektrisch leitfähigen Schicht (5) , die beidseitig in Kontakt mit dem angrenzenden Halbleitermaterial ist, gefüllt werden, in dem vierten Schritt Aussparungen (8) jeweils in geringem Abstand zu den Flanken zweier benachbarter Grabenfüllungen hergestellt werden, so dass an beiden einander gegenüberliegenden Flanken der Grabenfüllungen vertikale Streifen aus Halbleitermaterial stehen bleiben, in dem fünften Schritt eine Implantation von Dotierstoff zur Ausbildung von unteren Source-Drain-Bereichen (9) in die unteren Anteile des Halbleitermaterials an den Flanken der Bereiche aus dielektrischem Material (4) eingebracht werden und in der Längsrichtung der Gräben das Halbleitermaterial und die elektrisch leitfähigen Schichten (5) abschnittsweise zur Ausbildung getrennter Zellen entfernt werden, in dem sechsten Schritt die als Gate-Dielektrikum vorgesehene dielektrische Schicht (18) jeweils auf das Halbleitermaterial an den Flanken der Bereiche aus dielektrischem Material (4) aufgebracht wird, in dem siebenten Schritt jeweils zwei voneinander getrennte Gateelektroden (16) vor einander gegenüberliegenden Flanken der Bereiche aus dielektrischem Material (4) angeordnet und als Anteile getrennter Wortleitungen strukturiert werden und in dem achten Schritt jeweils ein von den Gateelektroden (16) isolierter elektrischer Anschluss an die elektrisch leitfähi- gen Schichten (5) als Anteil jeweils einer Bitleitung hergestellt wird.8. The method according to claim 7 for producing an arrangement of 1-transistor DRAM cells, in which trenches running parallel to one another are produced in the first step, in the second step the trenches with dielectric material (4) and a respective upper electrically conductive Layer (5), which is in contact with the adjacent semiconductor material on both sides, in the fourth step, recesses (8) are each made a short distance from the flanks of two adjacent trench fillings, so that vertical stripes on both opposite flanks of the trench fillings remain from semiconductor material, in the fifth step an implantation of dopant to form lower source-drain regions (9) is introduced into the lower portions of the semiconductor material on the flanks of the regions of dielectric material (4) and in the longitudinal direction of the trenches the semiconductor material and the electrically conductive layers (5) are removed in sections to form separate cells, in the sixth step the dielectric layer (18) provided as the gate dielectric is applied to the semiconductor material on the flanks of the regions of dielectric material (4), in the seventh step Two gate electrodes (16) separated from each other are arranged in front of mutually opposite flanks of the regions made of dielectric material (4) and structured as portions of separate word lines, and in the eighth step an electrical connection insulated from the gate electrodes (16) is connected to the electrically conductive gene layers (5) as part of a bit line is produced.
9. Verfahren nach Anspruch 8, bei dem in dem fünften Schritt die Implantationen von Dotierstoff in die unteren Anteile des Halbleitermateriales zur Ausbildung eines durchgehenden dotierten Bereiches nach Art einer Erdungsplatte vorgenommen werden und in einem weiteren Schritt diese Erdungsplatte zwischen den Gateelektroden (16) mit einem elektrischen Anschluss versehen wird. 9. The method according to claim 8, in which in the fifth step the implantation of dopant into the lower portions of the semiconductor material to form a continuous doped region in the manner of an earth plate and in a further step this earth plate between the gate electrodes (16) with a electrical connection is provided.
EP03737236A 2002-02-06 2003-01-23 Capacitor-less 1-transistor dram cell and method for producing the same Withdrawn EP1472737A1 (en)

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