EP1098555B1 - Gedruckte Leiterplatte - Google Patents

Gedruckte Leiterplatte Download PDF

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Publication number
EP1098555B1
EP1098555B1 EP00309666A EP00309666A EP1098555B1 EP 1098555 B1 EP1098555 B1 EP 1098555B1 EP 00309666 A EP00309666 A EP 00309666A EP 00309666 A EP00309666 A EP 00309666A EP 1098555 B1 EP1098555 B1 EP 1098555B1
Authority
EP
European Patent Office
Prior art keywords
lands
layer
wiring board
printed wiring
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP00309666A
Other languages
English (en)
French (fr)
Other versions
EP1098555A2 (de
EP1098555A3 (de
Inventor
Toru Otaki
Hideho Inagawa
Toru Osaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP31296399A external-priority patent/JP2001135898A/ja
Priority claimed from JP2000292146A external-priority patent/JP3658304B2/ja
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP1098555A2 publication Critical patent/EP1098555A2/de
Publication of EP1098555A3 publication Critical patent/EP1098555A3/de
Application granted granted Critical
Publication of EP1098555B1 publication Critical patent/EP1098555B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09336—Signal conductors in same plane as power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0939—Curved pads, e.g. semi-circular or elliptical pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Definitions

  • the present invention relates to a printed-wiring board. More particularly, the invention relates to a printed-wiring board provided at least with a first layer and a second layer, having multi-terminal devices, such as a grid array package ICs, installed hereon with a plurality of terminals arranged in a plane configuration.
  • multi-terminal devices such as a grid array package ICs
  • a package is of quad-flat package (QFP) or of tape carrier package (TPC)
  • QFP quad-flat package
  • TPC tape carrier package
  • only one line of terminals is arranged on the outer side of a package so that signal lines can be drawn out from the terminals of the printed-wiring board easily without any particular arrangement. Therefore, it is good enough for a printed-wiring board to use just one layer as the signal layer.
  • the other layers can be used for the power supply-source pattern, the ground patterns, and the like.
  • plural signal layers are needed in order to draw out signal lines from the inner lands. The resultant number of layers becomes many for the printed-wiring board in use or the signal lines should be interrupted into the power supply-source layer and ground layer in order to suppress the layer numbers of the printed-wiring board.
  • Fig. 15 is a plan view which shows the first layer, the surface, of the conventional double-layer printed wiring board generally in use, on which a ball grid array package is assembled.
  • Fig. 16 is a plan view which shows the second layer, the reverse side, of the printed wiring board represented in Fig. 15 , and arranged to be a perspective view in order to make the positional relations clear between them. Then, in order to distinguish the positional relations with lands in Fig. 15 , the land positions are indicated by dotted lines in Fig. 16 .
  • signal lines 52 and 62, and the power supply-source pattern 54 and ground pattern 56 are connected with the land 51. Of many lands, it is not easy to draw out patterns from the inner ones. Thus, the inner lands are connected with signal pattern on the second layer shown in Fig. 16 by way of through holes 53, 55, and 57.
  • a part of signal pattern shown in Fig. 16 is connected with the signal pattern on the second layer by way of through holes.
  • the signal line 62 is connected with the signal line 58 on the second layer by way of a through hole 53.
  • the power supply-source pattern 54 is connected with the power supply-source pattern 59 on the second layer by way of a through hole 55.
  • the ground pattern 56 is connected with the ground pattern 60 on the second layer by way of a through hole 57.
  • a reference numeral 61 designates the by-pass capacitor land which is assembled between the power supply-source pattern 63 and the ground pattern 64.
  • the grid array package assembled on a double-layer printed wiring board makes it impossible to arrange the ground pattern freely due to the existence of signal lines and others.
  • the ground pattern should be made far from being in an ideal plane configuration.
  • the structure of the ground pattern tends to become one having many chipping portions.
  • a multi-layer printed wiring board is used, in which the number of signal layers is increased so that a layer is dedicated for use of the power supply-source, and another for grounding. In this case, however, costs become significantly high, and also, there is a problem encountered that printed wiring board becomes heavier.
  • the loop area A As understandable from the above formula, it is desirable to make the loop area A as small as possible for the high frequency current I which may create the problem of irradiated noises.
  • the digital signal lines should be made as short as possible, and also, the ground pattern or the power supply-source pattern where return current runs should desirably be arranged as near the signal lines as possible. Also, among digital circuits, special care should be given to the clock signal lines through which high frequency signals flow.
  • the ground pattern that has many chipped portions may result in the increase of reflection that tends to invite the disturbance of signal waveforms or may invite ground bounces. Then, it becomes easier for equipment to malfunction.
  • Fig. 17 is a cross-sectional view of a printed wiring board which schematically shows the relationship between the pattern arrangement of signal lines, power supply-source lines, ground lines, and others on the printed wiring board, and the loop areas.
  • a reference numeral 101 designates an IC output buffer; 102, an IC that receives signals; 103, a signal line; 105, a power supply-source line; 106, a ground line; and 104, a bypass capacitor.
  • the loop area A expressed in the above formula corresponds to the loop A surrounded by the signal line 103 and the ground line 106 in Fig. 17 , the loops B and C surrounded by the power supply-source line 105 and ground line 106 up to the position where the bypass capacitor 104 is assembled, and the loops D and E which are created when the bypass capacitor does not work effectively.
  • Fig. 18 is a cross-sectional view of the printed wiring board which corresponds to Fig. 17 , and shows the changes of the loop areas due to the chipping of the ground pattern.
  • Fig. 16 there are chipping portions for the ground patterns 60 and 64 in the vicinity of the package assembling lands. With the signal output pins being considered as reference, for example, this is the condition where any ground pattern is arranged near the signal line. Then, as the loop G shown in Fig. 18 , the increase of loop area is invited, thus increasing unwanted radiant noises (irradiated noises).
  • thick lines in Fig. 16 indicate either the thick pattern on the printed wiring board or the smaller inductance due to smaller chipping portions.
  • the characteristic impedance becomes larger, and it tends to create inconformity with Lhe portion to which the ground pattern is formed closer, hence making a larger reflection.
  • the inductance becomes larger to generate greater ground bounces.
  • the present invention is designed in consideration of the problems discussed above. It is an object of the invention to provide an inexpensive and light printed wiring board having grid array type package assembled thereon with a lesser amount of unwanted radiant noises, being capable of suppressing the malfunction of electronic equipment that may be caused by reflections or ground bounces.
  • Fig. 1 is a plane view which shows the first layer, the surface of a double-layer printed wiring board in accordance with a first embodiment of the present invention.
  • Fig. 2 is a plan view which shows the second layer, the reverse side, of the double-layer printed wiring board.
  • Fig. 2 is a perspective view to distinguish the positional relation with each other, indicating the land position in Fig. 1 by dotted lines so that the positional relations with the lands is made clear.
  • a signal pattern 2 a power supply-source pattern 4, and a ground pattern 6 are connected with a land 1 where a ball grid array package is assembled.
  • through holes 3, 5, and 7 are arranged for connection with the second layer shown in Fig. 2 .
  • each of the through holes 3, 5, and 7 is formed for the signal line 21, the power supply-source pattern 4, and the ground pattern 6, respectively.
  • the first layer shown in Fig. 1 is connected with the second layer by way of the through holes.
  • the signal line 21 is connected with the signal line 8 on the second layer by way of the through hole 3.
  • the power supply-source pattern 4 is connected with the power supply-source pattern 9 by way of the through hole 5
  • the ground pattern 6 is connected with the ground pattern 10 by way of the through hole 7.
  • a reference numeral 11 designates the land of a bypass capacitor which is assembled between the power supply-source pattern 9 and the ground pattern 10.
  • the signal line 8 extends from the through hole 3 to the through hole 22, and the through hole 22 is structured to be connected with the signal pattern on the first layer.
  • the through hole 22 on the first layer is arranged slightly outside of the outermost land where the grid array package is assembled.
  • the ground pattern 10 it becomes possible to form the ground pattern 10 to surround the signal line 8 and through holes 3 and 22 on the second layer, hence enabling the ground pattern 10 to be a portion having a smaller amount of chipping that may present substantially an ideal plane pattern.
  • all the signal lines which are connected with the innermost lands where the grid array package is assembled, are structured in the same manner as the signal line 8.
  • the present invention is not limited to this structure. For example, it may be possible to collect plural numbers of signal lines together, and surround the circumference thereof by the ground pattern.
  • Fig. 3 is a cross-sectional view of a printed wiring board, which shows schematically the relations between the pattern arrangement of signal line, power supply-source line, ground line, and others, and the loop areas on the printed wiring board represented in Fig. 1 and Fig. 2 .
  • the ground pattern 10 is arranged in the vicinity of each of the signal pins, and the structure is made with a smaller amount of chipping. There is no possibility, therefore, to invite the increase of the loop area as in the loop G shown in Fig. 18 . Also, with the smaller amount of chipping on the ground pattern 109 near IC, inductance becomes smaller, and also, the influence of ground bounces becomes smaller.
  • the power supply-source pattern 108 (power supply-source pattern 9 in Fig. 2 ), which is branched from the nucleus power supply-pattern 107, has an appropriate value of inductance.
  • high frequency current is effectively decoupled by the bypass capacitor 104 (the capacity connected with the land 11 for use of the bypass capacitor shown in Fig. 2 ). Therefore, it becomes possible to reduce unwanted radiant noises.
  • the aforesaid effects can be obtained by use of the double-layer printed wiring board thus arranged. It is possible, therefore, to manufacture the printed wiring board of the first embodiment in a light weight at lower costs.
  • Fig. 4 is a plane view which shows the first layer, the surface of a double-layer printed wiring board in accordance with a second embodiment of the present invention.
  • Fig. 5 is a plan view which shows the second layer, the reverse side, of the double-layer printed wiring board.
  • the structure of the second embodiment is fundamentally the same as that of the first embodiment. Therefore, the same reference marks are applied to the same parts, and the detailed description thereof will be omitted.
  • ground patterns 14 are arranged to bury empty spaces in parallel with the signal lines on the outer side of the outermost lands where the grid array package is assembled on the first layer, which is the surface of the printed wiring board shown in Fig. 4 . As shown in Fig. 5 , these ground patterns are electrically connected with the ground pattern 10 on the second layer, which is the reverse side of the printed wiring board, by way of the through holes 15.
  • Fig. 6 is a cross-sectional view of a printed wiring board in accordance with the second embodiment, which shows schematically the relations between the pattern arrangement of signal line, power supply-source line, ground line, and others, and the loop areas on the printed wiring board.
  • the ground pattern 10 is arranged in the vicinity of each of the signal pins to form a structure where the chipping portions are made smaller. Therefore, there is no possibility to invite increasing the loop area G as shown in Fig. 18 . Also, the chipping portion of the ground pattern 109 near IC is small. As a result, inductance becomes smaller, and the influence of ground bounces also becomes smaller. Also, the power supply-source pattern 108, which is branched from the nucleus power supply-source pattern 107, has an appropriate value of inductance. Therefore, high frequency current is decoupled effectively by means of the bypass capacitor 104, hence reducing unwanted radiant noises.
  • the second embodiment is further structured to connect the ground pattern 14 arranged near the signal pattern on the first layer, which is the surface of the printed wiring board, with the ground pattern 10 on the second layer, which is the reverse side of the printed wiring board, by way of the through hole 15.
  • the loop area F becomes smaller to reduce unwanted radiant noises accordingly.
  • Fig. 7 is a plane view which shows the first layer, the surface of a double-layer printed wiring board in accordance with a third embodiment.
  • Fig. 8 is a plan view which shows the second layer, the reverse side, of the double-layer printed wiring board.
  • the structure of the third embodiment is fundamentally the same as that of the second embodiment. Therefore, the same reference marks are applied to the same parts, and the detailed description thereof will be omitted.
  • a ground pattern 17 is arranged anew on the first layer, the surface, of the printed wiring board shown in Fig. 7 .
  • a part of the ground pattern 14 which is arranged in parallel with signal line is connected with the ground pattern 6 which is arranged inner side of the innermost line of lands for use of grid array package connection.
  • Fig. 9 is a cross-sectional view which shows an electronic equipment provided with a printed wiring board illustrated in each of the embodiments described above.
  • a reference numeral 200 designates a double layer printed wiring board, and the double-layer printed wiring board 200 is of the same structure as the double-layer printed wiring board shown in each of the embodiments described above.
  • the ball grid array package type IC 201 is assembled on it.
  • an IC 202 is assembled, which corresponds to the IC 102 shown in Fig. 3 .
  • On the bottom face of the double-layer printed wiring board 200 a chip capacitor 203 and a chip capacitor 204 are assembled.
  • the chip capacitor 203 is the bypass capacitor for use of the IC 201 solder connected with the bypass capacitor for the land 11 shown in Fig. 2 .
  • the chip capacitor 204 is the bypass capacitor for use of the IC 202.
  • a reference numeral 207 designates the metal housing of the electronic equipment.
  • the metal housing 207 is a part of the frame that forms the electronic equipment.
  • supporting members 205 are fixed to install the printing wiring board.
  • the double-layer printed wiring board 200 is fixed to the supporting member 205 by means of screws 206.
  • each nation has a regulation so as not to allow unwanted radiant noises to be generated more than a specific level.
  • the electronic equipment shown in Fig. 9 is able to implement lower noise generation even if there is a slight defect as to the shielding of electromagnetic waves.
  • unwanted radiant noises from the electronic equipment are irradiated directly from the printed wiring board or the noises which are generated by the printed wiring board are transferred to cables, and irradiated from the cables.
  • noise source is surrounded by a metallic housing, for example, so that unwanted radiant noises are not allowed to leak externally, or some other measures are taken for the purpose.
  • an opening is provided for the metallic housing for various reasons, such as to counteract temperature rise, and unwanted radiant noises are allowed to leak from such opening. The actuality is that more consideration should be given to coping with noise generation.
  • the double-layer printed wiring board 200 of the present invention being assembled on an electronic equipment, not only becomes smaller the unwanted radiant noises generated directly from the double-layer printed wiring board 200, but also, the power supply-source and ground of the double-layer printed wiring board 200 are stabilized. Then, the noises which are transferred to cables also become smaller to make noises irradiated from the cables smaller accordingly. As a result, it is possible to implement suppressing the unwanted radiant noises that may be generated from the electronic equipment to an extremely small amount.
  • the double-layer printed wiring board is used, but the number of layers is not necessarily limited to that one.
  • the material of the housing 207 is metal, but the material is not necessarily limited to metal, either. It may be possible to use plastic or a complex material.
  • the installation method of the double-layer printed wiring board 200 is not necessarily limited to use of screws or the like, either.
  • lands 1 formed in matrix are arranged in four lines from the outermost line to the innermost line, and are divided radially into four blocks, A, B, C, and D.
  • Each of the blocks A, B, C, and D is formed by lands 1A1, 1B1, 1C1, and 1D1 on the outermost line, by lands 1A2, 1B2, 1C2, and 1D2 on the second line from the outermost line, by lands 1A3, 1B3, 1C3, and 1D3 on the third line from the outermost line, and by lands 1A4, 184, 1C4, and 1D4 on the fourth line from the outermost line, that is, on the innermost line.
  • the lands 1A1, 1B1, 1C1, and 1D1 on the outermost line of many lands J in matrix formed in four lines are provided with the signal line patterns 2A1, 2B1, 2C1, and 2D1 are provided in the external direction without any changes.
  • the second lands 1A2, 1B2, 1C2, and 1D2 from the outermost line of many lands in matrix are likewise provided with the signal line patterns 2A2, 2B2, 2C2, and 2D2 in the external direction.
  • the adjacent two are made a pair, and provided with the signal line patterns 2A2, 2B2, 2C2, and 2D2 in the external direction from between the lands 1A1, 1B1, 1C1, and 1D1 on the outermost line.
  • the third lands 1A3, 1B3, 1C3, and 1D3 from the outermost line of many lands in matrix are likewise provided with the signal line patterns 2A3, 2B3, 2C3, and 2D3 in the external direction.
  • the adjacent two are made a pair, and provided with the signal line patterns 2A3, 2B3, 2C3, and 2D3 in the external direction from between the lands 1A1, 1B1, 1C1, and 1D1 on the outermost line.
  • the third signal line patterns 2A3, 2B3, 2C3, and 2D3 are provided between the lands 1A1, 1B1, 1C1, and 1D1 on the outermost line and them where the second signal line patterns 2A2, 2B2, 2C2, and 2D2 do not exist. Then, between the lands 1A1, 1B1, 1C1, and 1D1 on the outermost line and them, the third signal line patterns 2A3, 2B3, 2C3, and 2D3, and the second line patterns 2A2, 2B2, 2C2, and 2D2 are arranged alternately.
  • the signal line patterns 2A3, 2B3, 2C3, and 2D3 from the third line, and the signal line patterns 2A2, 2B2, 2C2, and 2D2 from the second line are arranged between the lands 1A1, 1B1, 1C1, and 1D1 on the outermost line, it is difficult to arrange the signal line patterns 2A4, 2B4, 2C4, and 2D4 from the lands 1A4, 1B4, 1C4, and 1D4 on the innermost line of many lands 1 in matrix between the lands 1A1, 1B1, 1C1, and 1D1 on the outermost line.
  • the first through holes 3A, 3B, 3C, and 3D are arranged in the vicinity, the inner side, for example, of the lands 1A4, 1B4, 1C4, and 1D4 on the innermost line.
  • the second through holes 22A, 22B, 22C, and 22D are arranged on the outer side of the lands 1A1, 1B1, 1C1, and 1D1 on the outermost line.
  • the first through holes 3A, 3B, 3C, and 3D, and the second through holes 22A, 22B, 22C, and 22D penetrate between the first and second layers. Then, as shown in Fig.
  • signal lines 8A, 8B, 8C, and 8D are provided between the first through holes 3A, 3B, 3C, and 3D, and the second through holes 22A, 22B, 22C, and 22D.
  • One ends of signal lines 8A, 8B, 8C, and 8D are connected with the first through holes 3A, 3B, 3C, and 3D, and the other ends thereof are connected with the second through holes 22A, 22B, 22C, and 22D, respectively.
  • the signal line patterns 2A4, 284, 2C4, and 2D4 from the lands 1A4, 1B4, 1C4, and 1D4 on the innermost line of many lands 1 in matrix are installed through the first through holes 3A, 3B, 3C, and 3D, and the signal lines 8A, 8B, 8C, and 8D, and the second through holes 22A, 22B, 22C, and 22D.
  • the signal lines patterns from the many lands, which are divided into blocks are directed equally per block.
  • the first through holes 3A, 3B, 3C, and 3D are connected with the lands 1A4, 1B4, 1C4, and 1D4 on the innermost line by use of the signal lines 21A, 21B, 21C, and 21D.
  • lands are radially divided into four blocks as shown in Fig. 10 in order to draw signal lines in the same direction per block.
  • the present invention is not necessarily limited to the division of four blocks. It is possible to consider dividing many lands into blocks as shown in Fig. 14 .
  • the block structure so that the lands on the spaces ab and da are incorporated into the block a, and then, the lands on the spaces bc and cd are incorporated into the block c, or the lands on the space ab is incorporated into the block a, the lands on the space bc into the block b, the lands on the space cd into the block c, and the lands on the space da into the block d, or the lands on the spaces ab and da are incorporated into the block a, the lands on the space bc into the block b, and the lands on the space cd into the block d, or the lands on the spaces ab and da are incorporated into the space a, the land on the space bc into the block b, and the lands on the space cd into the block c.
  • the first layer and the second layer are connected by way of through holes.
  • the connections are not necessarily limited thereto. It may be possible to connect the first and second layers through the signal connection holes that connect them electrically. For example, via holes may be used for such connection.
  • the signal line patterns from the lands on the innermost line of many lands in matrix are arranged by way of the through hole and signal lines, and the second through hole.
  • the present invention is not limited thereto. It may be possible to arrange the signal line patterns positioned inside many lands on the outermost line by way of the first through hole and signal lines, and the second through hole.
  • the present invention is not necessarily limited thereto.
  • the printed wiring board of the present invention which is provided at least with the first and second layers, and on which is assembled multi-terminal device having a plurality of terminals arranged in matrix thereon, comprises many numbers of lands divided into plural blocks, which are arranged in matrix on the first layer so that each terminal of the multi-terminal devices is connected correspondingly; signal line patterns connected with many lands and drawn out in the same direction per block; the first signal connection holes connected with the lands positioned inside the outermost line of the many lands, which connect the first layer and the second layer electrically; the second signal connection holes positioned outside the lands on the outermost line of the many lands, which connect the first layer and the second layer electrically; and the signal lines having one end thereof connected with the first signal connection holes, and the other end thereof connected with the second signal connection holes.
  • the signal line patterns from the lands positioned on the innermost line of the many lands are arranged through the first signal connection holes, the signal lines, and the second signal connection holes.
  • the wiring patterns of signal lines can be drawn out regularly from many lands formed in matrix on the assembling surface of the grid array type package to make it possible to provide a printed wiring board capable of easily connecting lines without increasing the layers of printed wiring board or arranging any complicated wiring.
  • ground patterns that surround signal lines it becomes possible to secure the ground passage of return current, hence making the current loops smaller to reduce unwanted radiant. Also, it becomes possible to make the chipping portions smaller for the grounds in the vicinity of the multi-terminal devices. Thus, the influence of ground bounces and reflections is made smaller accordingly.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Claims (10)

  1. Leiterplatte, die zumindest mit einer ersten Schicht und einer zweiten Schicht vorgesehen ist, um eine Multi-Anschluss-Einrichtung mit einer Vielzahl von Anschlüssen aufzuweisen, die in einem auf mehreren Lötanschlüssen (1) rasterförmig auf der ersten Schicht zusammengesetzten Rastermuster angeordnet ist, mit:
    den mehreren Lötanschlüssen (1), die in vier Blöcken (A, B, C, D), einen pro Seite des Rastermusters, aufgeteilt sind, und die rasterförmig auf der ersten Schicht angeordnet sind, um jeden Anschluss der Multi-Anschluss-Einrichtung entsprechend zu verbinden;
    ersten Signal-Verbindungs-Löchern (3), die mit den innerhalb der äußersten Zeile der mehreren Lötanschlüsse (1) positionierten Lötanschlüssen verbunden sind, um die erste Schicht und die zweite Schicht elektrisch zu verbinden;
    zweiten Signal-Verbindungs-Löchern (22), die außerhalb der Lötanschlüsse in der äußersten Zeile der mehreren Lötanschlüsse positioniert sind, um die erste Schicht und die zweite Schicht elektrisch zu verbinden;
    Signalleitungen (8), die auf der zweiten Schicht vorgesehen sind, wobei ein Ende davon mit den ersten Signal-Verbindungs-Löchern verbunden ist, und das andere Ende davon mit den zweiten Signal-Verbindungs-Löchern verbunden ist;
    einer ersten Massestruktur (10), die auf der zweiten Schicht vorgesehen ist und ausgebildet ist, um die Signalleitungen (8) zu umgeben; und
    Signalleitungsstrukturen (2), die mit den mehreren Lötanschlüssen verbunden sind, und die in eine entsprechende unterschiedliche der vier Richtungen für jeden entsprechenden Block herausgezogen sind, wobei die Signalleitungsstrukturen (2) für die innerhalb der äußersten Zeile der mehreren Lötanschlüsse positionierten Lötanschlüsse daran über die ersten Signal-Verbindungs-Löcher (3), die Signalleitungen (8) und die zweiten Signal-Verbindungs-Löcher (22) verbunden sind.
  2. Leiterplatte gemäß Anspruch 1, wobei die innerhalb der äußersten Zeile der mehreren Lötanschlüsse (1) positionierten Lötanschlüsse mit den ersten Signal-Verbindungs-Löchern (3) durch die anderen Signalleitungen (21) verbunden sind, die für die erste Schicht vorgesehen sind.
  3. Leiterplatte gemäß Anspruch 1, wobei die mehreren Lötanschlüsse (1) jeweils im Wesentlichen kreisförmig sind.
  4. Leiterplatte gemäß Anspruch 1, wobei die ersten Massestrukturen (10) die Gebiete auf der zweiten Schicht, die den innerhalb der Lötanschlüsse in der innersten Zeile der Vielzahl von Lötanschlüssen positionierten Gebieten auf der ersten Schicht entsprechen, und die Gebiete auf der zweiten Schicht, die den außerhalb der Lötanschlüsse in der äußersten Zeile der Vielzahl von Lötanschlüssen positionierten Gebieten auf der ersten Schicht entsprechen, bedecken.
  5. Leiterplatte gemäß Anspruch 1, weiterhin mit:
    zweiten Massestrukturen (14), die entlang der ersten Signalleitungen auf den Gebieten auf der ersten Schicht angeordnet sind, die außerhalb der Lötanschlüsse in den äußersten Zeilen der Vielzahl von Lötanschlüssen positioniert sind; und
    dritten Signalverbindungslöchern (15) zum Verbinden der zweiten Massestrukturen (14) mit den ersten Massestrukturen (10).
  6. Leiterplatte gemäß Anspruch 1, weiterhin mit:
    zweiten Massestrukturen (14), die entlang der ersten Signalleitungen auf den Gebieten auf der ersten Schicht angeordnet sind, die außerhalb der Lötanschlüsse in der äußersten Zeile der Vielzahl von Lötanschlüssen positioniert ist;
    dritten Massestrukturen (6), die die Gebiete auf der ersten innerhalb der Lötanschlüsse in der innersten Zeile der Vielzahl von Lötanschlüssen positionierten Schicht bedecken; und
    einer Verbindungseinrichtung (17), die für die erste Schicht zum Verbinden der dritten Massestrukturen (6) und der zweiten Massestrukturen (14) vorgesehen ist.
  7. Leiterplatte gemäß Anspruch 5, weiterhin mit:
    dritten Massestrukturen (6), die die Gebiete auf der ersten Schicht bedecken, die innerhalb der Lötanschlüsse in der innersten Zeile der Vielzahl von Lötanschlüssen positioniert ist; und
    einer Verbindungseinrichtung (17), die für die erste Schicht zum Verbinden der dritten Massestrukturen (6) und der zweiten Massestrukturen (14) vorgesehen ist.
  8. Leiterplatte gemäß Anspruch 1, weiterhin mit:
    ersten Energiezuführungsquelle-Strukturen (9), die für die zweite Schicht vorgesehen sind, die von der Energiezuführungsquelle-Kernstruktur abzweigt;
    zweiten Energiezuführungsquelle-Strukturen (4), die auf der ersten innerhalb der Lötanschlüsse in der innersten Zeile der Vielzahl von Lötanschlüssen positionierten Schicht angeordnet sind; und
    vierten Signal-Verbindungs-Löchern (5) zum Verbinden der ersten Energiezuführungsquelle-Strukturen (9) und der zweiten Energiezuführungsquelle-Strukturen (4).
  9. Anordnung mit einer Leiterplatte gemäß Anspruch 8, weiterhin mit Ableitkondensatoren (104), die zwischen den ersten Energiezuführungsquelle-Strukturen (9) und Massestrukturen (10) angeordnet sind.
  10. Anordnung mit einer Leiterplatte gemäß irgendeinem vorangegangenen Anspruch 1 bis 8, mit einer Multi-Anschlusseinrichtung mit einer Vielzahl von Anschlüssen, die in einem auf den vielen Lötanschlüssen (1) rasterförmig auf der ersten Schicht davon zusammengesetzten Rastermuster angeordnet ist.
EP00309666A 1999-11-02 2000-11-01 Gedruckte Leiterplatte Expired - Lifetime EP1098555B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP31296399 1999-11-02
JP31296399A JP2001135898A (ja) 1999-11-02 1999-11-02 プリント配線板
JP2000292146 2000-09-26
JP2000292146A JP3658304B2 (ja) 2000-09-26 2000-09-26 プリント配線板

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EP1098555A2 EP1098555A2 (de) 2001-05-09
EP1098555A3 EP1098555A3 (de) 2005-04-13
EP1098555B1 true EP1098555B1 (de) 2008-07-23

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DE60039569D1 (de) 2008-09-04
CN1196385C (zh) 2005-04-06
EP1098555A2 (de) 2001-05-09
US6489574B1 (en) 2002-12-03
EP1098555A3 (de) 2005-04-13
CN1297323A (zh) 2001-05-30

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