EP0649079B1 - Geregelter Spannungsquellengenerator der Bandgapbauart - Google Patents

Geregelter Spannungsquellengenerator der Bandgapbauart Download PDF

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Publication number
EP0649079B1
EP0649079B1 EP94202878A EP94202878A EP0649079B1 EP 0649079 B1 EP0649079 B1 EP 0649079B1 EP 94202878 A EP94202878 A EP 94202878A EP 94202878 A EP94202878 A EP 94202878A EP 0649079 B1 EP0649079 B1 EP 0649079B1
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EP
European Patent Office
Prior art keywords
transistor
transistors
emitter
circuit
supply terminal
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EP94202878A
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English (en)
French (fr)
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EP0649079A1 (de
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Timothy Ridgers
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Philips Composants et Semiconducteurs SAS
Koninklijke Philips NV
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Philips Composants et Semiconducteurs SAS
Koninklijke Philips Electronics NV
Philips Electronics NV
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the present invention relates to a generator circuit stabilized voltage comprising a cell of the so-called "bandgap" type, in which a plurality of transistors connected in parallel forms a set equivalent to a first transistor, of a first polarity, whose transmitter is connected to one end of a first resistor emitter, the other end of this resistor being connected by elsewhere at the emitter of a second transistor, of the same polarity, of emitter area equal to that of one of the transistors forming the first transistor, second transistor whose base is connected to that of the first transistor, the node joining the emitter of the second transistor at the first emitter resistor being coupled to a first supply terminal through a second resistor transmitter, circuit further comprising an amplifier acting on the base of the first and second transistors to ensure equality of currents flowing through the first and second respectively transistors, which transistors have their collector powered at from a second supply terminal.
  • a stabilized voltage generator circuit is notably known from document EP-A-0 465 094.
  • Voltage generator circuits independent of variations in temperature and supply voltage are very often necessary for the realization of integrated devices modern.
  • voltage generator circuits of the "bandgap" type require a supply voltage which is above 3 direct junction voltages (3.V BE ) and even 4.V BE .
  • the object of the invention is therefore to propose a generator circuit of the "bandgap" type capable of operating under a supply voltage which hardly exceeds the stabilized voltage generated, (which is usually of the order of 2.V BE , ie ⁇ 1.2 V), a circuit which could nevertheless have stability performance at least as high as the known circuits operating under a supply voltage of 5 Volts.
  • V BE a voltage which is partly related to the drop of voltage provided in the first, second and third current source, and on the other hand, in relation to the voltage supplied by the circuit with determined voltage drop.
  • the known circuit of the prior art cited above comprises a starting device consisting of 4 junctions and a field effect transistor taking the place of a resistance of high value, the whole arranged in series between the power terminals.
  • this known circuit requires a supply voltage which must be greater than 4.V BE .
  • the circuit according to the invention can be supplied with a voltage of only 2 volts, if desired.
  • the circuit according to the invention has a large number of operating elements symmetrically which ensures high error compensation residual, so this circuit has an output voltage high stability against temperature differences as well only deviations from the supply voltage.
  • the circuit according to the invention also has the peculiarity to enter into operation as soon as the voltage power is applied to it.
  • the switch device can be presented in various forms, the simplest being essentially reduced to a transistor with field effect from which the control electrode receives a signal appropriate command.
  • each of the transistors of the current mirror having its transmitter coupled to the first terminal supply by means of a value transmitter resistor determined, another resistance whose value is equal to half of said determined value pairs the transmitter of the error amplifier transistor at the same first terminal feed.
  • the first and second current sources are reduced to resistances of equal value collector, while the third source of current is constituted by another resistance, of value half of the value of one of these collector resistors.
  • a voltage generator circuit comprises a cell 1 of the "bandgap" type as well as an amplifier 2 delivering a reference voltage Vref.
  • the cell 1 comprises a first transistor T 1 and a second transistor T 2 , the transistor T 1 having an emitter surface m times larger than the emitter surface of the second transistor T 2 .
  • the transistor T 1 is preferably made up of m individual transistors connected in parallel, which gives greater precision than the constitution of a single transistor T 1 . In what follows, the transistor T 1 , whatever its constitution will be considered as a single transistor.
  • the emitter is connected to a first end of a first emitter resistor 12, the other end of this resistor being connected on the one hand to the emitter of the second transistor T 2 and on the other hand a first terminal of power supply 9 (ground) through a second emitter resistor 13.
  • the bases of the transistors T 1 and T 2 are connected to each other.
  • the collectors of the transistors T 1 and T 2 are supplied from a second supply terminal 8 through respectively a first collector resistor 14, 15 and a second collector resistor 16, 17, these resistors taking the place of sources of current paired.
  • said resistances of collector each formed of two equal resistance parts, in series. Also for a technological reason, it will be necessary to have of another resistance whose value is equal to one of these four resistance parts.
  • Amplifier 2 includes an input stage provided with a pair of PNP type transistors T 3 , T 4 , the emitters of equivalent area, are respectively connected to the collector of the first and second transistors T 1 , T 2 .
  • the bases of the transistors T 3 and T 4 are connected to each other and coupled to the first supply terminal 9 through a circuit 7 ensuring a determined voltage drop, close to or slightly higher than a voltage drop of one direct polarized junction.
  • the collector of transistor T 4 is connected to the input of a current mirror M formed of NPN transistors T 5 and T 6 , the transistor T 5 being connected as a diode while the collector of transistor T 3 is connected to the collector of transistor T 6 , this node constituting the output of the current mirror.
  • the emitters of transistors T 5 and T 6 are coupled to the first supply terminal 9 through resistors equal to resistors 25 and 26 respectively.
  • the amplifier 2 finally comprises an output stage essentially constituted by a transistor called an error amplifier T 56 of the NPN type, a so-called bias transistor T 34 of the PNP type and a so-called compensation transistor T 22 , NPN type.
  • Each of the transistors constituting the output stage has been represented as formed by two transistors connected in parallel, this for the same technological reasons already mentioned above, that is to say that the transistor T 56 has an emitter surface equivalent to all of the emitter surfaces of transistors T 5 and T 6 , that transistor T 34 has an emitter surface equivalent to all of the emitter surfaces of transistors T 3 and T 4 and that transistor T 22 has an emitter area equivalent to twice the emitter area of transistor T 2 . Subsequently, these transistors will be considered as single transistors even if they are formed by two half surface transistors, connected in parallel.
  • the node joining the collectors of the transistors T 3 and T 6 , constituting the output of the input stage, is connected to the base of the error amplifier transistor T 56 .
  • the node connecting the bases of the pair of transistors T 3 and T 4 is connected to the base of the bias transistor T 34 and the collectors of the transistors T 34 and T 56 are connected to the node 117 connecting the bases of the transistors T 1 and T 2 , node which on the one hand is connected to the output terminal 18 of the amplifier and on the other hand is connected to the base of the compensation transistor T 22 .
  • the node connecting the emitter of the bias transistor T 34 to the collector of the compensation transistor T 22 is coupled to the second power supply terminal 8 via a resistor 35 whose value is equal to one of the resistors 14-17, again half the value of the first collector resistor 14, 15 or half of its equivalent, the second collector resistor 16, 17.
  • Resistor 35 thus achieves a simplified current source delivering a current of value twice the current flowing through resistors 14, 15 (or 16.17).
  • the error amplifying transistor T 56 has its emitter coupled to the first supply terminal 9 via two emitter resistors in parallel 45, 46 which are equal to each other and each equal to one of the emitter resistors 25 or 26 of transistors T 5 and T 6 .
  • the emitter of the compensation transistor T 22 is coupled to the first supply terminal 9 via a resistor 43 whose value is equal to the second emitter resistor 13 of the cell 1.
  • a capacitor 19 of low and non-critical value can be connected in parallel between the node 117 and the base of the error amplifier transistor T 56 so as to ensure better stability of the generator circuit, at high frequency.
  • said second terminal 8 can be connected to the positive power source Vcc.
  • the circuit stabilized voltage generator can be switched on or off operation by means of a switch device 11 arranged in series between the power source itself 10 brought to the positive potential Vcc and the conductor which was called second terminal supply 8.
  • a current I S is firstly divided into two portions I 1 and I 2 as a function of the collector resistors 14, 15 on the one hand and 16, 17 d 'somewhere else.
  • the current I 1 is in turn divided on the one hand into a current I A entering the emitter of the transistor T 3 and a current I pt entering the collector of the transistor T 1 .
  • the current I 2 is in turn divided into a current I B entering the emitter of transistor T 4 and a current I pt entering the collector of transistor T 2 .
  • the cell is supplied in such a way that the collector currents of transistor T 1 and of transistor T 2 are equal to each other.
  • the difference between the current between I A and I B appears at the output of the input stage of the amplifier namely on the node connecting the collectors of the transistors T 3 and T 6 current difference which is applied to the base of transistor T 56 .
  • the collector current of transistor T 56 which is an amplified error current, is applied to node 117 joining the bases of transistors T 1 , T 2 , T 22 and provides a feedback setting the voltage of this node so that the currents I pt passing through the transistors T 1 and T 2 are equal. Since the bases of the transistors T 3 and T 4 are connected together, and the resistors 14, 15 - 16, 17 are equal to each other, the currents I A and I B are substantially equal.
  • the compensation transistor T 22 has an emitter surface twice that of the transistor T 2 . Its emitter is connected to an emitter resistance 43 of value equal to the second emitter resistance 13 of cell 1, which is crossed by a current equal to 2.I pt . Also, the transistor T 22 also outputs it, a current very substantially equal to 2.I pt . As the resistor 35 is chosen to have a value equal to one of the resistors 14-17 and the bias transistor T 34 is chosen with an emitter surface twice that of one of the transistors T 3 or T 4 , it follows that the current entering the emitter of transistor T 34 is very substantially equal to 2.I A. Thus, another current with a value I s flows from the supply terminal 8 into the resistor 35.
  • I e (T 2 ) emitter current of transistor T 2
  • I e (T 2 ) (V T / R 12 ) .
  • the current I e (T 2 ) is therefore a current proportional to the absolute temperature and the collector current of the same transistor, denoted I pt is also a current of the same property whose value is very close to I e (T 2 ).
  • the compensation transistor T 22 in parallel on the transistor T 2 , is arranged to debit a current equal to 2.I pt by noting that this transistor T 22 has its base connected to the base of the transistor T 2 and its collector subjected to a voltage which is identical to the collector voltage of transistor T 2 , since the current I s passing through the resistor 35 is very substantially equal to the current I s , sum of the currents passing through the collector resistors 14, 15 and 16, 17.
  • V (7) + V BE (T 34 ) + R 35 .I s expression in which V (7) is the voltage drop in circuit 7, V BE (T 34 ) is the emitter-base voltage of transistor T 34 , and R 35 is the value of the resistor 35.
  • the voltage drop in the resistor 35 can be chosen to be relatively low, less than 1 V BE for example, but more than several V T.
  • the minimum supply voltage can be a little more than 2.V BE and less, 3V BE if necessary.
  • Vcc voltage of this source
  • the voltage of this source can be equal to the previously defined voltage or a little higher if one chooses a switch device 11 having its own internal resistance.
  • PNP transistors T 3 , T 4 , T 34 operate with an identical emitter / base voltage and an identical current density.
  • the NPN transistors T 1 , T 2 , T 22 operate at the same collector / base voltage and, moreover, the transistors T 2 and T 22 operate with the same current density and the same V BE .
  • the transistors T 5 and T 6 operate at all identical current conditions since the collector of transistor T 6 is connected to the base of transistor T 56 operating symmetrically with all the transistors T 5 and T 6 , while the transistor T 5 has its collector connected to its base. This reproduces a total operating symmetry for the transistors T 5 , T 6 .
  • transistors T 3 and T 4 operate at identical collector voltage.
  • the output voltage Vref It is only at node 117, carrying the output voltage Vref, that there is a difference with respect to the base voltage of the transistors T 5 and T 6 . Indeed, the value of Vref is of the order of 1.25 Volts, independent of the supply voltage.
  • the base / collector voltage of the transistors T 3 and T 4 is generally different from the base / collector voltage of the transistor T 34 although it is easy to provide a voltage equality for a nominal value of the voltage of food.
  • collector current of transistor T 34 should be a little lower or higher than the sum of the collector currents of transistors T 3 and T 4 , depending on whether the voltage drop in resistors 25 and 26 has been chosen lower or higher than the voltage drop of circuit 7, and / or that the supply voltage deviates from its nominal value.
  • the cascode type configuration of all the PNP transistors has the effect of multiplying the output resistance of these transistors and this especially when adopting a relatively high voltage drop in resistors 35, 14-17 is that is to say clearly greater than V T.
  • FIGS. 2A, 2B and 2C show exemplary embodiments of the block 7 of FIG. 1 ensuring a determined voltage drop, close to that of a direct polarized junction or slightly higher.
  • the value of this voltage drop is chosen mainly as a function of the nominal voltage provided on the second supply terminal 8 and of the voltage drops in the resistors 25, 26, 45, 46.
  • a preferred value is chosen to ensure, at the nominal supply voltage, an approximate equality between the voltage V ref of the node 117 and the voltage of the collectors of the transistors T 3 and T 4 .
  • the generator circuit then operates optimally with a very high degree of symmetry eliminating most of the causes of second order errors.
  • the circuit 7 is reduced to a bipolar transistor T 7 connected as a diode and directly biased.
  • the bipolar transistor T 7 can be replaced by an N-channel MOS type transistor, connected in an equivalent manner, so as to have a voltage drop corresponding to its threshold voltage. A voltage drop slightly higher than a V BE is then obtained, whose temperature behavior is advantageous for the operation of the generator circuit.
  • the circuit 7 is in the form of a circuit, known per se, in which a resistance bridge 71, 72 connects in parallel with the collector-emitter path of an NPN T 70 transistor whose base is connected to the intermediate point of this resistance bridge.
  • This arrangement provides a voltage drop proportional to a V BE , the proportionality factor, greater than 1, being chosen at will according to the values of resistors 71 and 72.
  • FIG. 2C provides yet another mounting example usable for the circuit 7 of FIG. 1, which is reduced here to a resistor bridge 73, 74 connected between the second power supply terminal 8 (or the power source Vcc) and the mass (terminal 9).
  • the voltage drop used to flow the base current of the transistors T 3 , T 4 , and T 34 is that occurring at the terminals of the resistor 74. Admittedly, this voltage drop is affected by variations in supply voltage, but this is favorable since the variation in voltage across the resistor 74 occurs in the same direction as the variation in the emitter voltage of the transistors T 3 and T 4 .
  • the variation of the currents I A and I B as a function of the variations of the supply voltage Vcc is reduced.
  • circuit 7 will be chosen which provides a lower voltage drop, the closer to 1 V BE , the lower the minimum supply voltage is desired.
  • FIG. 3 represents an exemplary embodiment of the switch 11 of FIG. 1. It essentially consists of a P-channel field effect transistor T 20 , with enrichment, the source of which is connected to the power source 10 carrying the voltage Vcc, through a resistor 31, the drain of which is connected to terminal 8 called the second supply terminal.
  • the gate of this transistor T 20 receives via a terminal 30 a control signal placing the transistor either in conduction or out of conduction under the effect of a control voltage varying between the voltage of the ground and the voltage Vcc.
  • the resistor 31 in series with the source of the transistor T 20 , as well as of the internal resistance of this transistor.
  • FIG. 4 provides another exemplary embodiment of the switch device 11 of FIG. 1, an example in which a pre-regulation of the current (2.I s ) supplying the amplifier 2 of FIG. 1 is also ensured.
  • a field effect transistor T 40 of the MOS field effect type has its source connected to the first supply terminal 9, (ground). Its gate receives a suitable control signal from a control terminal 41. Its drain is coupled to the power source 10, at Vcc voltage, via a resistor 42 and a PNP type transistor T 43 connected as a diode.
  • Another PNP transistor, T 44 has its base connected to the base of transistor T 43 and its emitter, with an area n times larger than that of the emitter of transistor T 43 , coupled to source 10 via a resistor. emitter 47.
  • the collector of transistor T 44 supplies a current to terminal 8, called the second supply terminal, the value of which is determined for a nominal voltage Vcc, varies logarithmically, and therefore only slightly, when Vcc varies.
  • circuit of figure 4 is a equivalent to that of Figure 3 in which the source resistance 31 would have a value varying in the same direction as the value of Vcc, thus attenuating variations in the voltage produced on terminal 8.
  • FIG. 5 presents a variant of the circuit of FIG. 4 according to which it is a bipolar transistor T 50 , of PNP type, which replaces the transistor T 40 of FIG. 4, the collector of which is connected to terminal 9 (ground) , and the base of which receives an appropriate control signal from the control terminal 51.
  • the emitter of transistor T 50 is coupled to the power source 10 (Vcc) via a resistor 52 of high value and the base-emitter path of a PNP transistor, T 53 . Between the resistor 52 and the collector of this transistor T 53 is inserted a resistor 54, the value of which is chosen to create a voltage drop close to V T under the nominal operating conditions.
  • the collector of transistor T 53 is connected to the base of another PNP transistor, T 55 , whose emitter, with an area n times larger than that of the emitter of transistor T 53 , is connected to the source of food 10.
  • the collector of transistor T 55 delivers a preset current at terminal 8, the value of which varies little as a function of variations in Vcc around its nominal value, as in the previous example.
  • the circuit of FIG. 4 uses a transistor T 40 of the MOS type for the power interruption function while the circuit of FIG. 5 shows a bipolar transistor T 50 to perform the same function.
  • transistor T 40 of the MOS type for the power interruption function
  • FIG. 5 shows a bipolar transistor T 50 to perform the same function.
  • the specialist will easily recognize that the use of these types of transistors could have been exchanged and that they are in no way specific to each of the examples described, where an NPN type transistor could also have been used easily.

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Claims (6)

  1. Stabilisierte Spannungserzeugungsschaltung mit einer Zelle (1) vom "Bandgap"-Typ, bei der eine Mehrzahl von parallel verbundenen Transistoren eine einem ersten Transistor (T1) äquivalente Einheit mit einer ersten Polarität bilden, deren Emitter mit einem Ende eines ersten Emitterwiderstandes (12) verbunden ist, wobei das andere Ende dieses Widerstandes außerdem mit dem Emitter eines zweiten Transistors (T2) mit gleicher Polarität und der gleichen Emitteroberfläche wie der eines der den ersten Transistor (T1) bildenden Transistoren verbunden ist, die Basis des zweiten Transistors mit der des ersten Transistors verbunden ist, der Knotenpunkt, der den Emitter des zweiten Transistors mit dem ersten Emitterwiderstand (12) verbindet, mit einer ersten Versorgungsklemme (9) durch einen zweiten Emitterwiderstand (13) gekoppelt ist, und wobei die Schaltung außerdem einen Verstärker (2) umfaßt, der auf die Basis des ersten und zweiten Transistors wirkt, um für die Gleichheit der Ströme zu sorgen, die durch den ersten bzw. den zweiten Transistor fließen, wobei der Kollektor dieser Transistoren (T1, T2) aus einer zweiten Versorgungsklemme (8) gespeist werden,
    dadurch gekennzeichnet, daß der Kollektor sowohl des ersten als auch des zweiten Transistors mit der zweiten Versorgungsklemme (8) über eine erste bzw. eine zweite Stromquelle (14-15, 16-17) verbunden ist, die beide einen Strom gleicher Stärke liefern, daß der Verstärker (2) eine Eingangsstufe umfaßt, die mit zwei Transistoren (T3, T4) versehen ist, deren Polarität der des ersten und zweiten Transistors (T1, T2) entgegengesetzt ist, deren Emitter mit gleicher Oberfläche mit den Kollektoren des ersten bzw. des zweiten Transistors verbunden sind, deren Basen untereinander verbunden und mit einer ersten Versorgungsklemme (9) durch eine Schaltung (7) mit bestimmten Spannungsabfall gekoppelt sind und deren Kollektoren mit dem Eingang bzw. dem Ausgang eines Stromspiegels (M) mit Verhältnis 1 verbunden sind, der aus Transistoren (T5, T6) mit der genannten ersten Polarität besteht, deren Emitter mit der ersten Versorgungsklemme (9) gekoppelt sind,
    daß der Verstärker (2) eine Ausgangsstufe umfaßt, die im wesentlichen von einem sogenannten Fehlerverstärkungstransistor (T56) mit der ersten Polarität, einem sogenannten Polarisationstransistor (T34) mit der zweiten Polarität sowie einem sogenannten Kompensationstransistor (T22) mit der ersten Polarität gebildet wird,
    daß der Fehlerverstärkungstransistor (T56) eine doppelt so große Emitterfläche hat wie jeder der Transistoren (T5, T6), die den Stromspiegel (M) bilden, seine Basis mit dem Ausgang des Stromspiegels verbunden ist, sein Emitter mit der ersten Versorgungsklemme (9) gekoppelt ist, sein Kollektor mit dem Knotenpunkt (117) verbunden ist, der die Basen des ersten (T1) und zweiten (T2) Transistors verbindet, wobei dieser Knotenpunkt auch den Ausgang (18) des Verstärkers bildet und die stabilisierte Ausgangsspannung (Vref) der Schaltung liefert,
    daß der Polarisationstransistor (T34) die gleiche Emitterfläche hat wie die Gesamtheit der beiden Transistoren (T3, T4) der Eingangsstufe, sein Emitter mit der zweiten Versorgungsklemme (8) über eine dritte Stromquelle (35) verbunden ist, die einen Strom liefert, dessen Wert gleich der Summe der Ströme der ersten und der zweiten Stromquelle (14-15), (16-17) ist, seine Basis mit den Basen der zwei Transistoren (T3, T4) der Eingangsstufe verbunden ist, seine Kollektor mit dem Ausgangsknotenpunkt (117) verbunden ist,
    und daß der Kompensationstransistor (T22) eine doppelt so große Emitterfläche hat wie der zweite Transistor (T2), seine Basis mit dem Ausgangsknotenpunkt (117) verbunden ist, sein Emitter mit der ersten Versorgungsklemme (117) durch einen Widerstand (43) verbunden ist, der den gleichen Wert hat wie der zweite Emitterwiderstand (13) der Zelle, und sein Kollektor mit dem Emitter des Polarisationstransistors (T34) verbunden ist.
  2. Schaltung nach Anspruch 1, dadurch gekennzeichnet, daß die erste und die zweite Stromquelle der Zelle (1) durch Kollektorwiderstände (14-15), (16-17) mit gleichen Werten gebildet werden, während die dritte Stromquelle im Verstärker (2) durch einen anderen Widerstand (35) gebildet wird, der den halben Wert hat wie einer der genannten Kollektorwiderstände.
  3. Schaltung nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, daß der Emitter von jedem der Transistoren (T5, T6) des Stromspiegels mit der ersten Versorgungsklemme (9) mittels eines Emitterwiderstands (25, 26) mit einem bestimmten Wert gekoppelt ist, wobei ein anderer Widerstand (45-46), dessen Wert halb so groß ist wie der genannte bestimmte Wert, die Kopplung des Emitters des Fehlerverstärkungstransitors (T56) mit der ersten Versorgungsklemme übernimmt.
  4. Schaltung nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß die genannte zweite Versorgungsklemme (8) mit einer Versorgungsquelle (10) über eine Unterbrechungsschaltung (11) zur In- oder Außerbetriebnahme der Spannungserzeugungsschaltung verbunden ist.
  5. Schaltung nach Anspruch 5, dadurch gekennzeichnet, daß die Transistoren der zweiten Polarität pnp-Transistoren sind, die Unterbrechungsschaltung im wesentlichen einen Feldeffekttransistor (T20) mit p-Kanal umfaßt, dessen Gate ein Steuersignal empfängt, dessen Drain, eine zweite Versorgungsklemme (8) speist und dessen Source mit einer positiven Spannungsquelle (10) über einen Strombegrenzungswiderstand (31) verbunden ist.
  6. Schaltung nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß die genannte zweite Versorgungsklemme (8) mit einer Versorgungsquelle (10) über eine Schaltung zur Vorregelung des Stroms (2.Is) gekoppelt ist, die den Spannungsregler speist, der eine Impedanz aufweist, die sich in der gleichen Richtung verändert wie die Spannung (Vcc) der Versorgungsquelle (10).
EP94202878A 1993-10-13 1994-10-05 Geregelter Spannungsquellengenerator der Bandgapbauart Expired - Lifetime EP0649079B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9312187A FR2711258A1 (fr) 1993-10-13 1993-10-13 Circuit générateur de tension stabilisée du type bandgap.
FR9312187 1993-10-13

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EP0649079A1 EP0649079A1 (de) 1995-04-19
EP0649079B1 true EP0649079B1 (de) 1998-09-23

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US (1) US5488329A (de)
EP (1) EP0649079B1 (de)
JP (1) JPH07152445A (de)
DE (1) DE69413489T2 (de)
FR (1) FR2711258A1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627461A (en) * 1993-12-08 1997-05-06 Nec Corporation Reference current circuit capable of preventing occurrence of a difference collector current which is caused by early voltage effect
JP2836547B2 (ja) * 1995-10-31 1998-12-14 日本電気株式会社 基準電流回路
DE19621110C1 (de) * 1996-05-24 1997-06-12 Siemens Ag Ein-/Ausschaltbare Schaltungsanordnung zur Erzeugung eines Referenzpotentials
DE19624676C1 (de) * 1996-06-20 1997-10-02 Siemens Ag Schaltungsanordnung zur Erzeugung eines Referenzpotentials
US5751182A (en) * 1996-08-28 1998-05-12 Texas Instruments Incorporated Rapid start-up circuit for voltage reference and method of operation
JPH10228326A (ja) * 1997-02-14 1998-08-25 Canon Inc 定電圧出力回路
JPH11347845A (ja) * 1998-06-10 1999-12-21 Sodick Co Ltd 放電加工用パルス電圧発生方法及び回路
US7321225B2 (en) * 2004-03-31 2008-01-22 Silicon Laboratories Inc. Voltage reference generator circuit using low-beta effect of a CMOS bipolar transistor
US7224210B2 (en) * 2004-06-25 2007-05-29 Silicon Laboratories Inc. Voltage reference generator circuit subtracting CTAT current from PTAT current
US20080164567A1 (en) * 2007-01-09 2008-07-10 Motorola, Inc. Band gap reference supply using nanotubes
CN102591401B (zh) * 2012-03-16 2013-10-16 北京经纬恒润科技有限公司 内建数字电源电路
US9983614B1 (en) * 2016-11-29 2018-05-29 Nxp Usa, Inc. Voltage reference circuit
US10139849B2 (en) * 2017-04-25 2018-11-27 Honeywell International Inc. Simple CMOS threshold voltage extraction circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617859A (en) * 1970-03-23 1971-11-02 Nat Semiconductor Corp Electrical regulator apparatus including a zero temperature coefficient voltage reference circuit
US4380706A (en) * 1980-12-24 1983-04-19 Motorola, Inc. Voltage reference circuit
US4435678A (en) * 1982-02-26 1984-03-06 Motorola, Inc. Low voltage precision current source
US4524318A (en) * 1984-05-25 1985-06-18 Burr-Brown Corporation Band gap voltage reference circuit
US4945260A (en) * 1989-04-17 1990-07-31 Advanced Micro Devices, Inc. Temperature and supply compensated ECL bandgap reference voltage generator
US5029295A (en) * 1990-07-02 1991-07-02 Motorola, Inc. Bandgap voltage reference using a power supply independent current source

Also Published As

Publication number Publication date
DE69413489D1 (de) 1998-10-29
EP0649079A1 (de) 1995-04-19
FR2711258A1 (fr) 1995-04-21
DE69413489T2 (de) 1999-05-20
US5488329A (en) 1996-01-30
JPH07152445A (ja) 1995-06-16

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