EP0597772A1 - Multiplexbetriebener Matrixbildschirm und Steuerverfahren dafür - Google Patents

Multiplexbetriebener Matrixbildschirm und Steuerverfahren dafür Download PDF

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Publication number
EP0597772A1
EP0597772A1 EP93402744A EP93402744A EP0597772A1 EP 0597772 A1 EP0597772 A1 EP 0597772A1 EP 93402744 A EP93402744 A EP 93402744A EP 93402744 A EP93402744 A EP 93402744A EP 0597772 A1 EP0597772 A1 EP 0597772A1
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EP
European Patent Office
Prior art keywords
line
selection
time
potential
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP93402744A
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English (en)
French (fr)
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EP0597772B1 (de
Inventor
Denis Sarrasin
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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Publication of EP0597772A1 publication Critical patent/EP0597772A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • the present invention relates to a matrix display screen of the multiplexed type as well as its control method.
  • This screen allows in particular the display in black and white or in color, with or without halftone, of simple or complex images allowing in particular the visualization of animated images of the television image type.
  • the invention applies to screens using an electroluminescent material or to microdot cathodoluminescent screens.
  • the line which is addressed or which is selected by the short line scan is brought to a so-called selection potential, denoted Vls.
  • Vls selection potential
  • the unaddressed or unselected lines are, depending on the type of screen, either brought to an unselected potential, denoted Vlns, or left floating or set to high impedance.
  • the invention is perfectly suited to cathodoluminescent screens using electron-emitting microdots supported by the column electrodes then playing the role of cathodes, the row electrodes resting on the column electrodes being isolated therefrom and perforated opposite the microdots, then playing the role of grids.
  • One or more cathodoluminescent anodes are arranged opposite the microtips.
  • a cathodoluminescent anode consists of an anode conductor covered with a luminescent material under electronic bombardment.
  • the structure of a microtip screen shows a strong row-column capacity at each row selection; this capacity can be charged or discharged at the column control voltage Vc.
  • the frequency Fm is equal to twice the frequency F1 of line scanning and the capacitive consumption is then maximum.
  • a modulated voltage on the columns of 30 V and a frequency F1 for scanning the lines of 30 kHz we arrive at a consumption of 8 W / dm2.
  • Electroluminescent screens of the ACTFEL type use a thin layer of electroluminescent material interposed between row electrodes and column electrodes. This type of screen is described in particular in the article "Display Drive Handbook” edition 1984 from the company Texas Instruments, "The AC Thin Film Electroluminescent Display", p.2-43 to 2-49.
  • the previously selected line goes into high impedance state, denoted HZ, and the potential of the line is then floating.
  • any voltage exceeding the threshold voltage immediately results in the emission of electrons at the tips and therefore of light at the front face (cathodoluminescence phenomenon).
  • the selection of a line is carried out by bringing it to a potential close to the threshold, the column potential translating the information to be displayed.
  • the discharge time corresponds in fact to the time necessary for the flow of all the charges stored in the line previously addressed.
  • a simple pulse of almost negligible duration in front of the selection time cannot be envisaged to solve this problem. Indeed, it is not enough to bring the line electrode to the desired potential, but it is also necessary to eliminate all the charges stored in the "reservoir" constituted by the line with distributed charges, formed by the line electrode (of non-zero resistivity ) coupled to its array of row-column capacitors, the second terminal of these capacitors being respectively connected to a high resistance (resistive layer disposed between the microtips and the corresponding column electrode).
  • the time required for the evacuation of the charges is greater than ten microseconds.
  • the subject of the invention is precisely a matrix display screen of the multiplexed type and its control method making it possible in particular to remedy the drawback mentioned above; that is to say to reduce the capacitive consumption without reduce the useful address time.
  • the capacitive consumption of a matrix screen is due to the charges and discharges of the capacities located between the rows and the columns not selected.
  • the inventors Since the moments of non-selection of the lines should not make any contribution to the display, the inventors have considered releasing the non-selected line electrodes by putting them in a state known as high impedance so that no current flows between the columns and these lines. However, this is only acceptable if, at any time, their potential difference with the columns remains below the electron emission threshold.
  • the subject of the invention is a matrix display screen of the multiplexed type comprising n line electrodes and m crossed column electrodes for conveying control signals, n line control circuits for successively controlling the n line electrodes, with n and m integers ⁇ 2, the control circuit of the line electrode Li, with i integer such as 1 ⁇ i ⁇ n, comprising means for applying a selection potential to the line electrode Li during a first selection time then a discharge potential during at least part of a second selection time of at least one other line electrode and for placing the line electrode Li at high impedance outside the first selection time and said part of the second selection time , column control circuits for simultaneously applying to the m column electrodes during the first time of selection of potentials suitable for displaying the information of the l igne Li.
  • the discharge of the selected or addressed line can be carried out simply by the use, at the output stage of the line control circuits, of push-pull type circuits.
  • the invention also applies to electroluminescent screens using one or more electroluminescent materials inserted between the row and column electrodes, for example of the ACTFEL type.
  • the display screen shown in Figure 1 is a cathodoluminescent matrix screen for black and white display.
  • This screen comprises, in a known manner, two transparent walls 4 and 6 situated opposite one another, normally assembled in leaktight manner.
  • the lower wall 6 is provided with column electrodes 8 parallel to one another, playing the role of cathodes, and row electrodes 10 parallel to each other, playing the role of grids, placed above and perpendicular to the column electrodes .
  • An electrically insulating layer 12 interposed between the electrodes 8 and 10 ensures their electrical isolation.
  • the column electrodes 8 carry microtips 16 made of an electron emitting material, at the pixel level. Opposite these microtips 16, the insulating layer 12 and the line electrodes 10 are pierced with holes 18 from which the microtips emerge.
  • the upper wall 4 of the screen is provided with a continuous conductive layer 20 acting as an anode. This is covered with a layer 22 made of a material emitting light when it is subjected to an electronic bombardment coming from the microtips 16.
  • the emission of electrons by the microtips 16 is achieved by simultaneously polarizing the cathodes 8, the grids 10 and the anode 20.
  • the anode is brought to the highest potential, denoted VA (generally between 200 and 600V) and the cathodes 8 are controlled simultaneously with each line addressing using a control circuit 24 of known type.
  • This circuit 24 delivers a voltage + Vc or -Vc, as shown in FIG. 2 in the case of a black and white display, the potential + Vc being intended for the display of a black point while the potential -Vc being intended for the display of a white point.
  • the originality of the invention resides in the control circuit for the lines of this screen, the rest being in accordance with the prior art.
  • the general block diagram of the screen line control circuit is also shown in FIG. 1.
  • Each line electrode Li (where i is an integer ranging from 1 to n if n is the total number of line electrodes) corresponds a control circuit 26i connected to a clock CP for the sequential addressing of the lines, to a source power supply delivering a line selection potential Vls and to a power supply supplying a line discharge potential Vd.
  • the selection potential Vls shown in FIG. 2 is applied during the selection time of line Li. During this selection time, potentials are applied to the columns suitable for displaying information on the line Li, ie the potential -Vc or + Vc depending on whether one wishes to display an on state or an off state on the pixels of the line Li.
  • the discharge of the line Li previously selected is then carried out by bringing it to the discharge potential Vd.
  • This discharge potential Vd is ⁇ -Vc. It is applied to the line Li for at least part of the time for selecting the line Li + 1 and therefore for applying the voltage Vls for selection on the line Li + 1.
  • the control circuits 261-26n must be able to impose a positive selection potential Vls or a discharge potential Vd on the addressed lines and then a high impedance state, denoted HZ.
  • an output stage 28i comprising (for each circuit 26i) a conventional push-pull type circuit, which can be produced using MOS transistors or bipolar and logic means to be able to control these transistors.
  • T1i and T2i denote the two transistors of the push-pull system 28i of the line Li.
  • T1i is connected on the one hand to a power source capable of delivering the selection potential Vls and on the other hand to T2i and to the line Li, and T2i is also connected to a power source capable of delivering the discharge potential Vd.
  • the selection of the line Li is done by opening the transistor T2i and by closing the transistor T1i.
  • Line Li is discharged by opening transistor T1i and closing transistor T2i.
  • High impedance is achieved by simultaneously opening the transistors T1i and T2i of the line Li.
  • This type of control can be carried out using an input circuit of the shift register type 30 comprising n + 1 flip-flops 321-32n + 1 to drive the n output circuits 281 to 28n of the n lines of the screen.
  • the shift register 30 has a serial data input D, an input CP clock and n + 1 parallel outputs Q1-Qn + 1.
  • the flip-flop of rank i (32i) is connected through an inverter 34i and a first level translator 36i to the transistor T1i, while the transistor T2i is connected, either directly, or through a second translator of level 38i, at the flip-flop of rank i + 1 and therefore at the output Qi + 1 of flip-flop 32i + 1.
  • the register must include one stage more than the number of line output circuits. This stage arranged at the end of the shift regulator makes it possible to complete the control of the last output circuit.
  • the information present on the input D of the shift register 30 is loaded into the first position of the register (or first flip-flop) and all the data contained in the register are shifted by a flip-flop to the other ; we operate at the start of the frame (or image) by positioning a logic level "1" on D, then a logic level "0" for all the following clock ticks. We thus obtain the circulation of a single state "1" in all the positions of the register, corresponding to the successive selection of all the lines of the screen.
  • an inverter 34i is advantageously used between the stage 32i and the transistor T1i, it being understood that other logic circuits can be used to control the transistors. Similarly, one could use a logic "0" for the selected line and a logic "1” for the lines not selected, and consequently, logic means suitable for this type of control of the transistors.
  • the logic level "1" of the flip-flop 32i of rank i is presented to the gate "AND" 40i-1 of the stage of rank (i-1) of the register, the flip-flop 32i-1 being normally at “0”; there is a logic “1” after its inverter 34i-1 and in front of the second input of the "AND” gate 40i-1 which thus transmits a logic "1” to the voltage translator 38i-1 of transistor T2i-1, imposing by the same at the gate of this transistor a voltage Vd + Vth such that it allows the conduction of the transistor T2i-1 (switch 28i closed on Vd: line Li-1 to Vd).
  • the "AND" gate 40i validating the transistor T2i imposes a logic level "0" for this transistor and the voltage translator 38i therefore imposes on the gate of the transistor T2i the voltage Vd which blocks the transistor T2i (switch 28i open, the state of the line Li is not imposed by the transistor T2i).
  • Tj corresponds to the time which elapses between two clock strokes CP with j going from 1 to n.
  • A, C respectively represent the inputs of the translators 36i and 38i of the output circuit 28i and B represents the input of the AND gate 40i connected to the flip-flop 32i + 1.
  • the output of rank i + 1 of register 30 is effectively connected directly to the gate of transistor T2 via the "AND" gate 40i (at a delay time closely achieved by conventional means, intended to avoid the simultaneous conduction of the two transistors T1i and T2i of the output stage i). Otherwise, a translation stage 38i of logic level must be inserted.
  • the half shift register 42 is associated with the combinational logic 33 2k (inverters and AND gates) and with the output circuits 28 2k comprising circuits of the push-pull type associated with the lines 2k (where k takes the values from 1 to n / 2).
  • the half-register 44 is associated with the combinational logic 33 2k-1 (inverters, and AND gates) and with the output circuits 28 2k-1 of the lines L 2k-1 .
  • FIGS. 5 and 6 respectively show a modification of the combinational logic of FIGS. 3 and 4 in the case of a discharge time of the line Li shorter than the selection time of the next line and in the case of a time longer than the selection time of the next line.
  • an ED signal is applied which operates identically on all the doors 40i.
  • This signal applied sequentially to the lines Li validates the discharge time and thus makes it possible to adjust its duration between 0 and the selection time of the next line.
  • the point C at the input of the translator 38i can only be at 1, which imposes the conduction of the transistor T2i and therefore the discharge, only if the signal ED is also at 1 .
  • the proposed command mode obviously applies in the case of a gray level display (whether digital or analog). Different shades of gray can be obtained by modulating the duration and amplitude of the column signals; to avoid parasitic light emissions, V d must remain the lowest voltage used.
  • the three-color process is obtained either by a successive scanning of three colors (red, green, blue) by multiplexing anode voltages, or by tripling the cathode controls. It therefore has no specific effect on the line scan mode.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
EP93402744A 1992-11-13 1993-11-09 Multiplexbetriebener Matrixbildschirm und Steuerverfahren dafür Expired - Lifetime EP0597772B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9213661A FR2698201B1 (fr) 1992-11-13 1992-11-13 Ecran d'affichage matriciel du type multiplexe et son procédé de commande.
FR9213661 1992-11-13

Publications (2)

Publication Number Publication Date
EP0597772A1 true EP0597772A1 (de) 1994-05-18
EP0597772B1 EP0597772B1 (de) 1997-05-02

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EP93402744A Expired - Lifetime EP0597772B1 (de) 1992-11-13 1993-11-09 Multiplexbetriebener Matrixbildschirm und Steuerverfahren dafür

Country Status (5)

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US (1) US5600343A (de)
EP (1) EP0597772B1 (de)
JP (1) JP3771285B2 (de)
DE (1) DE69310319T2 (de)
FR (1) FR2698201B1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7116291B1 (en) 1999-09-09 2006-10-03 Hitachi, Ltd. Image display and method of driving image display
EP1777688A1 (de) * 2005-10-21 2007-04-25 Toppoly Optoelectronics Corp. Systeme zur Pixelansteuerung
FR2907959A1 (fr) * 2006-10-30 2008-05-02 Commissariat Energie Atomique Procede de commande d'un dispositif de visualisation matriciel a source d'electrons a consommation capacitive reduite
US7916112B2 (en) 2005-10-19 2011-03-29 Tpo Displays Corp. Systems for controlling pixels

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6069598A (en) * 1997-08-29 2000-05-30 Candescent Technologies Corporation Circuit and method for controlling the brightness of an FED device in response to a light sensor
GB2329740A (en) * 1997-09-30 1999-03-31 Sharp Kk A display device and a method of driving a display device
FR2786597B1 (fr) * 1998-11-27 2001-02-09 Pixtech Sa Adressage numerique d'un ecran plat de visualisation
KR100434535B1 (ko) * 1998-12-14 2004-09-18 삼성에스디아이 주식회사 전계 방출 표시소자의 구동방법
JP2000305521A (ja) * 1999-04-16 2000-11-02 Matsushita Electric Ind Co Ltd 表示装置の駆動方法及び表示装置
JP2001188507A (ja) * 1999-12-28 2001-07-10 Futaba Corp 蛍光発光型表示器及び蛍光発光型表示装置
JP3915400B2 (ja) * 2000-11-28 2007-05-16 株式会社日立製作所 画像表示装置及び画像表示装置の駆動方法
KR100430085B1 (ko) * 2001-05-16 2004-05-03 엘지전자 주식회사 평판 디스플레이 패널 및 그 구동방법
JP5191075B2 (ja) * 2001-08-30 2013-04-24 ラピスセミコンダクタ株式会社 表示装置、表示装置の駆動方法、及び表示装置の駆動回路
FR2832537B1 (fr) * 2001-11-16 2003-12-19 Commissariat Energie Atomique Procede et dispositif de commande en tension d'une source d'electrons a structure matricielle, avec regulation de la charge emise
EP1518217A2 (de) * 2002-06-22 2005-03-30 Koninklijke Philips Electronics N.V. Schaltungsanordnung für eine anzeigevorrichtung betreibbar im partiellen anzeigemodus
JP2004272213A (ja) * 2003-02-17 2004-09-30 Hitachi Ltd 画像表示装置
JP5126276B2 (ja) * 2003-02-17 2013-01-23 株式会社日立製作所 画像表示装置
KR100666549B1 (ko) * 2003-11-27 2007-01-09 삼성에스디아이 주식회사 유기전계 발광표시장치 및 그의 구동방법
KR100589324B1 (ko) 2004-05-11 2006-06-14 삼성에스디아이 주식회사 발광 표시 장치 및 그 구동 방법
KR100624317B1 (ko) * 2004-12-24 2006-09-19 삼성에스디아이 주식회사 주사 구동부 및 이를 이용한 발광 표시장치와 그의 구동방법
KR100645700B1 (ko) 2005-04-28 2006-11-14 삼성에스디아이 주식회사 주사 구동부 및 이를 이용한 발광 표시장치와 그의 구동방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0197742A2 (de) * 1985-04-03 1986-10-15 Nortel Networks Corporation Flüssigkristall-Zellenadressierung
EP0249954A2 (de) * 1986-06-17 1987-12-23 Fujitsu Limited Ansteuerung für eine Anzeigevorrichtung in Matrix-Form

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3806760A (en) * 1969-04-17 1974-04-23 S Shimada Electron tube
GB1340456A (en) * 1972-02-08 1973-12-12 Mullard Ltd Cathode ray display device
US4652872A (en) * 1983-07-07 1987-03-24 Nec Kansai, Ltd. Matrix display panel driving system
US5015912A (en) * 1986-07-30 1991-05-14 Sri International Matrix-addressed flat panel display
JPH0693615B2 (ja) * 1988-05-16 1994-11-16 株式会社東芝 ドライバ回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0197742A2 (de) * 1985-04-03 1986-10-15 Nortel Networks Corporation Flüssigkristall-Zellenadressierung
EP0249954A2 (de) * 1986-06-17 1987-12-23 Fujitsu Limited Ansteuerung für eine Anzeigevorrichtung in Matrix-Form

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
S.A.STEINER ET AL.: "High-Performance Column Driver for Gray-Scale TFEL Displays", SID INTERNATIONAL SYMPOSIUM 1988 - DIGEST OF TECHNICAL PAPERS, 24 May 1988 (1988-05-24), ANAHEIM (CA) - USA, pages 31 - 34, XP000041810 *
T.LEROUX ET AL.: "Microtips Display Addressing", SID INTERNATIONAL SYMPOSIUM 1991 - DIGEST OF TECHNICAL PAPERS, May 1991 (1991-05-01), PLAYA DEL REY (CA) - USA, pages 437 - 439 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7116291B1 (en) 1999-09-09 2006-10-03 Hitachi, Ltd. Image display and method of driving image display
US7916112B2 (en) 2005-10-19 2011-03-29 Tpo Displays Corp. Systems for controlling pixels
EP1777688A1 (de) * 2005-10-21 2007-04-25 Toppoly Optoelectronics Corp. Systeme zur Pixelansteuerung
FR2907959A1 (fr) * 2006-10-30 2008-05-02 Commissariat Energie Atomique Procede de commande d'un dispositif de visualisation matriciel a source d'electrons a consommation capacitive reduite
WO2008052945A1 (fr) * 2006-10-30 2008-05-08 Commissariat A L'energie Atomique Procede de commande d'un dispositif de visualisation matriciel a source d'electrons a consommation capacitive reduite
US8477156B2 (en) 2006-10-30 2013-07-02 Commissariat A L'energie Atomique Method of driving a matrix display device having an electron source with reduced capacitive consumption

Also Published As

Publication number Publication date
FR2698201A1 (fr) 1994-05-20
JP3771285B2 (ja) 2006-04-26
US5600343A (en) 1997-02-04
JPH06208340A (ja) 1994-07-26
DE69310319T2 (de) 1997-11-20
FR2698201B1 (fr) 1994-12-16
DE69310319D1 (de) 1997-06-05
EP0597772B1 (de) 1997-05-02

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