EP0499224A1 - Halbleiter-Speicherzelle - Google Patents

Halbleiter-Speicherzelle Download PDF

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Publication number
EP0499224A1
EP0499224A1 EP92102318A EP92102318A EP0499224A1 EP 0499224 A1 EP0499224 A1 EP 0499224A1 EP 92102318 A EP92102318 A EP 92102318A EP 92102318 A EP92102318 A EP 92102318A EP 0499224 A1 EP0499224 A1 EP 0499224A1
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EP
European Patent Office
Prior art keywords
memory cell
node
semiconductor memory
capacitors
mos transistors
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Granted
Application number
EP92102318A
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English (en)
French (fr)
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EP0499224B1 (de
Inventor
Satoru c/o Intellectual Property Div. Takase
Natsuki c/o Intellectual Property Div. Kushiyama
Tohru C/O Intellectual Property Div. Furuyama
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Toshiba Corp
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Toshiba Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements

Definitions

  • the present invention relates to a semiconductor memory cell, particularly, to a memory cell used in, for example, a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • Fig. 1 shows a memory cell widely used nowadays in a DRAM.
  • the memory cell comprises a MOS (insulated gate) transistor Q acting as a transfer gate, which is connected to a word line WL and a bit line BL, and a capacitor C for data storage having a capacitor plate potential VPL connected to one end thereof.
  • MOS insulated gate
  • the DRAM cell shown in Fig.4 comprises a cascade gate including a plurality of cascade-connected MOS transistors Q1 - Q4 and having one end connected to a read/write node N1, and a plurality of capacitors C1 - C4 for data storage connected respectively to said MOS transistors Q1 - Q4.
  • the MOS transistors Q1 - Q4 are sequentially turned on or off in a predetermined order so as to sequentially read data stored in the capacitors C1 - C4 onto the read/write node N1 which is connected to a bit line in the order mentioned, and the read-out write-in data can be sequentially written into the capacitors C4 - C1 from the node N1 in the order mentioned.
  • the DRAM cell shown in Fig.6 is similar that shown in Fig. 4 except that is further incorporates a second node N2 and a MOS transistor Q5 connected between the transistor Q4 and node N2. Also in the DRAM cell of Fig.6, by turning on or off the transistors Q1 - Q5 in a predetermined order so as to sequentially read data stored in the capacitors C1 - C4 onto the node N1 in the order mentioned, and the data can be sequentially written into the capacitors C1 - C4 from the node N2 in the order mentioned.
  • the above described cascade gate type memory cells shown in Figs. 4 and 6 can store data of a plurality of bits in units of one bit.
  • a conventional DRAM consisting of an array of one transistor-one capacitor type cells
  • leading to a remarkably highly integrated DRAM can be formed of an array of memory cells of the cascade gate type, thereby much reducing the unit cost per bit of the memory cell, since only one contact is required to connect a plurality of cells or bits to a bit line.
  • This invention has been made in consideration of the above described circumstances, and therefore has the object to provide a semiconductor memory cell which can form a remarkably highly integrated memory cell array, thereby much reducing the cost of one bit of the memory cell, moreover the voltage variation of the read node will have substantially the same value when any of the capacitors is accesed.
  • the present invention provides a semiconductor memory cell comprising, a first node for reading data, a first cascade gate including a plurality of cascade-connected first MOS transistors and having one end connected to the first node, and a plurality of capacitors for data stage connected at one end to the first MOS transistors, respectively, at the end remote from the node, and there is a predetermined regulation in relation of the capacitance of the capacitors.
  • the present invention also provides a semiconductor memory cell comprising, a first node for reading data, a second node for writing data, a first cascade gate at least three cascade-connected first MOS transistors arranged between the first node and the second node, and a plurality of capacitors for data strange each connected at one end to the connection nodes between adjacent the first MOS transistors forming the cascade gate, respectively, and there is a predetermined regulation in relation of the capacitance of said capacitors.
  • the MOS transistors forming the cascade gate are sequentially turned on or off in a predetermined order so as to sequentially read data stored in the capacitors onto the first node. Further, the data can be sequentially written into the capacitors from the first node or the second node in the order mentioned.
  • the regulation relates to the order of reading data from the capacitors, e.g., the remoter from the first node the capacitors of the memory cell are located, the larger capacitance they have, that gradual reduction in the voltage variation of the first node which occurs while the capacitors are successively accesed will be compensated, so that the voltage variation of the first node will have substantially the same value when any of the capacitors is accesed, thereby preventing data from being erroneously read out.
  • Fig. 4 shows a semiconductor memory cell according to a first embodiment of the present invention.
  • the memory cell comprises a first cascade gate consisting of a plurality of, e.g., four, cascade-connected first MOS transistors Q1 to Q4.
  • One end of the first cascade gate i.e., one end of the MOS transistor Q1 in the drawing, is connected to a first node N1 for reading/writing.
  • capacitors C1 to C4 for data storage are connected to the first MOS transistors Q1 to Q4, respectively, at the ends remote from the node N1, so as to form a DRAM cell.
  • a memory cell array formed of a plurality of the DRAM cells described above is used in a DRAM.
  • the gates of the first MOS transistors Q1 to Q4 are connected to word lines WL1 to WL4 of the memory cell array, respectively, with the node N1 connected to a bit line BL of the memory cell array.
  • the other ends of the capacitors C1 to C4 are commonly connected to a capacitor wiring 11 of the memory cell array.
  • the plate electrodes of the capacitors C1 to C4 are commonly connected to each other, and a predetermined capacitor plate potential VPL is given to the plate electrode commonly with another DRAM cell.
  • a bit line precharging circuit PR is connected to the bit line BL.
  • a sense amplifier 12 senses and amplifies the potential of the bit line BL.
  • a write circuit 13 serves to set the potential of the bit line BL in accordance with the data to be written.
  • Fig. 5 shows timing wave forms exemplifying how the cascade gate type DRAM cell shown in Fig. 4 performs the read operation and write operation.
  • the word lines WL1 to WL4 are turned on or off at the timings shown in Fig. 5 so as to sequentially turn the first MOS transistors Q1 to Q4 on in this order and the transistors Q4 to Q1 off in this order.
  • the transistor Q1 is turned on, with the result that the data stored in the capacitor C1 is read through the transistor Q1 onto the bit line BL and, then, sensed by the sense amplifier 12.
  • the transistor Q2 is turned on, with the result that the data stored in the capacitor C2 is read through the transistors Q2 and Q1 onto the bit line BL.
  • the transistor Q3 is turned on, with the result that the data stored in the capacitor C3 is read through the transistors Q3, Q2 and Q1 onto the bit line BL.
  • the transistor Q4 When the word line WL4 is turned on in the next stage at the time t4 after the bit line BL is precharged again for a predetermined period of time, the transistor Q4 is turned on, with the result that the data stored in the capacitor C4 is read through the transistors Q4, Q3, Q2 and Q1 onto the bit line BL. Further, when the word line WL4 is turned off at the time t5, the transistor Q4 is turned off so as to write the data of the bit line BL, i.e., the write data set by the write circuit 13, into the capacitor C4. When the word line WL3 is turned off in the next stage at the time t6, the transistor Q3 is turned off so as to write the data of the bit line BL into the capacitor C3.
  • the transistor Q2 When the word line WL2 is turned off in the next stage at the time t7, the transistor Q2 is turned off so as to write the data of the bit line BL into the capacitor C2. Further, when the word line WL1 is turned off in the next stage at the time t8, the transistor Q1 is turned off so as to write the data of the bit line BL into the capacitor C1.
  • the capacitor C1 functions such as the floating capacitor CB connected to the bit line BL, so that when the capacitor C2 is connected, part of the read-out charges are distributed to the capacitor C1.
  • the node N1 is connected to the bit line BL. However, it is possible to connect the node N1 directly to the input terminal of the sense amplifier 12.
  • Fig. 6 shows a semiconductor memory cell according to a second embodiment of the present invention.
  • the cascade gate type DRAM cell of the second embodiment comprises a cascade gate including a plurality of cascade-connected first MOS transistors Q1 to Q5 and connected between a first node N1 and a second node N2, and a plurality of capacitors C1 to C4 connected at one end to the connection nodes between adjacent MOS transistors, respectively.
  • a memory cell array is formed of a plurality of the DRAM cells constructed as shown in Fig. 6, and is used in a DRAM.
  • the gates of the MOS transistors Q1 to Q5 are connected to word lines WL1 to WL5 of the memory cell array, respectively.
  • the first node N1 and the second node N2 are commonly connected to the bit line BL of the memory cell array.
  • the other ends of the capacitors C1 to C4 are commonly connected to the capacitor wiring 11 of the memory cell array.
  • a capacitor plate potential VPL is imparted to the capacitor wiring 11.
  • Fig. 7 shows timing wave forms exemplifying how the memory cell shown in Fig. 4 performs the read operation and write operation.
  • the word lines WL1 to WL5 are turned on or off at the timings shown in Fig. 7 so as to sequentially turn the first MOS transistors Q1 to Q5 on in this order and turn the transistors Q5 to Q1 off in this order.
  • the transistors Q1 to Q5 are sequentially turned on in this order, the data stored in the capacitors is sequentially read onto the node N1 starting with the data stored in the capacitor C1 close to the node N1 and ending with the data stored in the capacitor C4 remote from the node N1, as described previously with reference to Fig. 5.
  • the word line WL1 is turned off so as to turn the transistor Q1 off, and the word line WL5 is turned on so as to turn the transistor Q5 on.
  • This operation may be reversed.
  • the transistor Q2 is turned off in the next stage at the time t5
  • the transistor Q2 is turned off so as to write the data of the node N2 in the capacitor C1.
  • the transistor Q3 is turned off so as to write the data of the node N2 in the capacitor C2.
  • the transistor Q4 is turned off so as to write the data of the node N2 in the capacitor C3.
  • the transistor Q5 is turned off so as to write the data of the node N2 in the capacitor C4.
  • first node N1 and the second node N2 are commonly connected to the same bit line BL. However, it is also possible for these first and second nodes N1 and N2 to be separately connected to different bit lines or different sense amplifiers.
  • Fig. 8A is a plan view showing the semiconductor memory cell shown in Fig. 4, which is formed as a stacked cell structure.
  • the memory cell is used in a DRAM array, e.g., a DRAM cell array of an open bit line system, in which a memory node is formed at each of the intersections between the word lines and the bit line.
  • Fig. 8B is a cross sectional view along the line B-B shown in Fig. 8A.
  • the DRAM cell comprises a semiconductor substrate 50, a field isolation region 51, a cell active region 52 in which the active regions, i.e., source, drain and channel regions, of four transistors Q1 to Q4 are linearly arranged on the surface of the semiconductor substrate 50, gates (word lines) WL1 to WL4 of the transistors Q1 to Q4, storage nodes 531 to 534 of four capacitors C1 to C4 for data storage, contacts 541 to 544 between the storage nodes 531 to 534 and the source regions of the transistors Q1 to Q4, respectively, a contact 55 (bit line contact) between the drain region of the transistor Q1 and the bit line BL, a gate insulation film 56, an interlayer insulation film 57, an insulation film 58 for each of the capacitors C1 to C4, a plate electrode 59 for the capacitors C1 to C4, and an interlayer insulation film 60.
  • capacitors C1 - C4 can be controlled by changing thickness, material or area of the insulation film of capacitors, and the other way of controlling them, are described in, 1989 IEDM Technical Digest, pp. 592-595 "3-DEMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS” or "Stacked Capacitor Cells for High-density dynamic RAMs" on PP.600-603 of the literature noted above.
  • the bit line contact 55 is commonly used for another memory cell (not shown). In other words, a single bit line contact is commonly used for two memory cells (i.e., one contact per 8 bits or 1/2 contact per 4 bits).
  • Fig. 2 shows the plan view of the stacked cell in the conventional DRAM cell array of the folded bit line system.
  • Fig. 3 is a plan view showing the stacked cell in the conventional DRAM cell array of the open bit line system. The stacked cell shown in Fig.
  • the stacked cell further comprises a plate electrode (not shown) of the capacitor for data storage.
  • the stacked cell further comprises a plate electrode (not shown) of the capacitor for data storage.
  • the long sides of the conventional cells in Figs. 2 and 3 are 5.5F and 4.5F, respectively.
  • the long side of the pattern portion covering the transistor Q1 and the capacitor C1 is 4.5F in the DRAM cell of the present invention shown in Fig. 8A, which is substantially equal to that of the conventional cell.
  • the long side of the pattern portion covering a pair of the transistor Q2 and the capacitor C2, a pair of the transistor Q3 and the capacitor C3, or a pair of the transistor Q4 and the capacitor C4 is 3F in the DRAM cell shown in Fig.
  • the capacitance of the capacitors C1 to C4 is set C1 ⁇ C2 ⁇ C3 ⁇ C4 without changing the area of each of the capacitors.
  • the long side of the entire cell is 13.5F in the DRAM cell shown in Fig. 8. It follows that, in the case of a memory system of one bit per capacitor, the long side per bit of the cell is 3.375F in the present invention, which is 75% of the long side in the conventional cell shown in Fig. 3 and only 61% of the long side in the conventional cell shown in Fig. 2.
  • the present invention permits markedly diminishing the area per bit of the cell, leading to an improved integration density.
  • each of the capacitors C1 to C4 included in the DRAM cell of the present invention shown in Fig. 8A is smaller than that of the capacitor C included in the conventional cell shown in Figs. 2 and 3.
  • a capacitor capacitance Cs is diminished in the present invention, leading to an increase in a ratio Cb/Cs of a bit capacitance Cb to the capacitor capacitance Cs.
  • two DRAM cells are connected to the node N1 in the present invention, though only one DRAM cell is shown in the drawing.
  • one bit line contact is used for 8 bits (1/2 bit contact line per 4 bits), with the result that the bit capacitance Cb is also markedly diminished in the present invention.
  • the value of Cb/Cs ratio is smaller in the present invention than in the prior art, leading to a larger change in potential in the data reading step.
  • the marked reduction in the bit capacitance Cb permits saving of power consumption.
  • the capacitor capacitance Cs it is possible to increase the capacitor capacitance Cs, though a process change is required to some extent in this case, as described in, for example, "1988 IEDM Technical Digest, pp. 592-595 '3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS' by T. EMA et al" or "Stacked Capacitor Cells for High-density Dynamic RAMs" by H. WATANABE et al on pp. 600-603 of the literature noted above.
  • the array is constructed to include one bit at every intersection between the bit line and the word line.
  • the DRAM cell of the present invention shown in Figs. 8A and 8B is of a stacked cell structure.
  • the present invention also permits providing a DRAM cell of a cross point cell structure by employing the technique described in, for example, "1989 IEDM Technical Digest, pp. 23-26, 'A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs' by K. SUNOUCHI et al".
  • Fig. 9A is a cross sectional view examplifying a DRAM cell of the present invention utilizing a cross point cell structure.
  • Fig. 9B is an equivalent circuit diagram of the cell shown in Fig. 9A.
  • a pair of a vertical transistor and a vertical capacitor is stacked upon another pair in the vertical direction. It should be noted that the bit portion covering the number of pairs of the stacked vertical transistors and vertical capacitors can be integrated into a cell size equal to the one bit portion in the prior art.
  • the DRAM cell comprises a p type semiconductor substrate 61 having a convex portion partially formed on the surface, an n+ type drain region 62 of a transistor Q1 formed on the upper surface of the convex portion of the substrate 61, gate (word lines) 631 (WL1) of the transistor Q1, gate (word lines) 632 (WL2) of the transistor Q2 formed in the side surfaces of the convex portion of the substrate with gate insulation films interposed between these gates and the substrate, an n+ type conductive layers 64, i.e., the source region of the transistor Q1, storage node of a capacitor C1, drain region of a transistor Q2, partially formed on the side surface of the convex portion of the substrate 61, an n+ type source region 65 of the transistor Q2 formed in the lower end portions of the side surfaces of the convex portion of the substrate, a plate electrode 66 of a capacitor C1 or C2 partially formed on the side surface of the convex portion of the substrate with a gate insulation film interposed between the plate
  • each of the DRAM cells shown in Figs. 4 and 6 the other ends of the capacitors C1 to C4 are commonly connected to the capacitor plate potential VPL. However, it is also possible to connect each of the other ends of the capacitors C1 to C4 to a power source potential VCC given from the outside or to the ground potential VSS.
  • Fig. 10 is an equivalent circuit diagram of the DRAM cell prepared by applying the technique described in this literature to, for example, the DRAM cell shown in Fig. 4. In this case, capacitor wirings PL1 to PL4 are connected to the other ends of the capacitors C1 to C4, respectively, as shown in Fig. 10.
  • Fig. 11 is an equivalent circuit diagram of the DRAM cell prepared by applying the technique described in this literature to the DRAM cell shown in Fig. 4.
  • Fig. 12 is an equivalent circuit diagram of the DRAM cell prepared by applying the technique described in this literature to the DRAM cell shown in Fig. 6.
  • the DRAM cell shown in Fig. 11 comprises cascade-connected second MOS transistors Q1a to Q4a acting as transfer gates.
  • the sources of these transistors Q1a to Q4a are connected to the other ends of the capacitors C1 to C4, respectively, and the gates of these second transistors Q1a to Q4a are connected to the gates of the first transistors Q1 to Q4, respectively.
  • the drains of the first and second transistors Q1 and Q1a are connected to complementary bit lines BL and BL ⁇ , respectively. Incidentally, it is possible to connect the drains of these transistors Q1 and Q1a directly to pair of differential input terminals of the sense amplifier.
  • the DRAM cell shown in Fig. 12 comprises cascade-connected second MOS transistors Q1a to Q5a acting as transfer gates.
  • the connection nodes between adjacent second transistors are connected to the other ends of the capacitors C1 to C4, respectively.
  • the gates of the second transistors Q1a to Q5a are connected to the gates of the first transistors Q1 to Q5, respectively.
  • the first and second transistors Q1 and Q1a are connected at one end to complementary bit lines BL1 and BL1 ⁇ , respectively.
  • the first and second transistors Q5 and Q5a are connected at the other end to complementary bit lines BL2, BL2 ⁇ , respectively.
  • the DRAM cell is constructed such that one bit signal of "1" or "0" (one digital data) is stored in a single capacitor.
  • the DRAM cell it is possible to construct the DRAM cell such that data consisting of a plurality of bits is stored in a single capacitor.
  • the semiconductor memory cell of the present invention permits markedly diminishing the cell area per bit using the conventional process technology, leading to a marked reduction in the unit cost per bit. It follows that the present invention makes it possible to avoid the problem inherent in the prior art, i.e., the problem that the manufacturing process is made highly complex and the manufacturing time is increased with increase in the integration density. Further, if a new process technique is developed, the integration density can be further enhanced drastically by the present invention. Moreover, the possibility is reduced that data changes as the bits forming it are sequentially read from the capacitors of the memory cells. This is because the capacitors have, as described above, a specific relationship in terms of their capacitances -- that is, the farther the capacitor is located from the first node, the greater its capacitor.
  • the present invention serves, in particular, to manufacture DRAMs having a large storage capacity at low cost, which can be used in place of memory media such as magnetic disks.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
EP92102318A 1991-02-13 1992-02-12 Halbleiter-Speicherzelle Expired - Lifetime EP0499224B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3041321A JP2660111B2 (ja) 1991-02-13 1991-02-13 半導体メモリセル
JP41321/91 1991-02-13

Publications (2)

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EP0499224A1 true EP0499224A1 (de) 1992-08-19
EP0499224B1 EP0499224B1 (de) 1996-12-11

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EP92102318A Expired - Lifetime EP0499224B1 (de) 1991-02-13 1992-02-12 Halbleiter-Speicherzelle

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US (1) US5341326A (de)
EP (1) EP0499224B1 (de)
JP (1) JP2660111B2 (de)
KR (1) KR960011200B1 (de)
DE (1) DE69215707T2 (de)

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US5369612A (en) * 1990-06-27 1994-11-29 Kabushiki Kaisha Toshiba Semiconductor memory device
US5432733A (en) * 1991-02-13 1995-07-11 Kabushiki Kaisha Toshiba Semiconductor memory device
US5500815A (en) * 1991-11-27 1996-03-19 Kabushiki Kaisha Toshiba Semiconductor memory
EP0697701A3 (de) * 1994-08-10 1996-12-04 Cirrus Logic Inc Verbesserter elektronischer Speicher und Verfahren zur Herstellung und zum Gebrauch eines solcher Speichers
US5625602A (en) * 1991-11-18 1997-04-29 Kabushiki Kaisha Toshiba NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines
CN1742343B (zh) * 2003-01-29 2011-10-19 波尔伊克两合公司 有机存储单元及其驱动电路

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US6330181B1 (en) * 1998-09-29 2001-12-11 Texas Instruments Incorporated Method of forming a gate device with raised channel
US6300179B1 (en) 1999-09-24 2001-10-09 Texas Instruments Incorporated Gate device with access channel formed in discrete post and method
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US7023776B2 (en) * 2001-01-25 2006-04-04 Dphi Acquisitions, Inc. Calibration initiation methods for a tracking and focus servo system
US7294545B2 (en) 2003-07-02 2007-11-13 Micron Technology, Inc. Selective polysilicon stud growth
US20060278912A1 (en) * 2004-09-02 2006-12-14 Luan Tran Selective polysilicon stud growth
US7782697B2 (en) * 2007-04-24 2010-08-24 Novelics, Llc. DRAM with hybrid sense amplifier
TWI415247B (zh) * 2010-12-15 2013-11-11 Powerchip Technology Corp 具有垂直通道電晶體的動態隨機存取記憶胞及陣列
TWI596769B (zh) * 2011-01-13 2017-08-21 半導體能源研究所股份有限公司 半導體裝置及半導體儲存裝置
TWI525615B (zh) * 2011-04-29 2016-03-11 半導體能源研究所股份有限公司 半導體儲存裝置
JP6298657B2 (ja) * 2013-03-07 2018-03-20 株式会社半導体エネルギー研究所 半導体装置
US9343506B2 (en) 2014-06-04 2016-05-17 Micron Technology, Inc. Memory arrays with polygonal memory cells having specific sidewall orientations
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US5369612A (en) * 1990-06-27 1994-11-29 Kabushiki Kaisha Toshiba Semiconductor memory device
US5410505A (en) * 1990-06-27 1995-04-25 Kabushiki Kaisha Toshiba Semiconductor memory device having a memory cell unit including a plurality of transistors connected in series
US5432733A (en) * 1991-02-13 1995-07-11 Kabushiki Kaisha Toshiba Semiconductor memory device
US5444652A (en) * 1991-02-13 1995-08-22 Kabushiki Kaisha Toshiba Semiconductor memory device having a memory cell unit including a plurality of transistors connected in series
US5625602A (en) * 1991-11-18 1997-04-29 Kabushiki Kaisha Toshiba NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines
US5892724A (en) * 1991-11-18 1999-04-06 Kabushiki Kaisha Toshiba NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines
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KR960011200B1 (ko) 1996-08-21
JP2660111B2 (ja) 1997-10-08
DE69215707T2 (de) 1997-05-07
JPH04258881A (ja) 1992-09-14
EP0499224B1 (de) 1996-12-11
KR920017109A (ko) 1992-09-26
US5341326A (en) 1994-08-23
DE69215707D1 (de) 1997-01-23

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