EP0067993A1 - Halbleiterwürfel-verbindung mit verbesserter qualität und zuverlässigkeit - Google Patents

Halbleiterwürfel-verbindung mit verbesserter qualität und zuverlässigkeit

Info

Publication number
EP0067993A1
EP0067993A1 EP81901580A EP81901580A EP0067993A1 EP 0067993 A1 EP0067993 A1 EP 0067993A1 EP 81901580 A EP81901580 A EP 81901580A EP 81901580 A EP81901580 A EP 81901580A EP 0067993 A1 EP0067993 A1 EP 0067993A1
Authority
EP
European Patent Office
Prior art keywords
preform
die
substrate
tin
antimony
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP81901580A
Other languages
English (en)
French (fr)
Inventor
John B. Finn
Robert F. Palermo
Dale W. Dycus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of EP0067993A1 publication Critical patent/EP0067993A1/de
Withdrawn legal-status Critical Current

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    • H01L23/492—Bases or plates or solder therefor
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Definitions

  • the present invention relates generally to the fabrication of semiconductor devices , and more particularly to an improved technique for attaching a die or integrated circuit (IC) chip to a metal or ceramic substrate .
  • IC integrated circuit
  • Attachment of silicon IC chips to metal lead frames or to metallized ceramic bases comprises an important step in the fabrication of semiconductor devices. Typically, after testing, the chips are individually attached to the central portions of metal or metallized ceramic bases from which extend multiple external lead pins for connecting each chip to a circuit board. The terminals of each chip are then wired to the leads of its corresponding base before the chip and central base portion are encased in plastic or hermetically sealed with a ceramic or metal lid for protection. In the industry, such chips are commonly referred to as “dice” with the metal bases being such as “lead frames” and the metallized ceramics known as cer-dip bases.
  • the prior techniques for attaching dice to lead frames or other bases have been characterized by the use of rare metals at relatively high temperatures.
  • the usual practice has been to use an uncoated die or to coat the backside of a die with a thin layer of pure gold, and then use a small piece of gold alloy for bonding the die to a heated lead frame or other base.
  • Such small pieces of gold alloy which are usually comprised of pure gold, gold and silicon, or gold and germanium, are commonly known as "preforms" in the industry.
  • the preform is placed on the central portion thereof until it melts, after which the die is placed on the preform and gently rubbed or "scrubbed in” until wetting of the die by the molten alloy is accomplished, followed by cooling of the lead frame or other base to form a bond and complete attachment.
  • a pure gold preform is employed for die attachment, the gold does not melt until the silicon die is "scrubbed in”. The intimate contact provided by scrubbing permits interdiffusion between the pure gold and the silicon.
  • the silicon content in the gold preform reaches approximately 3..4%, by weight, the alloy melts at approximately 363°C. This is referred to as eutectic melting and die attachment accomplished by this method is known as eutectic die attachment.
  • Another technique has involved the use of epoxy or other organic resin materials filled with a metal powder such as silver.
  • the present invention comprises a method of attaching a die to a substrate which overcomes the foregoing and other difficulties associated with the prior art.
  • an improved die-attach technique which does not require expensive gold or gold alloys and which can be carried out at relatively lower temperatures, thereby avoiding the thermal stress-related problems of the prior art and achieving a connection of greater strength and reliability.
  • an illustrated embodiment of the invention provides a method of attaching a silicon IC chip or die to a metal substrate wherein a barrier coating of chromium is first provided on the back side of the die followed by a coating of silver, gold, tin, antimony or alloys thereof over the chromium coating.
  • the base or substrate is heated to an appropriate temperature of between about 250°C and 400°C.
  • a preform comprised primarily of tin with a small amount of antimony and a trace of aluminum is then placed on the heated substrate until it melts, followed by placement of the die on the melted preform, scrubbing-in the die and cooling to provide a reliable joint between the die and substrate.
  • FIGURE 1 is a perspective view of dice being attached to a lead frame
  • FIGURE 2 is an exploded view of the die-attach technique of the prior art.
  • FIGURE 3 is an exploded view of the die-attach method of the invention.
  • FIGURES 1 illustrates attachment of silicon IC chips or dice 10 onto bases or substrates 12, each of which comprises a central pad portion interconnected by supports to a lead frame 14.
  • the die attach technique herein is described and shown with specific reference to metal lead frames for purposes of illustration, however, it will be understood that the invention can also be utilized with metalized ceramic bases or substrates.
  • Lead frame 14 rests on a heated block 16 and is guided for movement thereacross between a pair of guides 18.
  • An adjustable heating element, temperature sensor and thermometer ⁇ not shown) are associated with block 16 for controlling the temperature thereof.
  • a blank frame 14 is inserted between guides 18 and advanced to position a substrate 12 on block 16 for heating. After substrate 12 has reached the desired temperature, a preform 20 is positioned thereon until it melts, after which die 10 is positioned on the melted preform material and scrubbed-in until wetted by the molten solder. Frame 14 is then advanced to allow the junction between die 10 and substrate 12 to cool while simultaneously positioning the next following substrate in place for heating.
  • a tube 22 discharging a stream of inert or non-oxidizing gas, such as nitrogen, or reducing, such as hydrogen, across frame 14 is preferably associated with heater block 16 to reduce oxidation during the die-attach process.
  • the operation of advancing frame 14 and positioning preform 20 and die 10 thereon can be carried out on an automatic basis or on a manual basis by an operator looking through a microscope and manipulating tweezers.
  • FIGURE 2 illustrates the die-attach technique of the prior art, wherein the underside of the silicon die 10 is first provided with a thin coating of pure gold, typically about 1000 to 2000 Angstroms thick.
  • the coating 24 is usually applied by sputtering, a technique which involves vaporizing the gold and depositing it onto the backside of a die 10 or a wafer of dice under partial vacuum conditions.
  • the metal or metallized ceramic substrate 12 is typically heated to a temperature of about 460°C before the preform 20 of gold alloy is positioned thereon until it melts.
  • Substrate 12 typically has been comprised of silver plated nickel/iron alloy (commonly known as Alloy 42) or silver metallized ceramic material.
  • the materials of preform 20 typically have been comprised of gold or gold alloys, such as gold and silicon or gold and germanium.
  • the die 10 is then lowered into contact with the material of preform 20 and scrubbed in until the die is wetted by the molten preform material, after which substrate 12 is removed from heater block 16 to allow cooling of the junction between the die and substrate.
  • this technique requires expensive materials having d ifferent rates of thermal expansion and brittle characteristics when alloyed with silicon which can result in thermal stress-related difficulties and low reliability in the finished semiconductor package.
  • FIGURE 3 illustrates the die-attach method 30 incorporating the present invention.
  • the underside of the silicon die 10 is provided with two thin coatings.
  • a thin coating 32 of barrier material In the preferred embodiment, substantially pure chromium is used for coating 32; however, it is believed that titanium, zirconium, hafnium, molybdenum, tungsten, vanadium, tantalum and niobium (columbium) would also be effective.
  • a coating 34 of silver, tin, antimony or a tin-antimony alloy is then provided over coating 32. If desired, gold may be used for the second coating 34.
  • Each coating 32 and 34 is approximately 1000 Angstroms thick and can be applied by means of sputtering or other suitable methods of deposition.
  • the preform 36 is preferably comprised of primarily tin with a small amount of antimony and a trace of aluminum. Inclusion of a trace of aluminum is advantageous because it serves to inhibit oxidation, however, the aluminum can be omitted under some conditions if desired. Other combinations of elements which bond with those of coatings 32 and 34 may also be used to fabricate preform 36.
  • the substrate 38 shown in the form of a lead frame comprises metal Carpenter 42 alloy, which is comprised essentially of 0.10% carbon maximum, 0.80% manganese maximum, 0.30% silicon maximum, 0.25% chromium maximum, 40-43% nickel and the balance iron.
  • Substrate 38 may also be comprised of other suitable metal alloys, ceramics, or metallized ceramics and it will be understood that the substrate need not necessarily be in the form of a lead frame to practice the present invention.
  • the steps involved in the die-attach method 30 of the invention also require heating substrate 38 to a temperature of about 250° to 400°C sufficient to melt the preform 36. It has been found in experimentation that a temperature range of 275° to 290°C works well.
  • Preform 36 is then positioned on the heated substrate 38 until the preform melts, followed by placement of die 10 onto the melted material of the preform and scrubbing it in until it is wetted by the molten preform.
  • the chromium of coating 32 acts as a barrier to protect the silicon of die 10, while simultaneously reacting to a limited degree with the alley of preform 36.
  • the molten preform 36 dissolves the material of coating 34 to react with coating 32, and also reacts with the material of substrate 38 to form a bond of enhanced strength and reliability between the die 10 and substrate.
  • tin and antimony which have been found suitable for use as preform 36 are set out below.
  • a trace amount of about 0.06 to 0.08% aluminum is preferablyincluded to inhibit oxidation.
  • the present invention comprises an improved method of attaching a silicon IC chip to a metal substrate or to a metallized ceramic substrate.
  • the method herein is carried out with less expensive materials at less elevated temperatures to avoid the brittleness and stress-related problems of the prior art.
  • Other advantages will be evident to those skilled in the art.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)
EP81901580A 1980-12-30 1980-12-30 Halbleiterwürfel-verbindung mit verbesserter qualität und zuverlässigkeit Withdrawn EP0067993A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1980/001746 WO1982002457A1 (en) 1980-12-30 1980-12-30 Die attachment exhibiting enhanced quality and reliability

Publications (1)

Publication Number Publication Date
EP0067993A1 true EP0067993A1 (de) 1983-01-05

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WO (1) WO1982002457A1 (de)

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Publication number Priority date Publication date Assignee Title
IT1213144B (it) * 1984-02-23 1989-12-14 Ates Componenti Elettron Processo per la saldatura di piastrine di materiale semiconduttore ad un supporto metallico nell'assemblaggio automatico di dispositivi a semiconduttore.
DE3442537A1 (de) * 1984-11-22 1986-05-22 BBC Aktiengesellschaft Brown, Boveri & Cie., Baden, Aargau Verfahren zum blasenfreien verbinden eines grossflaechigen halbleiter-bauelements mit einem als substrat dienenden bauteil mittels loeten
US4772935A (en) * 1984-12-19 1988-09-20 Fairchild Semiconductor Corporation Die bonding process
EP0186585B1 (de) * 1984-12-19 1991-02-06 Fairchild Semiconductor Corporation Verfahren zum Befestigen von Plättchen
US4954870A (en) * 1984-12-28 1990-09-04 Kabushiki Kaisha Toshiba Semiconductor device
US4659006A (en) * 1985-09-26 1987-04-21 Rca Corporation Method of bonding a die to a substrate
JP2502511B2 (ja) * 1986-02-06 1996-05-29 日立マクセル株式会社 半導体装置の製造方法
DE3785720T2 (de) * 1986-09-25 1993-08-12 Toshiba Kawasaki Kk Verfahren zum herstellen eines filmtraegers.
US4875617A (en) * 1987-01-20 1989-10-24 Citowsky Elya L Gold-tin eutectic lead bonding method and structure
US5296074A (en) * 1987-03-30 1994-03-22 E. I. Du Pont De Nemours And Company Method for bonding small electronic components
US5027997A (en) * 1990-04-05 1991-07-02 Hughes Aircraft Company Silicon chip metallization system
US5198695A (en) * 1990-12-10 1993-03-30 Westinghouse Electric Corp. Semiconductor wafer with circuits bonded to a substrate
GB9204731D0 (en) * 1992-03-05 1992-04-15 Westinghouse Brake & Signal A solder joint
DE19639438A1 (de) * 1996-09-25 1998-04-02 Siemens Ag Halbleiterkörper mit Lotmaterialschicht

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US3942244A (en) * 1967-11-24 1976-03-09 Semikron Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Semiconductor element
DE1789062C3 (de) * 1968-09-30 1978-11-30 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen von Metallkontaktschichten für Halbleiteranordnungen
GB1374626A (en) * 1970-10-30 1974-11-20 Matsushita Electronics Corp Method of making a semiconductor device
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