JPS6187396A - 電子回路装置とその製造方法 - Google Patents

電子回路装置とその製造方法

Info

Publication number
JPS6187396A
JPS6187396A JP59208072A JP20807284A JPS6187396A JP S6187396 A JPS6187396 A JP S6187396A JP 59208072 A JP59208072 A JP 59208072A JP 20807284 A JP20807284 A JP 20807284A JP S6187396 A JPS6187396 A JP S6187396A
Authority
JP
Japan
Prior art keywords
solder
melting point
circuit board
electronic circuit
point solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59208072A
Other languages
English (en)
Other versions
JPH0528000B2 (ja
Inventor
了平 佐藤
大島 宗夫
稔 田中
勝 坂口
旻 村田
和夫 廣田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59208072A priority Critical patent/JPS6187396A/ja
Priority to KR1019850006974A priority patent/KR900000183B1/ko
Priority to DE8585112539T priority patent/DE3581251D1/de
Priority to EP85112539A priority patent/EP0177042B1/en
Priority to US06/784,035 priority patent/US4673772A/en
Priority to CN85108637A priority patent/CN85108637B/zh
Publication of JPS6187396A publication Critical patent/JPS6187396A/ja
Publication of JPH0528000B2 publication Critical patent/JPH0528000B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 (発明の利用分野) 本発明は加工熱処理・はんだの局部溶融接続によシ半導
体や部品を回路基板に接続および封止した電子回路装置
およびその製造方法とくに接続部および封止部の信頼性
を向上させるのに利用可能な電子回路装置およびその製
造方法に関する。
(発明の背景) 従来、電子回路装置においては、半導体や部品の機械的
、化学的保護および量産性、信頼性の向上を目的として
はんだによる面付実装が知られている。その中でも半導
体の最も高密度な実装法として第9図に示す如く、半導
体チップ1と基板2の周端部対向面を電極4,5を介し
て微細なはんだ3で接続する方法が知られている(例、
特開昭43−28735 、米国特許第3871014
号)。然るにこの方法は、半導体チップ1と、回路基板
2とを接続するさいにはんだ3を完全に溶融し、上記電
極4.5とのぬれ・拡散反応を利用して半導体チップ1
と、基板2とを接続していた。そのため、半導体チップ
1と、基板2との接続部のはんだ3が冷却過程で合金組
成の偏析や欠隔および残留応力が発生して伸びが小さな
鋳造組織状態となる。この鋳造状態は外力に対して伸び
が小さく、不均一な変形を発生するため、疲労性が悪く
、使用中の種々のストレスに対して比較的短時間ではん
だ3が破壌する問題があった。
(発明の目的) 本発明は従来の上記問題点を解決し、高信穎性のはんだ
接続を可能とする電子回路装置と、その製造方法を提供
することにある。
(発明の概云) 本発明は上記の目的を達成するため、圧延等の強加工と
、熱処理を加えて延性を著しく改善し、はんだ接続部に
対応した形状に成形加工を行なった加工はんだ材を、導
体チップ等の部品と、基板との間に供給された低融点は
んだで加工はんだが溶けない程度の低温度で局部溶融接
続し、加工はんだの優れた延性を活かすことを特徴とす
るものである。
而して、本発明はつぎのような現象および原理に基いて
加工はんだ材を部品と基板との間の接続部材として使用
したのである。すなわち、金属の多くは、溶融・凝固す
ると、ガスの吸截や欠陥が多く、さらに純金属以外の殆
んどの合金は、凝固の過程で組成偏析や重量偏析を伴な
う不均質な鋳造組織となる。このような欠陥や不均質な
組織からなる金属・合金は一般に脆く硬いため、構造部
材等に使用する場合等においては、圧延や熱処理を行な
い鋳造組織をこわして均質にし、これによシ靭性や延性
を改善する方法が行なわれている。
然るに、ろう材としてのpb −SnやAu−8n等の
合金は、溶融接続を基本原理としているため、溶融凝固
すると、必らず鋳造組織となるので、これを加工して破
壌することは殆んど不可能である。
そこで鋳造組織の硬くて脆い性質をそのま\使用せざる
を得なくなる。
第10図は縦軸に応力の(Ky/j )をとり、横軸に
伸びε(イ)をとった場合のPb−Sn合金を例として
加工材a、b、cと、鋳造材a、b、cの引張特性がど
の程度異なるかを示したものである。
同図に示す如く、加工材、/ 、 b/ 、 c/はい
ずれの組成においても、軟かく著しい伸びの改善が見ら
れる。この加工材’ +b 、Cは圧下率90%で冷間
圧延したシートから引張試験片を作成したのち、約1週
間位室温で熱処理したものである。つぎに第11図は9
5 Pb/ 5 Snはんだの鋳造材(第11図(a)
第10図(C)に相当)と、加工材(第11図(b)、
第10図(e′)に相当)の組織を比較したものである
。同図に示す如く、加工材の組織は鋳造材に比較して結
晶粒が細かく偏析して高濃度のSn相が球状化し、かつ
内部歪の少ないものになっている。この伸びは鋳造材の
3〜4倍で、加工・熱処理による特性改善の効果が理解
できる。
本発明者らは、上記の現象から、上記の加工材を接続材
料として使用することによシ、種々のストレスによる疲
労等に十分に耐えられる接続部が得られると想うに至っ
たのである。すなわち1加工材よシ低融点のはんだで、
加工材の接続端部のみを溶融接続することにより、加工
材のすぐれた靭性および延性を失なうことなく接続でき
るので、信頼性の高い接続ができ、かつこのような効果
が期待できる材料としては殆んどのろう材について可能
性があるからである。第12図はM、 HanBanに
よる1958年に発表されたPb−8n合金の状態図、
第13図は同じ(Pb−In合金の状態図、第14図は
同じ(Pb−8b合金の状態図である。これらの図から
明らかな如く、いずれも冷却凝固過程で偏析や不均質な
組織となり、これらを加工・熱処理すれば、伸び特性の
改善が期待できる。
以下本発明の一実施例を示す第1図乃至第3図について
説明する。第1図は本発明による接続構造を有する電子
回路装置の斜視図、第2図は第1図のA−A矢視断面図
を示す。第1図および第2図に示す如く、半導体チップ
1と、基板2との間に電極4.5を介して加工成形した
加工はんだ6を介挿し上記電極4,5に加工はんだ6よ
りも低融点のはんだ(図示せず)を付着し、このはんだ
のみを溶融して上記半導体チップ1と、基板2とをはん
だ6によシ接続するものである。
つぎに第3図によシその製造方法を述べると、まず、第
3図(a)に示す如く各種材料からなる基板2上に各々
の材料に適した方法で電極5を形成する。たとえば上記
基板2がアルミナセラミックで形成されている場合には
、Ag−PdおよびW等の導体ペーストを印刷、焼成し
て上記電極5を形成する。導体ペーストがWのときには
、さらにNiメッキ等を行なって電極5を形成する。こ
のようにして形成された電極5上に低融点のはんだたと
えばPb −SnあるいはAn−8n等の共晶はんだを
はんだペーストの印刷・リフ口やはんだボール、真空蒸
着等による供給・リフ口およびはんだディップによりは
んだ7を形成して回路基板を作成する。同様な方法で半
導体チップ1にも電極4に低融点のはんだ9を形成する
。ついで第3図(b)に示す如く、上記電極5の形状た
とえば円形、四角形、三角形等に対応する形状をした高
融点の加工はんだ8を形成する。すなわち、加工はんだ
8はたとえば95wt %Pb −5wt%Sn 、 
80wt% −20wt%Snを成形して、上記回路基
板2上の低融点はんだ7に一致させて載置する。
この状態で加熱し、低融点はんだ7のみを溶融して加工
はんだ8を電極5上に固定する。なお、上記加工はんだ
8は溶解・鋳造して版状に圧延したのち、90°圧下率
まで加工して50℃で2日間不活性雰囲気中で熱処理を
行なったもので、この引張特性は前記第1O図に示すC
′の特性に・略一致していた。ついで、第3図(e)に
示す如く上記半導体チップ1をそのはんだ4が上記加工
はんだ8に一致する如く載置したのち、低融点はんだ9
の融点よシもわずかに高い温度で加熱して加工はんだ8
の上部に溶融接続すると、第3図(d)に示す如く電子
回路装置を得ることができる。上記実施例では上記加工
はんだ8の形状は直径0.1511E11、長さ0.3
 mの円柱を用いている。また上記加工はんだ8の回路
基板2への供給方法は、電極5のパターンに対応して穴
の開いたステンレスマスクを使用している。
このようにして得られたはんだ接続部は、加工はんだ8
の融点が高く、体積も多いため、上記低融点はんだ7,
9と、溶融接続する加工はんだ8の領域が加〜Iμmと
非常にわずかであるため、殆んど加工はんだである。こ
れを温度サイクル−55〜+150℃、1サイクル/h
 r試験で寿命、を評価すると、疲労寿命は従来の鋳造
はんだに比較して95Pb−5Snはんだで5倍、80
 Au −20Snはんだで2倍であった。
同様な方法でセラミックパッケージされたICおよびコ
ンデンサ、抵抗等の面付は部品につい−Cも適用するこ
とができる。たとえば、第4図に示す如く、セラミック
基板10の素子取付用の凹部10aの中央部に載置され
モリブデン−マンガン層にニッケルメッキと金メッキ1
1を施したメタライズ層12と、このメタライズ層12
上に載置された半導体素子13と、上記凹部10aを除
くセラミック基板10上にモリブテン−マンガン層がメ
タライズされた内部リード14と、この内部リード14
および上記半導体素子13間を接続するワイヤボンドの
ワイヤ15と、上記セラミック基板10および該セラミ
ック基板10の上方部に配置された封止キャップ16間
を封止する封止部17とからなるセラミックパッケージ
18を基板2上に電極4,5を介してはんだ6で接続す
る場合、および第5図に示す如く、基板2上にコンデン
サあるいは抵抗体19を電極4,5を介してはんだ6で
接続するものにも適用できる。
この場合の疲労寿命特性を測定した結果、従来の鋳造材
に比較して3〜5倍の特性を示した。
つぎにI C、LSIの接続のように数百μmの端子が
数百端子必要になる場合にはこれらの端子に対応した加
工、熱処理はんだを供給することが問題になる。そこで
本発明はまづ微細加工によ多端子がバラバラになるのを
防止するため、第6図(、)に示す如く加工、熱処理し
たはんだシート加を硬化フラックス21(約100℃以
下で硬くなる)で裏打ちして補強したのち、ガラス板n
等に固定する。
なお、上記硬化スラックス21は後で容易に除去可能な
ものを使用する。またこの補強用材料は上記はんだシー
ト20よシも低融点のはんだをメッキ。
蒸着、圧延貼合せ等によシ供給しても良い。ついで第6
図(b)に示す如く、はんだシート加を数百μmのピッ
チにてワイヤソーあるいは放電加工法にて多数個に分割
切断し、その下方の硬化フラックス21を途中まで切断
して各はんだ柱6が固定された状態にする。然る後第6
図(c)に示す如く各はんだ柱6の端部をあらかじめ、
部品あるいは半導体チップ10対向端面にディップ等に
て供給された共晶はんだ等の低融点はんだおで接触させ
て低融点はんだnのみを溶解すると、全端子が部品に確
実に接続される。ついで、トリ7レン、イソプロピルア
ルコール等の溶剤にて硬化フラックス21を溶解して除
去したのち、部品もしくは半導体チップ1を回路基板2
に低融点はんだ(図示せず)で接続することによシ、多
数の細かい、熱処理はんだを溶解することなく、部品と
回路基板2に接続することができる。なお上記に述べた
はんだ供給方法は部品単位に限定されることなく、たと
えばSiウェハ全面の端子を一括加工して供給できるの
で、量産性に優れている。
つぎに本発明を電子回路装置における封止に実施した場
合を示す第7図および第8図について説明する。同図に
示す如く、回路基板2上に接続用はんだ冴にょシ接続す
る半導体チップ1およびコンデンサ等の部品を封止する
ため、上記半導体チップ1およびコンデンサ等の部品の
上方部を覆うように配置されたキャップδと、上記回路
基板2の周端部間に電極4,5を介して加工成形された
加工はんだ26を介挿し、上記電極4,5と加工はんだ
あとの間に該加工はんだ訪よりも低融点のはんだ(図示
せず)を付着し、この低融点のはんだのみを溶融して上
記キャップ部と回路基板2とを局所的に溶融接続したも
のである。なお、上記キャップ5、加工はんだあおよび
回路基板5にて封止された内部は真空があるいは不活性
ガスの雰囲気で部品を化学的に保護している。甘た上記
半導体チップ1訃よびコンデンサ等の部品を回路基板2
に接続するだめの接続用はんだあはキャップ6と、回路
基板2とを封止するさいに溶融しないように高融点のは
んだを使用している。さらに、この場合の電子回路装置
の製造方法は、前記第3図に述べた方法と同一である。
(発明の効果) 本発明は以上述べた如く、軟かく、かつ延性や疲労特性
のすぐれた加工はんだを用いて半導体および部品の接続
、封止を行なうことができるから、簡単な構成、容易な
操作によシ高信頼度の電子回路装置を得ることができ、
かつ今後増々高信頼度および高密度が要求される面付実
装の分野たとえば計算機等の電子回路装置の高機能化に
大きい貢献をすることができるものである。
【図面の簡単な説明】
第1図は本発明の一実施例を示す電子回路装置の斜視図
、第2図は第1図のA−A’断面図、第3図はその製造
過程を示す説明用断面図、第4図は本発明の他の一実施
例を示すセラミックパッケージの断面図、第5図は抵抗
器の面付は部品を示す断面図、第6図は加工はんだの供
給装置の製造過程を示す説明用斜視図、第7図は本発明
のさらに他の一実施例を示す電子回路装置の斜視図、第
8図は第7図のA −A’断面図、第9図は従来の電子
回路装置を示す斜視図、第10図は本発明に係る加工は
んだと従来のはんだとの引張特性図、第11図は本発明
に係る加工はんだと、従来の鋳造はんだの組織を示す図
面に代わる写真、第12図は本発明に係るPb −Sn
合金の状態図、第13図はPb−In合金の状態図、第
14図はpb−sb金合金状態図である。 1・・・半導体チップ、2・・・回路基板、3.7・・
・はんだ、4.5・・・電極、6,8.26・・・加工
はんだ、9.23・・・低融点はんだ、10・・・セラ
ミック基板、11・・・金メッキ、12・・・メタライ
ズ層、13・・・半導体素子、14・・・内部リード、
15・・・ワイヤ、16・・・封止キャップ、17・・
・封止部、18・・・セラミックパッケージ、19・・
・抵抗体、加・・・はんだシート、21・・・硬化フラ
ックスあるいは高融点のはんだ、n・・・ガラス板、冴
・・・接続用はんだ、5・・・キャップ。

Claims (1)

  1. 【特許請求の範囲】 1、導体パターンを有する部品を回路基板上にはんだで
    接続構成した電子回路装置において、上記はんだを加工
    熱処理した高融点のはんだおよび低融点のはんだとで形
    成し、この低融点のはんだの局部的溶融により高融点の
    はんだを、上記回路基板および部品に接続する如く構成
    したことを特徴とする電子回路装置。 2、前記高融点のはんだの形状を細長く形成したことを
    特徴とする前記特許請求の範囲第1項記載の電子回路装
    置。 3、前記高融点のはんだの形状を球状に形成したことを
    特徴とする前記特許請求の範囲第1項記載の電子回路装
    置。 4、前記高融点のはんだの形状を鼓状に形成したことを
    特徴とする前記特許請求の範囲第1項記載の電子回路装
    置。 5、導体パターンを有する部品と、回路基板とを有する
    部品と、回路基板と をはんだにより接続する電子回路装置の製造方法におい
    て、高融点のはんだと、上記部品および回路基板との間
    に低融点のはんだを介挿したのち、上記低融点はんだの
    み溶融しうる温度で加熱して低融点はんだのみ溶融して
    上記部品および回路基板を接続することを特徴とする回
    路基板装置の製造方法。 6、前記高融点のはんだを、予じめシート状に加工して
    、その一端面を溶解可能な当板に補強しその当板の1部
    を残して該シート状のはんだを接続部材形状に1体加工
    して、1体のまま接続部に供給してその端面に付着した
    低融点のはんだのみを溶解して回路基板もしくは部品に
    接続したことを特徴とする前記特許請求の範囲第5項記
    載の回路基板装置の製造方法。 7、前記回路基板上のはんだ接続部の導体パターンに一
    致して穴の開いたマスクを用いて前記高融点のはんだを
    上記回路基板と前記部品との間の所定位置に供給するこ
    とを特徴とする前記特許請求の範囲第6項記載の電子回
    路装置の製造方法。 8、メタライズを有する回路基板上の部品をキャップで
    封止する電子回路装置において、上記回路基板と、キャ
    ップとの間に低融点のはんだを介して高融点のはんだを
    介挿し、上記低融点のはんだを溶融によつて回路基板上
    の部品を封止するように構成したことを特徴とする電子
    回路装置。
JP59208072A 1984-10-05 1984-10-05 電子回路装置とその製造方法 Granted JPS6187396A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP59208072A JPS6187396A (ja) 1984-10-05 1984-10-05 電子回路装置とその製造方法
KR1019850006974A KR900000183B1 (ko) 1984-10-05 1985-09-24 전자회로 장치와 그 제조방법
DE8585112539T DE3581251D1 (de) 1984-10-05 1985-10-03 Elektronische schaltungsvorrichtung und verfahren zu ihrer herstellung.
EP85112539A EP0177042B1 (en) 1984-10-05 1985-10-03 Electronic circuit device and method of producing the same
US06/784,035 US4673772A (en) 1984-10-05 1985-10-04 Electronic circuit device and method of producing the same
CN85108637A CN85108637B (zh) 1984-10-05 1985-10-05 电子电路器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59208072A JPS6187396A (ja) 1984-10-05 1984-10-05 電子回路装置とその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4125018A Division JPH088408B2 (ja) 1992-05-18 1992-05-18 電子回路装置

Publications (2)

Publication Number Publication Date
JPS6187396A true JPS6187396A (ja) 1986-05-02
JPH0528000B2 JPH0528000B2 (ja) 1993-04-22

Family

ID=16550175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59208072A Granted JPS6187396A (ja) 1984-10-05 1984-10-05 電子回路装置とその製造方法

Country Status (6)

Country Link
US (1) US4673772A (ja)
EP (1) EP0177042B1 (ja)
JP (1) JPS6187396A (ja)
KR (1) KR900000183B1 (ja)
CN (1) CN85108637B (ja)
DE (1) DE3581251D1 (ja)

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Also Published As

Publication number Publication date
CN85108637A (zh) 1986-07-09
EP0177042B1 (en) 1991-01-09
CN85108637B (zh) 1988-03-09
KR860003756A (ko) 1986-05-28
EP0177042A2 (en) 1986-04-09
KR900000183B1 (ko) 1990-01-23
DE3581251D1 (de) 1991-02-14
EP0177042A3 (en) 1988-08-17
JPH0528000B2 (ja) 1993-04-22
US4673772A (en) 1987-06-16

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