DE69737748D1 - Laufzeitunterschiedverringerungsschaltung - Google Patents

Laufzeitunterschiedverringerungsschaltung

Info

Publication number
DE69737748D1
DE69737748D1 DE69737748T DE69737748T DE69737748D1 DE 69737748 D1 DE69737748 D1 DE 69737748D1 DE 69737748 T DE69737748 T DE 69737748T DE 69737748 T DE69737748 T DE 69737748T DE 69737748 D1 DE69737748 D1 DE 69737748D1
Authority
DE
Germany
Prior art keywords
reducing circuit
skew reducing
skew
circuit
reducing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69737748T
Other languages
English (en)
Other versions
DE69737748T2 (de
Inventor
Yoshinori Okajima
Tsuyoshi Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP12758397A external-priority patent/JP3708285B2/ja
Priority claimed from JP12758497A external-priority patent/JP3727753B2/ja
Priority claimed from JP12758297A external-priority patent/JP3708284B2/ja
Priority claimed from JP12976197A external-priority patent/JP3789598B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69737748D1 publication Critical patent/DE69737748D1/de
Application granted granted Critical
Publication of DE69737748T2 publication Critical patent/DE69737748T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE69737748T 1997-05-16 1997-11-10 Laufzeitunterschiedverringerungsschaltung Expired - Lifetime DE69737748T2 (de)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP12758397 1997-05-16
JP12758397A JP3708285B2 (ja) 1997-05-16 1997-05-16 スキュー低減回路と半導体装置
JP12758497A JP3727753B2 (ja) 1997-05-16 1997-05-16 スキュー低減回路と半導体装置
JP12758497 1997-05-16
JP12758297 1997-05-16
JP12758297A JP3708284B2 (ja) 1997-05-16 1997-05-16 スキュー低減回路と半導体装置
JP12976197 1997-05-20
JP12976197A JP3789598B2 (ja) 1997-05-20 1997-05-20 複数種類のスキューを低減する回路及び半導体装置

Publications (2)

Publication Number Publication Date
DE69737748D1 true DE69737748D1 (de) 2007-07-05
DE69737748T2 DE69737748T2 (de) 2008-01-31

Family

ID=27471312

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69737748T Expired - Lifetime DE69737748T2 (de) 1997-05-16 1997-11-10 Laufzeitunterschiedverringerungsschaltung

Country Status (4)

Country Link
US (1) US6114890A (de)
EP (1) EP0878910B1 (de)
KR (1) KR100381121B1 (de)
DE (1) DE69737748T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7187721B1 (en) * 2000-02-09 2007-03-06 Rambus Inc. Transition-time control in a high-speed data transmitter
GB2379142B (en) * 2001-08-24 2004-11-17 Fujitsu Ltd Distribution of signals in high speed digital circuitry
US7609778B2 (en) * 2001-12-20 2009-10-27 Richard S. Norman Methods, apparatus, and systems for reducing interference on nearby conductors
US6703868B2 (en) 2001-12-20 2004-03-09 Hyperchip Inc. Methods, apparatus, and systems for reducing interference on nearby conductors
US20030117183A1 (en) * 2001-12-20 2003-06-26 Claude Thibeault Methods, apparatus, and systems for reducing interference on nearby conductors
US6897497B2 (en) * 2001-12-20 2005-05-24 Hyperchip Inc. Methods, apparatus, and systems for reducing interference on nearby conductors
US7124314B2 (en) * 2002-11-05 2006-10-17 Ip-First, Llc Method and apparatus for fine tuning clock signals of an integrated circuit
JP4179884B2 (ja) * 2003-01-08 2008-11-12 株式会社東芝 動作テスト回路を含む半導体集積回路、および、その動作テスト方法
US6686862B1 (en) * 2003-02-21 2004-02-03 National Semiconductor Corporation Apparatus and method for duty cycle conversion
US6859109B1 (en) 2003-05-27 2005-02-22 Pericom Semiconductor Corp. Double-data rate phase-locked-loop with phase aligners to reduce clock skew
US7664216B2 (en) * 2004-08-05 2010-02-16 Micron Technology, Inc. Digital frequency locked delay line
US7216247B2 (en) * 2004-08-05 2007-05-08 Texas Instruments Incorporated Methods and systems to reduce data skew in FIFOs
KR100887016B1 (ko) * 2004-08-05 2009-03-04 마이크론 테크놀로지, 인크. 디지털 주파수 동기 지연선
US7496169B2 (en) * 2004-09-14 2009-02-24 Nippon Precision Circuits Inc. Frequency synthesizer, pulse train generation apparatus and pulse train generation method
EP1772795A1 (de) * 2005-10-10 2007-04-11 STMicroelectronics (Research & Development) Limited Schneller Pufferzeiger in einem Takt
KR100801058B1 (ko) * 2006-07-29 2008-02-04 삼성전자주식회사 스큐를 감소시키는 신호 전달 회로, 신호 전달 방법 및상기 회로를 구비하는 시스템
EP2119090A1 (de) * 2007-03-02 2009-11-18 Nxp B.V. Schnelles hochfahren eines datenkommunikationssystems
US8406361B2 (en) * 2007-03-20 2013-03-26 Nxp B.V. Fast powering-up of data communication system
US20080272817A1 (en) * 2007-05-04 2008-11-06 Niels Fricke Integrated Circuit on a Semiconductor Chip with a Phase Shift Circuit and a Method for Digital Phase Shifting
KR101418015B1 (ko) * 2008-02-20 2014-07-09 삼성전자주식회사 스큐 조정 회로 및 방법
MX2012013817A (es) * 2010-05-31 2013-01-28 663447 N B Inc Metodo y sistema para mejorar el ahorro de combustible y controlar las emisiones de motor.
TWI459360B (zh) * 2011-08-09 2014-11-01 Raydium Semiconductor Corp 自動調整訊號偏移的源極驅動裝置
JP5910383B2 (ja) * 2012-07-19 2016-04-27 株式会社ソシオネクスト スキュー低減回路
WO2015038867A1 (en) * 2013-09-16 2015-03-19 Rambus Inc. Source-synchronous receiver using edged-detection clock recovery
JP2017028489A (ja) * 2015-07-22 2017-02-02 富士通株式会社 スキュー補正回路、電子装置及びスキュー補正方法
US10276229B2 (en) * 2017-08-23 2019-04-30 Teradyne, Inc. Adjusting signal timing

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216524A (ja) * 1985-03-22 1986-09-26 Hitachi Ltd 位相同期検出回路
US5184027A (en) * 1987-03-20 1993-02-02 Hitachi, Ltd. Clock signal supply system
JPH02142215A (ja) * 1988-11-24 1990-05-31 Matsushita Electric Ind Co Ltd 位相調整装置
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
US5258660A (en) * 1990-01-16 1993-11-02 Cray Research, Inc. Skew-compensated clock distribution system
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
US5317202A (en) * 1992-05-28 1994-05-31 Intel Corporation Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle
US5369640A (en) * 1993-04-16 1994-11-29 Digital Equipment Corporation Method and apparatus for clock skew reduction through remote delay regulation
DE4427972C1 (de) * 1994-08-08 1995-07-27 Siemens Ag Integrierbare Taktrückgewinnungsschaltung
JPH08265349A (ja) * 1995-03-27 1996-10-11 Toshiba Microelectron Corp ディジタル情報処理装置
JP3639000B2 (ja) * 1995-06-13 2005-04-13 富士通株式会社 位相合わせ装置及び遅延制御回路

Also Published As

Publication number Publication date
KR19980086422A (ko) 1998-12-05
EP0878910A3 (de) 2004-08-04
US6114890A (en) 2000-09-05
DE69737748T2 (de) 2008-01-31
KR100381121B1 (ko) 2003-08-02
EP0878910B1 (de) 2007-05-23
EP0878910A2 (de) 1998-11-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE