DE69840993D1 - Synchrone Verzögerungsschaltung - Google Patents

Synchrone Verzögerungsschaltung

Info

Publication number
DE69840993D1
DE69840993D1 DE69840993T DE69840993T DE69840993D1 DE 69840993 D1 DE69840993 D1 DE 69840993D1 DE 69840993 T DE69840993 T DE 69840993T DE 69840993 T DE69840993 T DE 69840993T DE 69840993 D1 DE69840993 D1 DE 69840993D1
Authority
DE
Germany
Prior art keywords
delay circuit
synchronous delay
synchronous
circuit
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69840993T
Other languages
English (en)
Inventor
Takanori Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69840993D1 publication Critical patent/DE69840993D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
  • Networks Using Active Elements (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE69840993T 1997-10-03 1998-10-05 Synchrone Verzögerungsschaltung Expired - Lifetime DE69840993D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28774397A JP3434682B2 (ja) 1997-10-03 1997-10-03 同期遅延回路

Publications (1)

Publication Number Publication Date
DE69840993D1 true DE69840993D1 (de) 2009-09-03

Family

ID=17721190

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69840993T Expired - Lifetime DE69840993D1 (de) 1997-10-03 1998-10-05 Synchrone Verzögerungsschaltung

Country Status (7)

Country Link
US (1) US6222408B1 (de)
EP (1) EP0907251B1 (de)
JP (1) JP3434682B2 (de)
KR (1) KR100279389B1 (de)
CN (1) CN1144367C (de)
DE (1) DE69840993D1 (de)
TW (1) TW429682B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3415444B2 (ja) * 1998-06-12 2003-06-09 Ｎｅｃエレクトロニクス株式会社 クロック制御方法および回路
JP3386031B2 (ja) * 2000-03-06 2003-03-10 日本電気株式会社 同期遅延回路及び半導体集積回路装置
US6903592B2 (en) * 2003-01-22 2005-06-07 Promos Technologies Inc. Limited variable width internal clock generation
JP4480341B2 (ja) * 2003-04-10 2010-06-16 日立プラズマディスプレイ株式会社 プラズマディスプレイ装置
US6856270B1 (en) * 2004-01-29 2005-02-15 International Business Machines Corporation Pipeline array
US7084686B2 (en) * 2004-05-25 2006-08-01 Micron Technology, Inc. System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
JP4425722B2 (ja) 2004-06-18 2010-03-03 Ｎｅｃエレクトロニクス株式会社 Ｓｍｄ任意逓倍回路
JP2006067190A (ja) 2004-08-26 2006-03-09 Nec Electronics Corp クロック生成回路
US7078951B2 (en) * 2004-08-27 2006-07-18 Micron Technology, Inc. System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
JP2017220063A (ja) * 2016-06-08 2017-12-14 キヤノン株式会社 半導体集積回路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245231A (en) 1991-12-30 1993-09-14 Dell Usa, L.P. Integrated delay line
EP0720291B1 (de) 1994-12-20 2002-04-17 Nec Corporation Zeitverzögerungsschaltung
JP3672056B2 (ja) * 1995-08-18 2005-07-13 松下電器産業株式会社 タイミング信号発生回路

Also Published As

Publication number Publication date
EP0907251A2 (de) 1999-04-07
EP0907251B1 (de) 2009-07-22
JPH11112309A (ja) 1999-04-23
KR100279389B1 (ko) 2001-02-01
US6222408B1 (en) 2001-04-24
JP3434682B2 (ja) 2003-08-11
CN1144367C (zh) 2004-03-31
CN1213900A (zh) 1999-04-14
TW429682B (en) 2001-04-11
EP0907251A3 (de) 2001-01-17
KR19990036833A (ko) 1999-05-25

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