DE69732268D1 - Automatische Datenvorausladung in einem Rechnersystem - Google Patents
Automatische Datenvorausladung in einem RechnersystemInfo
- Publication number
- DE69732268D1 DE69732268D1 DE69732268T DE69732268T DE69732268D1 DE 69732268 D1 DE69732268 D1 DE 69732268D1 DE 69732268 T DE69732268 T DE 69732268T DE 69732268 T DE69732268 T DE 69732268T DE 69732268 D1 DE69732268 D1 DE 69732268D1
- Authority
- DE
- Germany
- Prior art keywords
- loading
- computer system
- data pre
- automatic data
- automatic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4054—Coupling between buses using bus bridges where the bridge performs a synchronising function where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US658496 | 1996-06-05 | ||
US08/658,496 US6075929A (en) | 1996-06-05 | 1996-06-05 | Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69732268D1 true DE69732268D1 (de) | 2005-02-24 |
DE69732268T2 DE69732268T2 (de) | 2005-06-30 |
Family
ID=24641474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69732268T Expired - Lifetime DE69732268T2 (de) | 1996-06-05 | 1997-06-04 | Automatische Datenvorausladung in einem Rechnersystem |
Country Status (4)
Country | Link |
---|---|
US (1) | US6075929A (de) |
EP (1) | EP0811937B1 (de) |
JP (1) | JPH10187597A (de) |
DE (1) | DE69732268T2 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6862635B1 (en) * | 1998-11-13 | 2005-03-01 | Cray Inc. | Synchronization techniques in a multithreaded environment |
FI107207B (fi) * | 1999-04-28 | 2001-06-15 | Nokia Networks Oy | Menetelmä, järjestelmä ja laite viallisen yksikön tunnistamiseksi |
US6625683B1 (en) * | 1999-08-23 | 2003-09-23 | Advanced Micro Devices, Inc. | Automatic early PCI transaction retry |
US7529799B2 (en) * | 1999-11-08 | 2009-05-05 | International Business Machines Corporation | Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system |
US7174401B2 (en) * | 2002-02-28 | 2007-02-06 | Lsi Logic Corporation | Look ahead split release for a data bus |
US7610329B2 (en) * | 2002-07-30 | 2009-10-27 | Storediq, Inc. | Method and apparatus for managing file systems and file-based data storage |
US7424562B2 (en) * | 2004-03-01 | 2008-09-09 | Cisco Technology, Inc. | Intelligent PCI bridging consisting of prefetching data based upon descriptor data |
US7238218B2 (en) * | 2004-04-06 | 2007-07-03 | International Business Machines Corporation | Memory prefetch method and system |
JP4912299B2 (ja) * | 2004-06-25 | 2012-04-11 | エヌヴィディア コーポレイション | 個別グラフィックスシステムおよび方法 |
US20060074872A1 (en) * | 2004-09-30 | 2006-04-06 | International Business Machines Corporation | Adaptive database buffer memory management using dynamic SQL statement cache statistics |
US7328312B2 (en) * | 2005-02-03 | 2008-02-05 | International Business Machines Corporation | Method and bus prefetching mechanism for implementing enhanced buffer control |
FR3046267B1 (fr) * | 2015-12-28 | 2018-02-16 | Proton World International N.V. | Stockage de donnees dans une memoire flash |
US10691519B2 (en) * | 2016-09-15 | 2020-06-23 | International Business Machines Corporation | Hang detection and recovery |
CN115480947A (zh) * | 2022-10-18 | 2022-12-16 | 超聚变数字技术有限公司 | 一种内存条故障检测装置及检测方法 |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5569830A (en) * | 1978-11-20 | 1980-05-26 | Toshiba Corp | Intelligent terminal |
EP0334627A3 (de) * | 1988-03-23 | 1991-06-12 | Du Pont Pixel Systems Limited | Multiprozessorbauweise |
JPH03188546A (ja) * | 1989-12-18 | 1991-08-16 | Fujitsu Ltd | バスインターフェイス制御方式 |
US5454093A (en) * | 1991-02-25 | 1995-09-26 | International Business Machines Corporation | Buffer bypass for quick data access |
US5483641A (en) * | 1991-12-17 | 1996-01-09 | Dell Usa, L.P. | System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities |
JPH0789340B2 (ja) * | 1992-01-02 | 1995-09-27 | インターナショナル・ビジネス・マシーンズ・コーポレイション | バス間インターフェースにおいてアドレス・ロケーションの判定を行なう方法及び装置 |
CA2080210C (en) * | 1992-01-02 | 1998-10-27 | Nader Amini | Bidirectional data storage facility for bus interface unit |
US5491811A (en) * | 1992-04-20 | 1996-02-13 | International Business Machines Corporation | Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory |
US5579530A (en) * | 1992-06-11 | 1996-11-26 | Intel Corporation | Method and apparatus for dynamically allocating access time to a resource shared between a peripheral bus and a host bus by dynamically controlling the size of burst data transfers on the peripheral bus |
JP2531903B2 (ja) * | 1992-06-22 | 1996-09-04 | インターナショナル・ビジネス・マシーンズ・コーポレイション | コンピュ―タ・システムおよびシステム拡張装置 |
US5463753A (en) * | 1992-10-02 | 1995-10-31 | Compaq Computer Corp. | Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller |
US5519839A (en) * | 1992-10-02 | 1996-05-21 | Compaq Computer Corp. | Double buffering operations between the memory bus and the expansion bus of a computer system |
US5535395A (en) * | 1992-10-02 | 1996-07-09 | Compaq Computer Corporation | Prioritization of microprocessors in multiprocessor computer systems |
US5381528A (en) * | 1992-10-15 | 1995-01-10 | Maxtor Corporation | Demand allocation of read/write buffer partitions favoring sequential read cache |
US5396602A (en) * | 1993-05-28 | 1995-03-07 | International Business Machines Corp. | Arbitration logic for multiple bus computer system |
US5522050A (en) * | 1993-05-28 | 1996-05-28 | International Business Machines Corporation | Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus |
US5623633A (en) * | 1993-07-27 | 1997-04-22 | Dell Usa, L.P. | Cache-based computer system employing a snoop control circuit with write-back suppression |
US5613075A (en) * | 1993-11-12 | 1997-03-18 | Intel Corporation | Method and apparatus for providing deterministic read access to main memory in a computer system |
US5455915A (en) * | 1993-12-16 | 1995-10-03 | Intel Corporation | Computer system with bridge circuitry having input/output multiplexers and third direct unidirectional path for data transfer between buses operating at different rates |
US5559800A (en) * | 1994-01-19 | 1996-09-24 | Research In Motion Limited | Remote control of gateway functions in a wireless data communication network |
US5471590A (en) * | 1994-01-28 | 1995-11-28 | Compaq Computer Corp. | Bus master arbitration circuitry having improved prioritization |
US5535341A (en) * | 1994-02-24 | 1996-07-09 | Intel Corporation | Apparatus and method for determining the status of data buffers in a bridge between two buses during a flush operation |
US5530933A (en) * | 1994-02-24 | 1996-06-25 | Hewlett-Packard Company | Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus |
SG47015A1 (en) * | 1994-02-24 | 1998-03-20 | Intel Corp | Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer |
TW400483B (en) * | 1994-03-01 | 2000-08-01 | Intel Corp | High performance symmetric arbitration protocol with support for I/O requirements |
US5528766A (en) * | 1994-03-24 | 1996-06-18 | Hewlett-Packard Company | Multiple arbitration scheme |
US5586297A (en) * | 1994-03-24 | 1996-12-17 | Hewlett-Packard Company | Partial cache line write transactions in a computing system with a write back cache |
US5623700A (en) * | 1994-04-06 | 1997-04-22 | Dell, Usa L.P. | Interface circuit having zero latency buffer memory and cache memory information transfer |
US5535340A (en) * | 1994-05-20 | 1996-07-09 | Intel Corporation | Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge |
US5546546A (en) * | 1994-05-20 | 1996-08-13 | Intel Corporation | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge |
US5687347A (en) * | 1994-09-19 | 1997-11-11 | Matsushita Electric Industrial Co., Ltd. | Data providing device, file server device, and data transfer control method |
US5548730A (en) * | 1994-09-20 | 1996-08-20 | Intel Corporation | Intelligent bus bridge for input/output subsystems in a computer system |
US5524235A (en) * | 1994-10-14 | 1996-06-04 | Compaq Computer Corporation | System for arbitrating access to memory with dynamic priority assignment |
US5553265A (en) * | 1994-10-21 | 1996-09-03 | International Business Machines Corporation | Methods and system for merging data during cache checking and write-back cycles for memory reads and writes |
US5555383A (en) * | 1994-11-07 | 1996-09-10 | International Business Machines Corporation | Peripheral component interconnect bus system having latency and shadow timers |
US5664124A (en) * | 1994-11-30 | 1997-09-02 | International Business Machines Corporation | Bridge between two buses of a computer system that latches signals from the bus for use on the bridge and responds according to the bus protocols |
US5625779A (en) * | 1994-12-30 | 1997-04-29 | Intel Corporation | Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge |
US5568619A (en) * | 1995-01-05 | 1996-10-22 | International Business Machines Corporation | Method and apparatus for configuring a bus-to-bus bridge |
US5630094A (en) * | 1995-01-20 | 1997-05-13 | Intel Corporation | Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions |
US5596729A (en) * | 1995-03-03 | 1997-01-21 | Compaq Computer Corporation | First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus |
US5664150A (en) * | 1995-03-21 | 1997-09-02 | International Business Machines Corporation | Computer system with a device for selectively blocking writebacks of data from a writeback cache to memory |
US5619661A (en) * | 1995-06-05 | 1997-04-08 | Vlsi Technology, Inc. | Dynamic arbitration system and method |
US5694556A (en) * | 1995-06-07 | 1997-12-02 | International Business Machines Corporation | Data processing system including buffering mechanism for inbound and outbound reads and posted writes |
US5634138A (en) * | 1995-06-07 | 1997-05-27 | Emulex Corporation | Burst broadcasting on a peripheral component interconnect bus |
US5710906A (en) * | 1995-07-07 | 1998-01-20 | Opti Inc. | Predictive snooping of cache memory for master-initiated accesses |
US5649175A (en) * | 1995-08-10 | 1997-07-15 | Cirrus Logic, Inc. | Method and apparatus for acquiring bus transaction address and command information with no more than zero-hold-time and with fast device acknowledgement |
US5632021A (en) * | 1995-10-25 | 1997-05-20 | Cisco Systems Inc. | Computer system with cascaded peripheral component interconnect (PCI) buses |
US5673399A (en) * | 1995-11-02 | 1997-09-30 | International Business Machines, Corporation | System and method for enhancement of system bus to mezzanine bus transactions |
US5717876A (en) * | 1996-02-26 | 1998-02-10 | International Business Machines Corporation | Method for avoiding livelock on bus bridge receiving multiple requests |
-
1996
- 1996-06-05 US US08/658,496 patent/US6075929A/en not_active Expired - Lifetime
-
1997
- 1997-06-04 DE DE69732268T patent/DE69732268T2/de not_active Expired - Lifetime
- 1997-06-04 EP EP97303808A patent/EP0811937B1/de not_active Expired - Lifetime
- 1997-06-05 JP JP9162075A patent/JPH10187597A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0811937A2 (de) | 1997-12-10 |
JPH10187597A (ja) | 1998-07-21 |
US6075929A (en) | 2000-06-13 |
EP0811937B1 (de) | 2005-01-19 |
DE69732268T2 (de) | 2005-06-30 |
EP0811937A3 (de) | 1998-07-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |