DE69810098T2 - Leseoperationen in einem multiprozessorrechnersystem - Google Patents

Leseoperationen in einem multiprozessorrechnersystem

Info

Publication number
DE69810098T2
DE69810098T2 DE69810098T DE69810098T DE69810098T2 DE 69810098 T2 DE69810098 T2 DE 69810098T2 DE 69810098 T DE69810098 T DE 69810098T DE 69810098 T DE69810098 T DE 69810098T DE 69810098 T2 DE69810098 T2 DE 69810098T2
Authority
DE
Germany
Prior art keywords
computer system
reading operations
multiprocessor computer
multiprocessor
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69810098T
Other languages
English (en)
Other versions
DE69810098D1 (de
Inventor
Kumar Arimilli
Steven Dodson
Michael Kaiser
Don Lewis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/839,479 external-priority patent/US5946709A/en
Priority claimed from US08/837,516 external-priority patent/US5940856A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69810098D1 publication Critical patent/DE69810098D1/de
Publication of DE69810098T2 publication Critical patent/DE69810098T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
DE69810098T 1997-04-14 1998-04-03 Leseoperationen in einem multiprozessorrechnersystem Expired - Lifetime DE69810098T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/839,479 US5946709A (en) 1997-04-14 1997-04-14 Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing
US08/837,516 US5940856A (en) 1997-04-14 1997-04-14 Cache intervention from only one of many cache lines sharing an unmodified value
PCT/GB1998/001002 WO1998047071A1 (en) 1997-04-14 1998-04-03 Read operations in multiprocessor computer system

Publications (2)

Publication Number Publication Date
DE69810098D1 DE69810098D1 (de) 2003-01-23
DE69810098T2 true DE69810098T2 (de) 2003-09-25

Family

ID=27125949

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69810098T Expired - Lifetime DE69810098T2 (de) 1997-04-14 1998-04-03 Leseoperationen in einem multiprozessorrechnersystem

Country Status (7)

Country Link
EP (1) EP0976047B1 (de)
CN (1) CN1215416C (de)
CA (1) CA2286364A1 (de)
DE (1) DE69810098T2 (de)
PL (1) PL336162A1 (de)
RU (1) RU2183850C2 (de)
WO (1) WO1998047071A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7496729B2 (en) * 2004-05-13 2009-02-24 International Business Machines Corporation Method and apparatus to eliminate interpartition covert storage channel and partition analysis
CN1328670C (zh) * 2005-03-30 2007-07-25 中国人民解放军国防科学技术大学 目录协议对多处理器结点内脏数据共享的支持方法
US20060253662A1 (en) * 2005-05-03 2006-11-09 Bass Brian M Retry cancellation mechanism to enhance system performance
US9639276B2 (en) * 2015-03-27 2017-05-02 Intel Corporation Implied directory state updates
CN107634916B (zh) * 2016-07-19 2020-11-03 大唐移动通信设备有限公司 一种数据通信方法和装置
US10713166B2 (en) * 2017-05-05 2020-07-14 Samsung Electronics Co., Ltd. Efficient early ordering mechanism
RU2672726C1 (ru) * 2017-11-27 2018-11-19 Общество с ограниченной ответственностью "РЭЙДИКС" Способ выполнения упреждающего чтения в системах хранения данных
CN113032298B (zh) * 2019-12-24 2023-09-29 中科寒武纪科技股份有限公司 用于保序的计算装置、集成电路装置、板卡及保序方法
CN113032299B (zh) * 2019-12-24 2023-09-26 中科寒武纪科技股份有限公司 用于处理请求的总线***、集成电路装置、板卡及保序方法
US11314637B2 (en) * 2020-05-29 2022-04-26 Hewlett Packard Enterprise Development Lp System and method for efficient cache coherency protocol processing

Also Published As

Publication number Publication date
WO1998047071A1 (en) 1998-10-22
RU2183850C2 (ru) 2002-06-20
CN1252142A (zh) 2000-05-03
CA2286364A1 (en) 1998-10-22
PL336162A1 (en) 2000-06-05
EP0976047B1 (de) 2002-12-11
CN1215416C (zh) 2005-08-17
EP0976047A1 (de) 2000-02-02
DE69810098D1 (de) 2003-01-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7