DE69727581D1 - RAM-Speicherzelle mit niedriger Leistungsaufnahme - Google Patents

RAM-Speicherzelle mit niedriger Leistungsaufnahme

Info

Publication number
DE69727581D1
DE69727581D1 DE69727581T DE69727581T DE69727581D1 DE 69727581 D1 DE69727581 D1 DE 69727581D1 DE 69727581 T DE69727581 T DE 69727581T DE 69727581 T DE69727581 T DE 69727581T DE 69727581 D1 DE69727581 D1 DE 69727581D1
Authority
DE
Germany
Prior art keywords
memory cell
power consumption
low power
ram memory
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69727581T
Other languages
English (en)
Inventor
Michael Tooher
Stefano Tonello
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69727581D1 publication Critical patent/DE69727581D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE69727581T 1997-11-28 1997-11-28 RAM-Speicherzelle mit niedriger Leistungsaufnahme Expired - Lifetime DE69727581D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97120943A EP0920025B1 (de) 1997-11-28 1997-11-28 RAM-Speicherzelle mit niedriger Leistungsaufnahme

Publications (1)

Publication Number Publication Date
DE69727581D1 true DE69727581D1 (de) 2004-03-18

Family

ID=8227704

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69727581T Expired - Lifetime DE69727581D1 (de) 1997-11-28 1997-11-28 RAM-Speicherzelle mit niedriger Leistungsaufnahme

Country Status (4)

Country Link
US (1) US6380592B2 (de)
EP (1) EP0920025B1 (de)
JP (1) JPH11232878A (de)
DE (1) DE69727581D1 (de)

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KR100460141B1 (ko) * 2002-07-08 2004-12-03 삼성전자주식회사 듀얼 포트 정적 메모리 셀 및 이 셀을 구비한 반도체메모리 장치
JP4219663B2 (ja) * 2002-11-29 2009-02-04 株式会社ルネサステクノロジ 半導体記憶装置及び半導体集積回路
JP2004356614A (ja) * 2003-05-08 2004-12-16 Renesas Technology Corp 半導体記憶装置
US6778462B1 (en) * 2003-05-08 2004-08-17 Lsi Logic Corporation Metal-programmable single-port SRAM array for dual-port functionality
US7006369B2 (en) 2003-08-27 2006-02-28 Lsi Logic Corporation Design and use of a spacer cell to support reconfigurable memories
US6934174B2 (en) * 2003-09-03 2005-08-23 Lsi Logic Corporation Reconfigurable memory arrays
US7724565B2 (en) * 2004-03-19 2010-05-25 International Business Machines Corporation Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices
US8566111B2 (en) * 2005-02-04 2013-10-22 The Invention Science Fund I, Llc Disposition of component virtual property rights
JP2006269674A (ja) 2005-03-23 2006-10-05 Nec Electronics Corp 半導体集積回路
KR100656452B1 (ko) 2005-11-29 2006-12-11 주식회사 하이닉스반도체 프리차지 장치
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7440313B2 (en) * 2006-11-17 2008-10-21 Freescale Semiconductor, Inc. Two-port SRAM having improved write operation
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
FR2932003B1 (fr) 2008-06-02 2011-03-25 Commissariat Energie Atomique Cellule de memoire sram a transistor integres sur plusieurs niveaux et dont la tension de seuil vt est ajustable dynamiquement
FR2932005B1 (fr) 2008-06-02 2011-04-01 Commissariat Energie Atomique Circuit a transistor integres dans trois dimensions et ayant une tension de seuil vt ajustable dynamiquement
WO2010008948A2 (en) 2008-07-16 2010-01-21 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
JPWO2010013449A1 (ja) * 2008-08-01 2012-01-05 パナソニック株式会社 半導体記憶装置
JP2011054255A (ja) 2009-09-04 2011-03-17 Panasonic Corp 半導体集積回路
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
JP6318088B2 (ja) 2011-07-26 2018-04-25 アンフォラ メディカル， インコーポレイテッド 骨盤神経組織を変調するための装置および方法
CN106999242A (zh) 2014-05-23 2017-08-01 安福拉医药公司 用于治疗骨盆病症的方法及装置
US9741452B2 (en) 2015-02-23 2017-08-22 Qualcomm Incorporated Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and related memory systems and methods
US9842634B2 (en) 2015-02-23 2017-12-12 Qualcomm Incorporated Wordline negative boost write-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) write port(s), and related systems and methods
US9940993B2 (en) * 2016-04-07 2018-04-10 Arm Limited Storage bitcell with isolation

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3971004A (en) * 1975-03-13 1976-07-20 Rca Corporation Memory cell with decoupled supply voltage while writing
JPS5856288A (ja) * 1981-09-28 1983-04-02 Toshiba Corp 半導体集積回路
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
JPS6038796A (ja) * 1983-08-12 1985-02-28 Hitachi Ltd 半導体集積回路装置
US4712194A (en) * 1984-06-08 1987-12-08 Matsushita Electric Industrial Co., Ltd. Static random access memory
JPS6124092A (ja) * 1984-07-13 1986-02-01 Toshiba Corp 半導体記憶装置
JPH01166391A (ja) * 1987-12-23 1989-06-30 Toshiba Corp スタティック型ランダムアクセスメモリ
JPH0682807B2 (ja) * 1988-09-12 1994-10-19 株式会社東芝 半導体メモリ
JPH0834059B2 (ja) * 1990-08-31 1996-03-29 三菱電機株式会社 半導体記憶装置
US5289432A (en) * 1991-04-24 1994-02-22 International Business Machines Corporation Dual-port static random access memory cell
US5301147A (en) * 1993-01-08 1994-04-05 Aptix Corporation Static random access memory cell with single logic-high voltage level bit-line and address-line drivers
JPH09120682A (ja) * 1995-10-24 1997-05-06 Mitsubishi Electric Corp 半導体メモリ装置

Also Published As

Publication number Publication date
JPH11232878A (ja) 1999-08-27
US6380592B2 (en) 2002-04-30
EP0920025A1 (de) 1999-06-02
US20020003244A1 (en) 2002-01-10
EP0920025B1 (de) 2004-02-11

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Legal Events

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