DE69525764D1 - Verfahren und struktur zur verwendung einer dram-matrix für einen zweite-stufe-cachespeicher - Google Patents

Verfahren und struktur zur verwendung einer dram-matrix für einen zweite-stufe-cachespeicher

Info

Publication number
DE69525764D1
DE69525764D1 DE69525764T DE69525764T DE69525764D1 DE 69525764 D1 DE69525764 D1 DE 69525764D1 DE 69525764 T DE69525764 T DE 69525764T DE 69525764 T DE69525764 T DE 69525764T DE 69525764 D1 DE69525764 D1 DE 69525764D1
Authority
DE
Germany
Prior art keywords
stage cache
dram matrix
dram
matrix
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69525764T
Other languages
English (en)
Other versions
DE69525764T2 (de
Inventor
Wingyu Leung
Fu-Chieh Hsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Technologies LLC
Original Assignee
Monolithic System Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Monolithic System Technology Inc filed Critical Monolithic System Technology Inc
Publication of DE69525764D1 publication Critical patent/DE69525764D1/de
Application granted granted Critical
Publication of DE69525764T2 publication Critical patent/DE69525764T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
DE69525764T 1994-11-22 1995-11-20 Verfahren und struktur zur verwendung einer dram-matrix für einen zweite-stufe-cachespeicher Expired - Lifetime DE69525764T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US34330694A 1994-11-22 1994-11-22
US44399895A 1995-05-17 1995-05-17
PCT/US1995/014552 WO1996016371A1 (en) 1994-11-22 1995-11-20 Method and structure for utilizing a dram array as second level cache memory

Publications (2)

Publication Number Publication Date
DE69525764D1 true DE69525764D1 (de) 2002-04-11
DE69525764T2 DE69525764T2 (de) 2002-10-31

Family

ID=26993415

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69525764T Expired - Lifetime DE69525764T2 (de) 1994-11-22 1995-11-20 Verfahren und struktur zur verwendung einer dram-matrix für einen zweite-stufe-cachespeicher

Country Status (4)

Country Link
EP (1) EP0793827B1 (de)
JP (1) JP3576561B2 (de)
DE (1) DE69525764T2 (de)
WO (1) WO1996016371A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990071604A (ko) 1996-09-26 1999-09-27 요트.게.아. 롤페즈 램구성내의정보를판독하고복원하기위한처리시스템및방법
TW360823B (en) 1996-09-30 1999-06-11 Hitachi Ltd Data processor and graphic processor
US5963481A (en) * 1998-06-30 1999-10-05 Enhanced Memory Systems, Inc. Embedded enhanced DRAM, and associated method
US6640266B2 (en) * 2000-03-24 2003-10-28 Cypress Semiconductor Corp. Method and device for performing write operations to synchronous burst memory
JP3951918B2 (ja) * 2000-06-23 2007-08-01 インテル・コーポレーション 不揮発性キャッシュ
JP4674865B2 (ja) * 2006-10-30 2011-04-20 株式会社日立製作所 半導体集積回路
US10394719B2 (en) * 2017-01-25 2019-08-27 Samsung Electronics Co., Ltd. Refresh aware replacement policy for volatile memory cache
CN113590520B (zh) * 2021-06-15 2024-05-03 珠海一微半导体股份有限公司 Spi***自动写入数据的控制方法及spi***

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4464715A (en) * 1982-02-24 1984-08-07 Daisy Systems Corporation Memory accessing method
DE69029122T2 (de) * 1989-06-16 1997-04-03 Advantest Corp Prüfmustergenerator
EP0454162B1 (de) * 1990-04-27 1996-09-25 Nec Corporation Halbleiterspeicheranordnung
JPH04172711A (ja) * 1990-11-06 1992-06-19 Mitsubishi Electric Corp 半導体遅延回路
US5249282A (en) * 1990-11-21 1993-09-28 Benchmarq Microelectronics, Inc. Integrated cache memory system with primary and secondary cache memories
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5537479A (en) * 1994-04-29 1996-07-16 Miller And Kreisel Sound Corp. Dual-driver bass speaker with acoustic reduction of out-of-phase and electronic reduction of in-phase distortion harmonics

Also Published As

Publication number Publication date
EP0793827A1 (de) 1997-09-10
JP3576561B2 (ja) 2004-10-13
EP0793827B1 (de) 2002-03-06
WO1996016371A1 (en) 1996-05-30
JPH11511872A (ja) 1999-10-12
DE69525764T2 (de) 2002-10-31
EP0793827A4 (de) 1998-04-15

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