DE69513469T2 - Silizium-auf-Isolator-Substrat und dessen Herstellungsverfahren - Google Patents

Silizium-auf-Isolator-Substrat und dessen Herstellungsverfahren

Info

Publication number
DE69513469T2
DE69513469T2 DE69513469T DE69513469T DE69513469T2 DE 69513469 T2 DE69513469 T2 DE 69513469T2 DE 69513469 T DE69513469 T DE 69513469T DE 69513469 T DE69513469 T DE 69513469T DE 69513469 T2 DE69513469 T2 DE 69513469T2
Authority
DE
Germany
Prior art keywords
silicon
manufacturing process
insulator substrate
insulator
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69513469T
Other languages
English (en)
Other versions
DE69513469D1 (de
Inventor
Kenya Kobayashi
Tomohiro Hamajima
Kensuke Okonogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69513469D1 publication Critical patent/DE69513469D1/de
Application granted granted Critical
Publication of DE69513469T2 publication Critical patent/DE69513469T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275Vertical isolation by bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286Lateral isolation by refilling of trenches with polycristalline material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/012Bonding, e.g. electrostatic for strain gauges

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
DE69513469T 1994-06-16 1995-06-14 Silizium-auf-Isolator-Substrat und dessen Herstellungsverfahren Expired - Fee Related DE69513469T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15645194 1994-06-16

Publications (2)

Publication Number Publication Date
DE69513469D1 DE69513469D1 (de) 1999-12-30
DE69513469T2 true DE69513469T2 (de) 2000-07-06

Family

ID=15628040

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69513469T Expired - Fee Related DE69513469T2 (de) 1994-06-16 1995-06-14 Silizium-auf-Isolator-Substrat und dessen Herstellungsverfahren

Country Status (5)

Country Link
US (2) US6004406A (de)
EP (1) EP0701286B1 (de)
KR (1) KR100223505B1 (de)
CN (1) CN1055789C (de)
DE (1) DE69513469T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09331049A (ja) * 1996-04-08 1997-12-22 Canon Inc 貼り合わせsoi基板の作製方法及びsoi基板
JPH1022184A (ja) * 1996-06-28 1998-01-23 Sony Corp 基板張り合わせ装置
JP3114643B2 (ja) * 1997-02-20 2000-12-04 日本電気株式会社 半導体基板の構造および製造方法
JPH11204452A (ja) 1998-01-13 1999-07-30 Mitsubishi Electric Corp 半導体基板の処理方法および半導体基板
US6071783A (en) * 1998-08-13 2000-06-06 Taiwan Semiconductor Manufacturing Company Pseudo silicon on insulator MOSFET device
KR20010079918A (ko) * 1998-09-25 2001-08-22 야마모토 카즈모토 반도체 기판과 그 제조 방법, 및 그것을 이용한 반도체디바이스와 그 제조 방법
US6635552B1 (en) 2000-06-12 2003-10-21 Micron Technology, Inc. Methods of forming semiconductor constructions
US6429070B1 (en) 2000-08-30 2002-08-06 Micron Technology, Inc. DRAM cell constructions, and methods of forming DRAM cells
US7608927B2 (en) 2002-08-29 2009-10-27 Micron Technology, Inc. Localized biasing for silicon on insulator structures
FR2847077B1 (fr) 2002-11-12 2006-02-17 Soitec Silicon On Insulator Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation
US6955988B2 (en) * 2003-12-04 2005-10-18 Analog Devices, Inc. Method of forming a cavity and SOI in a semiconductor substrate
EP1790004B1 (de) * 2004-09-02 2013-01-30 Imec Verfahren zur herstellung eines halbleiterbauelements und ein solches halbleiterbauelement
DE102006015076B4 (de) * 2006-03-31 2014-03-20 Advanced Micro Devices, Inc. Halbleiterbauelement mit SOI-Transistoren und Vollsubstrattransistoren und ein Verfahren zur Herstellung
WO2007126907A1 (en) * 2006-03-31 2007-11-08 Advanced Micro Devices, Inc. Semiconductor device comprising soi transistors and bulk transistors and a method of forming the same
FR2910702B1 (fr) * 2006-12-26 2009-04-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat mixte
CN101636832B (zh) 2007-03-19 2012-01-11 S.O.I.Tec绝缘体上硅技术公司 形成图案的薄soi
US8749018B2 (en) * 2010-06-21 2014-06-10 Infineon Technologies Ag Integrated semiconductor device having an insulating structure and a manufacturing method
FR2972564B1 (fr) 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0671043B2 (ja) * 1984-08-31 1994-09-07 株式会社東芝 シリコン結晶体構造の製造方法
JP2586422B2 (ja) * 1987-10-20 1997-02-26 日本電装株式会社 誘電体分離型複合集積回路装置の製造方法
US4963505A (en) * 1987-10-27 1990-10-16 Nippondenso Co., Ltd. Semiconductor device and method of manufacturing same
JPH025545A (ja) * 1988-06-24 1990-01-10 Nec Corp 半導体装置の製造方法
US4968628A (en) * 1988-12-09 1990-11-06 Harris Corporation Method of fabricating back diffused bonded oxide substrates
JPH0382138A (ja) * 1989-08-25 1991-04-08 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH0719839B2 (ja) * 1989-10-18 1995-03-06 株式会社東芝 半導体基板の製造方法
JPH07112007B2 (ja) * 1990-02-28 1995-11-29 株式会社日立製作所 誘電体分離基板およびその製造方法
JP2799035B2 (ja) * 1990-03-16 1998-09-17 富士通株式会社 半導体装置の製造方法
JPH0429353A (ja) * 1990-05-24 1992-01-31 Sharp Corp 半導体装置
JPH0582634A (ja) * 1991-06-26 1993-04-02 Fuji Electric Co Ltd 複合化半導体基板の製造方法
JPH0574667A (ja) * 1991-09-18 1993-03-26 Fujitsu Ltd 半導体装置の製造方法
JP3095268B2 (ja) 1991-09-20 2000-10-03 日立マクセル株式会社 有機電解液およびそれを使用した有機電解液電池
JP3416163B2 (ja) * 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
JP2766417B2 (ja) * 1992-02-10 1998-06-18 三菱マテリアル株式会社 貼り合わせ誘電体分離ウェーハの製造方法
JP3014012B2 (ja) * 1992-03-19 2000-02-28 日本電気株式会社 半導体装置の製造方法
JP3006387B2 (ja) * 1993-12-15 2000-02-07 日本電気株式会社 半導体装置およびその製造方法
US5374582A (en) * 1994-04-28 1994-12-20 Nec Corporation Laminated substrate for semiconductor device and manufacturing method thereof
JP2624186B2 (ja) * 1994-07-29 1997-06-25 日本電気株式会社 貼り合わせシリコン基板の製造方法

Also Published As

Publication number Publication date
US6004406A (en) 1999-12-21
EP0701286B1 (de) 1999-11-24
CN1055789C (zh) 2000-08-23
US5691231A (en) 1997-11-25
CN1117206A (zh) 1996-02-21
EP0701286A1 (de) 1996-03-13
KR100223505B1 (ko) 1999-10-15
DE69513469D1 (de) 1999-12-30
KR960002872A (ko) 1996-01-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee