DE69427209D1 - Anordnung und Verfahren zum Lesen von Mehrpegeldatensignalen in einem Halbleiterspeicher - Google Patents
Anordnung und Verfahren zum Lesen von Mehrpegeldatensignalen in einem HalbleiterspeicherInfo
- Publication number
- DE69427209D1 DE69427209D1 DE69427209T DE69427209T DE69427209D1 DE 69427209 D1 DE69427209 D1 DE 69427209D1 DE 69427209 T DE69427209 T DE 69427209T DE 69427209 T DE69427209 T DE 69427209T DE 69427209 D1 DE69427209 D1 DE 69427209D1
- Authority
- DE
- Germany
- Prior art keywords
- arrangement
- semiconductor memory
- data signals
- level data
- reading multi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19387693A JP3179943B2 (ja) | 1993-07-12 | 1993-07-12 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69427209D1 true DE69427209D1 (de) | 2001-06-21 |
DE69427209T2 DE69427209T2 (de) | 2001-10-11 |
Family
ID=16315220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69427209T Expired - Fee Related DE69427209T2 (de) | 1993-07-12 | 1994-07-12 | Anordnung und Verfahren zum Lesen von Mehrpegeldatensignalen in einem Halbleiterspeicher |
Country Status (7)
Country | Link |
---|---|
US (2) | US5457650A (de) |
EP (1) | EP0634750B1 (de) |
JP (1) | JP3179943B2 (de) |
KR (1) | KR0135698B1 (de) |
CN (1) | CN1038074C (de) |
DE (1) | DE69427209T2 (de) |
TW (1) | TW268129B (de) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5218569A (en) * | 1991-02-08 | 1993-06-08 | Banks Gerald J | Electrically alterable non-volatile memory with n-bits per memory cell |
US6002614A (en) | 1991-02-08 | 1999-12-14 | Btg International Inc. | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
US6353554B1 (en) | 1995-02-27 | 2002-03-05 | Btg International Inc. | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
JP2768321B2 (ja) * | 1995-02-28 | 1998-06-25 | 日本電気株式会社 | 半導体記憶装置 |
KR0182868B1 (ko) * | 1995-09-27 | 1999-04-15 | 김주용 | 플래쉬 메모리셀의 리페어 회로 및 리페어 방법 |
TW334566B (en) * | 1996-02-26 | 1998-06-21 | Sanyo Electric Co | Non-volatile semiconductor memory device |
US5748533A (en) * | 1996-03-26 | 1998-05-05 | Invoice Technology, Inc. | Read circuit which uses a coarse-to-fine search when reading the threshold voltage of a memory cell |
EP0904587B1 (de) * | 1996-06-14 | 2003-10-08 | Macronix International Co., Ltd. | Seitenmodus-schwebegatterspeicheranordnung mit mehrbitzellen |
US6857099B1 (en) * | 1996-09-18 | 2005-02-15 | Nippon Steel Corporation | Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program |
JP3093655B2 (ja) * | 1996-09-27 | 2000-10-03 | 日本電気アイシーマイコンシステム株式会社 | 多値マスクromのワード線駆動方法及びその駆動回路 |
KR100226746B1 (ko) * | 1996-12-30 | 1999-10-15 | 구본준 | 다중비트셀의데이타센싱장치및방법 |
US6137726A (en) * | 1997-11-25 | 2000-10-24 | Samsung Electronics Co., Ltd. | Multi-level memory devices having memory cell referenced word line voltage generations |
KR100282707B1 (ko) * | 1997-12-29 | 2001-02-15 | 윤종용 | 멀티-비트 데이터를 저장하는 반도체 메모리 장치 (semiconductor memory device for storing a multi-bit data) |
KR100266744B1 (ko) * | 1997-12-29 | 2000-09-15 | 윤종용 | 고집적 가능한 멀티-비트 데이터 래치 회로를 갖는 반도체 메모리 장치 |
KR100283029B1 (ko) * | 1997-12-29 | 2001-03-02 | 윤종용 | 반도체 메모리 장치의 워드 라인 전압 발생 회로 |
KR100266748B1 (ko) | 1997-12-31 | 2000-10-02 | 윤종용 | 반도체 메모리 장치 및 그 장치의 에러 정정 방법 |
US6279133B1 (en) | 1997-12-31 | 2001-08-21 | Kawasaki Steel Corporation | Method and apparatus for significantly improving the reliability of multilevel memory architecture |
US5896337A (en) | 1998-02-23 | 1999-04-20 | Micron Technology, Inc. | Circuits and methods for multi-level data through a single input/ouput pin |
JPH11283386A (ja) * | 1998-03-31 | 1999-10-15 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
US6178114B1 (en) | 1999-01-12 | 2001-01-23 | Macronix International Co., Ltd. | Sensing apparatus and method for fetching multi-level cell data |
KR100291897B1 (ko) | 1999-03-11 | 2001-06-01 | 윤종용 | 버스트 모드 액세스를 구비한 반도체 메모리 장치 |
US6305095B1 (en) | 2000-02-25 | 2001-10-23 | Xilinx, Inc. | Methods and circuits for mask-alignment detection |
US6424569B1 (en) | 2000-02-25 | 2002-07-23 | Advanced Micro Devices, Inc. | User selectable cell programming |
US6684520B1 (en) | 2000-02-25 | 2004-02-03 | Xilinx, Inc. | Mask-alignment detection circuit in x and y directions |
US6563320B1 (en) | 2000-02-25 | 2003-05-13 | Xilinx, Inc. | Mask alignment structure for IC layers |
US6297988B1 (en) | 2000-02-25 | 2001-10-02 | Advanced Micro Devices, Inc. | Mode indicator for multi-level memory |
US6205055B1 (en) | 2000-02-25 | 2001-03-20 | Advanced Micro Devices, Inc. | Dynamic memory cell programming voltage |
US6219276B1 (en) | 2000-02-25 | 2001-04-17 | Advanced Micro Devices, Inc. | Multilevel cell programming |
US6707713B1 (en) | 2000-03-01 | 2004-03-16 | Advanced Micro Devices, Inc. | Interlaced multi-level memory |
JP4467815B2 (ja) | 2001-02-26 | 2010-05-26 | 富士通マイクロエレクトロニクス株式会社 | 不揮発性半導体メモリの読み出し動作方法および不揮発性半導体メモリ |
US6891745B2 (en) * | 2002-11-08 | 2005-05-10 | Taiwan Semiconductor Manufacturing Company | Design concept for SRAM read margin |
US20050035429A1 (en) * | 2003-08-15 | 2005-02-17 | Yeh Chih Chieh | Programmable eraseless memory |
US7180123B2 (en) * | 2003-07-21 | 2007-02-20 | Macronix International Co., Ltd. | Method for programming programmable eraseless memory |
US7132350B2 (en) | 2003-07-21 | 2006-11-07 | Macronix International Co., Ltd. | Method for manufacturing a programmable eraseless memory |
CN100343920C (zh) * | 2004-07-14 | 2007-10-17 | 义隆电子股份有限公司 | 适用字符线金属导线技术的平面单元只读存储器 |
US7145816B2 (en) * | 2004-08-16 | 2006-12-05 | Micron Technology, Inc. | Using redundant memory for extra features |
WO2006051455A1 (en) * | 2004-11-09 | 2006-05-18 | Koninklijke Philips Electronics N.V. | Memory integrated circuit |
KR100684873B1 (ko) * | 2004-11-22 | 2007-02-20 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 워드라인 전압 제어 방법 |
JP4203489B2 (ja) * | 2005-03-16 | 2009-01-07 | シャープ株式会社 | 半導体記憶装置 |
KR100680479B1 (ko) | 2005-04-11 | 2007-02-08 | 주식회사 하이닉스반도체 | 비휘발성 메모리 장치의 프로그램 검증 방법 |
US7257046B2 (en) * | 2005-06-13 | 2007-08-14 | Atmel Corporation | Memory data access scheme |
KR100706797B1 (ko) * | 2005-08-23 | 2007-04-12 | 삼성전자주식회사 | 각각의 워드 라인에 다른 레벨의 소거 전압을 인가하는낸드 플래시 메모리 장치 |
KR100714823B1 (ko) * | 2005-09-09 | 2007-05-07 | 주식회사 엑셀반도체 | 다치 에스램 |
US7400527B2 (en) * | 2006-03-16 | 2008-07-15 | Flashsilicon, Inc. | Bit symbol recognition method and structure for multiple bit storage in non-volatile memories |
JP2010073275A (ja) * | 2008-09-19 | 2010-04-02 | Spansion Llc | 半導体装置およびデータ読み出し方法 |
JP2010140554A (ja) * | 2008-12-11 | 2010-06-24 | Samsung Electronics Co Ltd | 不揮発性半導体記憶装置の読出し方法 |
US8248855B2 (en) * | 2010-03-10 | 2012-08-21 | Infinite Memories Ltd. | Method of handling reference cells in NVM arrays |
JP5355667B2 (ja) * | 2011-11-21 | 2013-11-27 | 株式会社東芝 | メモリシステム |
JP2012109022A (ja) * | 2012-03-07 | 2012-06-07 | Nippon Telegr & Teleph Corp <Ntt> | 読み出し装置 |
CN103325413B (zh) * | 2012-03-21 | 2016-03-23 | 旺宏电子股份有限公司 | 具有寻址及相邻位的存储单元的集成电路及其操作方法 |
CN114817092A (zh) * | 2022-04-13 | 2022-07-29 | 苏州菲斯力芯软件有限公司 | 一种高存储密度的多状态rom电路 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5671965A (en) * | 1979-11-19 | 1981-06-15 | Nec Corp | Semiconductor device |
JPS603711B2 (ja) * | 1980-04-30 | 1985-01-30 | 沖電気工業株式会社 | 読み出し専用記憶装置 |
JPS5769259A (en) * | 1980-10-17 | 1982-04-27 | Toshiba Corp | Voltage detecting circuit |
JPS5794990A (en) * | 1980-12-03 | 1982-06-12 | Seiko Epson Corp | Data rom |
CA1167963A (en) * | 1980-12-24 | 1984-05-22 | Mostek Corporation | Multi-bit read only memory cell sensing circuit |
JPS57120299A (en) * | 1981-01-17 | 1982-07-27 | Sanyo Electric Co Ltd | Read-only memory |
US4404655A (en) * | 1981-01-28 | 1983-09-13 | General Instrument Corporation | Data sense apparatus for use in multi-threshold read only memory |
JPS57153582A (en) * | 1981-03-18 | 1982-09-22 | Matsushita Electric Ind Co Ltd | Speed controller for dc motor |
JPS57181497A (en) * | 1981-04-30 | 1982-11-08 | Ricoh Co Ltd | Read only memory |
JPS5888672A (ja) * | 1981-11-24 | 1983-05-26 | Hitachi Ltd | 入力しきい電圧自動測定回路 |
JPS58181497A (ja) * | 1982-04-19 | 1983-10-24 | Kobe Steel Ltd | 被覆成形用押出装置の脱気方法 |
EP0148488B1 (de) * | 1983-12-23 | 1992-03-18 | Hitachi, Ltd. | Halbleiterspeicher mit einer Speicherstruktur mit vielfachen Pegeln |
JPH06101534B2 (ja) * | 1985-08-09 | 1994-12-12 | 三菱電機株式会社 | 半導体集積回路の内部電源電圧発生回路 |
US5293560A (en) * | 1988-06-08 | 1994-03-08 | Eliyahou Harari | Multi-state flash EEPROM system using incremental programing and erasing methods |
US5172338B1 (en) * | 1989-04-13 | 1997-07-08 | Sandisk Corp | Multi-state eeprom read and write circuits and techniques |
US5132935A (en) * | 1990-04-16 | 1992-07-21 | Ashmore Jr Benjamin H | Erasure of eeprom memory arrays to prevent over-erased cells |
KR940006611B1 (ko) * | 1990-08-20 | 1994-07-23 | 삼성전자 주식회사 | 전기적으로 소거 및 프로그램이 가능한 반도체 메모리장치의 자동 소거 최적화회로 및 방법 |
JPH04172698A (ja) * | 1990-11-05 | 1992-06-19 | Nec Kyushu Ltd | 半導体集積回路 |
US5218569A (en) * | 1991-02-08 | 1993-06-08 | Banks Gerald J | Electrically alterable non-volatile memory with n-bits per memory cell |
US5335198A (en) * | 1993-05-06 | 1994-08-02 | Advanced Micro Devices, Inc. | Flash EEPROM array with high endurance |
-
1993
- 1993-07-12 JP JP19387693A patent/JP3179943B2/ja not_active Expired - Fee Related
-
1994
- 1994-07-06 TW TW083106173A patent/TW268129B/zh active
- 1994-07-08 US US08/272,682 patent/US5457650A/en not_active Expired - Lifetime
- 1994-07-12 DE DE69427209T patent/DE69427209T2/de not_active Expired - Fee Related
- 1994-07-12 EP EP94110810A patent/EP0634750B1/de not_active Expired - Lifetime
- 1994-07-12 KR KR1019940016937A patent/KR0135698B1/ko not_active IP Right Cessation
- 1994-07-12 CN CN94108259A patent/CN1038074C/zh not_active Expired - Fee Related
-
1997
- 1997-03-18 US US08/819,052 patent/US5852575A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1038074C (zh) | 1998-04-15 |
KR0135698B1 (ko) | 1998-05-15 |
EP0634750A3 (de) | 1996-01-10 |
JPH0729383A (ja) | 1995-01-31 |
EP0634750A2 (de) | 1995-01-18 |
KR950004286A (ko) | 1995-02-17 |
US5852575A (en) | 1998-12-22 |
DE69427209T2 (de) | 2001-10-11 |
TW268129B (de) | 1996-01-11 |
EP0634750B1 (de) | 2001-05-16 |
US5457650A (en) | 1995-10-10 |
CN1102499A (zh) | 1995-05-10 |
JP3179943B2 (ja) | 2001-06-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |