DE69216267D1 - Multiport-Speicher - Google Patents

Multiport-Speicher

Info

Publication number
DE69216267D1
DE69216267D1 DE69216267T DE69216267T DE69216267D1 DE 69216267 D1 DE69216267 D1 DE 69216267D1 DE 69216267 T DE69216267 T DE 69216267T DE 69216267 T DE69216267 T DE 69216267T DE 69216267 D1 DE69216267 D1 DE 69216267D1
Authority
DE
Germany
Prior art keywords
multiport memory
multiport
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69216267T
Other languages
English (en)
Other versions
DE69216267T2 (de
Inventor
Keizo Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69216267D1 publication Critical patent/DE69216267D1/de
Publication of DE69216267T2 publication Critical patent/DE69216267T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
DE69216267T 1991-03-19 1992-03-19 Multiport-Speicher Expired - Fee Related DE69216267T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5504491 1991-03-19

Publications (2)

Publication Number Publication Date
DE69216267D1 true DE69216267D1 (de) 1997-02-13
DE69216267T2 DE69216267T2 (de) 1997-09-25

Family

ID=12987671

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69216267T Expired - Fee Related DE69216267T2 (de) 1991-03-19 1992-03-19 Multiport-Speicher

Country Status (4)

Country Link
US (1) US5335199A (de)
EP (1) EP0505926B1 (de)
KR (1) KR960004735B1 (de)
DE (1) DE69216267T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994007200A1 (en) * 1992-09-21 1994-03-31 Unisys Corporation Multiported buffer memory system for disk drive complex
US5710742A (en) * 1995-05-12 1998-01-20 International Business Machines Corporation High density two port SRAM cell for low voltage CMOS applications
US5719890A (en) * 1995-06-01 1998-02-17 Micron Technology, Inc. Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM
US5836007A (en) * 1995-09-14 1998-11-10 International Business Machines Corporation Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles
US5642325A (en) * 1995-09-27 1997-06-24 Philips Electronics North America Corporation Register file read/write cell
US5828623A (en) * 1996-02-23 1998-10-27 Integrated Device Technology, Inc. Parallel write logic for multi-port memory arrays
US6487207B1 (en) 1997-02-26 2002-11-26 Micron Technology, Inc. Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology
US5978889A (en) * 1997-11-05 1999-11-02 Timeplex, Inc. Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception
US6198684B1 (en) * 1999-12-23 2001-03-06 Intel Corporation Word line decoder for dual-port cache memory
US6594194B2 (en) * 2001-07-11 2003-07-15 Sun Microsystems, Inc. Memory array with common word line
US6938111B2 (en) * 2002-04-19 2005-08-30 Siemens Aktiengesellschaft Method for operating automation control equipment applications
JP2006134379A (ja) * 2004-11-02 2006-05-25 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR100655081B1 (ko) * 2005-12-22 2006-12-08 삼성전자주식회사 가변적 액세스 경로를 가지는 멀티 포트 반도체 메모리장치 및 그에 따른 방법
KR100745374B1 (ko) * 2006-02-21 2007-08-02 삼성전자주식회사 멀티포트 반도체 메모리 장치 및 그에 따른 신호 입출력방법
US7564735B2 (en) * 2006-07-05 2009-07-21 Qimonda Ag Memory device, and method for operating a memory device
KR101475346B1 (ko) * 2008-07-02 2014-12-23 삼성전자주식회사 비트라인 쌍의 디벨롭 레벨을 클립핑하는 디벨롭 레벨클리핑 회로, 이를 포함하는 컬럼 경로 회로 및 멀티 포트반도체 메모리 장치
JP2011258270A (ja) 2010-06-09 2011-12-22 Renesas Electronics Corp 半導体記憶装置
US9171594B2 (en) * 2012-07-19 2015-10-27 Arm Limited Handling collisions between accesses in multiport memories
US8867263B2 (en) * 2013-01-14 2014-10-21 Freescale Semiconductor, Inc. Multiport memory with matching address and data line control
US8861289B2 (en) * 2013-01-14 2014-10-14 Freescale Semiconductor, Inc. Multiport memory with matching address control
US10885973B2 (en) * 2018-07-31 2021-01-05 Taiwan Semiconductor Manufacturing Company Ltd. Memory device and method of controlling memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07111822B2 (ja) * 1986-03-07 1995-11-29 株式会社日立製作所 半導体記憶装置
JPH07107792B2 (ja) * 1988-01-19 1995-11-15 株式会社東芝 マルチポートメモリ
US5053652A (en) * 1988-01-28 1991-10-01 Hitachi, Ltd. High speed sensor system using a level shift circuit
JP2613257B2 (ja) * 1988-05-24 1997-05-21 株式会社日立製作所 多ポートｒａｍ
KR0141494B1 (ko) * 1988-01-28 1998-07-15 미다 가쓰시게 레벨시프트회로를 사용한 고속센스 방식의 반도체장치
JPH023164A (ja) * 1988-06-16 1990-01-08 Sharp Corp デュアル・ポート・メモリ
JP2600304B2 (ja) * 1988-06-30 1997-04-16 三菱電機株式会社 半導体記憶装置とこれを用いたデータパス
JP2891504B2 (ja) * 1990-03-13 1999-05-17 三菱電機株式会社 マルチポートメモリ

Also Published As

Publication number Publication date
EP0505926B1 (de) 1997-01-02
DE69216267T2 (de) 1997-09-25
KR960004735B1 (ko) 1996-04-12
KR920018753A (ko) 1992-10-22
EP0505926A1 (de) 1992-09-30
US5335199A (en) 1994-08-02

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8339 Ceased/non-payment of the annual fee