DE68902185D1 - Modularer speicher. - Google Patents

Modularer speicher.

Info

Publication number
DE68902185D1
DE68902185D1 DE8989401392T DE68902185T DE68902185D1 DE 68902185 D1 DE68902185 D1 DE 68902185D1 DE 8989401392 T DE8989401392 T DE 8989401392T DE 68902185 T DE68902185 T DE 68902185T DE 68902185 D1 DE68902185 D1 DE 68902185D1
Authority
DE
Germany
Prior art keywords
modular storage
modular
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8989401392T
Other languages
English (en)
Other versions
DE68902185T2 (de
Inventor
Georges Keryvel
Jean-Louis Thomas
Claude Timsit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SAS
Original Assignee
Bull SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SAS filed Critical Bull SAS
Application granted granted Critical
Publication of DE68902185D1 publication Critical patent/DE68902185D1/de
Publication of DE68902185T2 publication Critical patent/DE68902185T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
DE8989401392T 1988-05-25 1989-05-22 Modularer speicher. Expired - Fee Related DE68902185T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8806910A FR2632093B1 (fr) 1988-05-25 1988-05-25 Memoire modulaire

Publications (2)

Publication Number Publication Date
DE68902185D1 true DE68902185D1 (de) 1992-08-27
DE68902185T2 DE68902185T2 (de) 1993-01-21

Family

ID=9366572

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8989401392T Expired - Fee Related DE68902185T2 (de) 1988-05-25 1989-05-22 Modularer speicher.

Country Status (5)

Country Link
US (1) US5175832A (de)
EP (1) EP0344052B1 (de)
JP (1) JPH0218639A (de)
DE (1) DE68902185T2 (de)
FR (1) FR2632093B1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5249301A (en) * 1988-10-25 1993-09-28 Bull S.A Processing communication system having a plurality of memories and processors coupled through at least one feedback shift register provided from ring configured input stations
JPH05274273A (ja) * 1991-06-28 1993-10-22 Digital Equip Corp <Dec> コンピュータ・システムに於ける素子のインターロック・スキーム
FR2820874B1 (fr) * 2001-02-13 2003-05-30 St Microelectronics Sa Procede de gestion a acces aleatoire et rapide d'une memoire dram
US9021482B2 (en) * 2007-05-04 2015-04-28 International Business Machines Corporation Reordering data responses using ordered indicia in a linked list
JP7476676B2 (ja) * 2020-06-04 2024-05-01 富士通株式会社 演算処理装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3566363A (en) * 1968-07-11 1971-02-23 Ibm Processor to processor communication in a multiprocessor computer system
US4156288A (en) * 1978-06-13 1979-05-22 Sperry Rand Corporation Asynchronous shift register with turnpike feature
IT1118355B (it) * 1979-02-15 1986-02-24 Cselt Centro Studi Lab Telecom Sistema di interconnessione tra processori
US4491915A (en) * 1982-11-30 1985-01-01 Rca Corporation Multiprocessor-memory data transfer network
US4809232A (en) * 1986-12-16 1989-02-28 The United States Of America As Represented By The United States Department Of Energy High speed, very large (8 megabyte) first in/first out buffer memory (FIFO)
JPH0760594B2 (ja) * 1987-06-25 1995-06-28 富士通株式会社 半導体記憶装置
US4918600A (en) * 1988-08-01 1990-04-17 Board Of Regents, University Of Texas System Dynamic address mapping for conflict-free vector access

Also Published As

Publication number Publication date
DE68902185T2 (de) 1993-01-21
JPH0218639A (ja) 1990-01-22
US5175832A (en) 1992-12-29
FR2632093A1 (fr) 1989-12-01
FR2632093B1 (fr) 1990-08-10
EP0344052B1 (de) 1992-07-22
EP0344052A1 (de) 1989-11-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee