DE68902193D1 - Datenspeicheranordnung. - Google Patents
Datenspeicheranordnung.Info
- Publication number
- DE68902193D1 DE68902193D1 DE8989304836T DE68902193T DE68902193D1 DE 68902193 D1 DE68902193 D1 DE 68902193D1 DE 8989304836 T DE8989304836 T DE 8989304836T DE 68902193 T DE68902193 T DE 68902193T DE 68902193 D1 DE68902193 D1 DE 68902193D1
- Authority
- DE
- Germany
- Prior art keywords
- data storage
- storage arrangement
- arrangement
- data
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB888814077A GB8814077D0 (en) | 1988-06-14 | 1988-06-14 | Data memory system |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68902193D1 true DE68902193D1 (de) | 1992-08-27 |
DE68902193T2 DE68902193T2 (de) | 1993-02-04 |
Family
ID=10638633
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8989304836T Expired - Fee Related DE68902193T2 (de) | 1988-06-14 | 1989-05-12 | Datenspeicheranordnung. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5146603A (de) |
EP (1) | EP0347040B1 (de) |
AU (1) | AU608447B2 (de) |
DE (1) | DE68902193T2 (de) |
GB (1) | GB8814077D0 (de) |
ZA (1) | ZA893785B (de) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5287512A (en) * | 1990-08-06 | 1994-02-15 | Ncr Corporation | Computer memory system and method for cleaning data elements |
US5303362A (en) * | 1991-03-20 | 1994-04-12 | Digital Equipment Corporation | Coupled memory multiprocessor computer system including cache coherency management protocols |
EP0510242A2 (de) * | 1991-04-22 | 1992-10-28 | Acer Incorporated | Anordnung und Verfahren zur Verwaltung der Leitweglenkungsausführung in einer Rechneranordnung |
US5319768A (en) * | 1991-05-01 | 1994-06-07 | Sgs-Thomson Microelectronics, Inc. | Control circuit for resetting a snoop valid bit in a dual port cache tag memory |
US5396604A (en) * | 1991-07-12 | 1995-03-07 | Hewlett-Packard Company | System and method for reducing the penalty associated with data cache misses |
US5335335A (en) * | 1991-08-30 | 1994-08-02 | Compaq Computer Corporation | Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed |
US5530835A (en) * | 1991-09-18 | 1996-06-25 | Ncr Corporation | Computer memory data merging technique for computers with write-back caches |
US5301298A (en) * | 1991-10-11 | 1994-04-05 | Intel Corporation | Processor for multiple cache coherent protocols |
GB2260429B (en) * | 1991-10-11 | 1995-05-24 | Intel Corp | Versatile cache memory |
US5371872A (en) * | 1991-10-28 | 1994-12-06 | International Business Machines Corporation | Method and apparatus for controlling operation of a cache memory during an interrupt |
US5724549A (en) * | 1992-04-06 | 1998-03-03 | Cyrix Corporation | Cache coherency without bus master arbitration signals |
US5524212A (en) * | 1992-04-27 | 1996-06-04 | University Of Washington | Multiprocessor system with write generate method for updating cache |
KR100294105B1 (ko) * | 1992-04-29 | 2001-09-17 | 썬 마이크로시스템즈, 인코포레이티드 | 멀티 프로세서 컴퓨터 시스템의 일관성 카피-백 버퍼용 방법 및 장치 |
JPH0667980A (ja) * | 1992-05-12 | 1994-03-11 | Unisys Corp | 4ブロックキャッシュメモリへのアクセスを最適化するためのキャッシュ論理システムおよびメインフレームコンピュータの高速キャッシュメモリへのアクセス時のダブルミスを防ぐ方法 |
US5675763A (en) * | 1992-07-15 | 1997-10-07 | Digital Equipment Corporation | Cache memory system and method for selectively removing stale aliased entries |
ATE186411T1 (de) * | 1992-08-19 | 1999-11-15 | Siemens Nixdorf Inf Syst | Multiprozessorsystem mit cache-speichern |
US5522057A (en) * | 1993-10-25 | 1996-05-28 | Intel Corporation | Hybrid write back/write through cache having a streamlined four state cache coherency protocol for uniprocessor computer systems |
US5581704A (en) * | 1993-12-06 | 1996-12-03 | Panasonic Technologies, Inc. | System for maintaining data coherency in cache memory by periodically broadcasting invalidation reports from server to client |
US5586297A (en) * | 1994-03-24 | 1996-12-17 | Hewlett-Packard Company | Partial cache line write transactions in a computing system with a write back cache |
US5613153A (en) * | 1994-10-03 | 1997-03-18 | International Business Machines Corporation | Coherency and synchronization mechanisms for I/O channel controllers in a data processing system |
JP2902976B2 (ja) * | 1995-06-19 | 1999-06-07 | 株式会社東芝 | キャッシュフラッシュ装置 |
US6615300B1 (en) * | 2000-06-19 | 2003-09-02 | Transmeta Corporation | Fast look-up of indirect branch destination in a dynamic translation system |
DE10158393A1 (de) * | 2001-11-28 | 2003-06-12 | Infineon Technologies Ag | Speicher für die Zentraleinheit einer Rechenanlage, Rechenanlage und Verfahren zum Synchronisieren eines Speichers mit dem Hauptspeicher einer Rechenanlage |
US20070271421A1 (en) * | 2006-05-17 | 2007-11-22 | Nam Sung Kim | Reducing aging effect on memory |
WO2008053053A1 (es) * | 2006-11-03 | 2008-05-08 | Intel Corporation | Reducción del efecto de envejecimiento en los registros |
US20150363312A1 (en) * | 2014-06-12 | 2015-12-17 | Samsung Electronics Co., Ltd. | Electronic system with memory control mechanism and method of operation thereof |
US10255183B2 (en) | 2015-07-23 | 2019-04-09 | Arteris, Inc. | Victim buffer for cache coherent systems |
US9542316B1 (en) * | 2015-07-23 | 2017-01-10 | Arteris, Inc. | System and method for adaptation of coherence models between agents |
GB2550903B (en) * | 2016-05-27 | 2019-06-12 | Arm Ip Ltd | Context data control |
US10318436B2 (en) * | 2017-07-25 | 2019-06-11 | Qualcomm Incorporated | Precise invalidation of virtually tagged caches |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3845474A (en) * | 1973-11-05 | 1974-10-29 | Honeywell Inf Systems | Cache store clearing operation for multiprocessor mode |
GB1515376A (en) * | 1975-07-09 | 1978-06-21 | Int Computers Ltd | Data storage systems |
US4053948A (en) * | 1976-06-21 | 1977-10-11 | Ibm Corporation | Look aside array invalidation mechanism |
DE3068498D1 (en) * | 1979-05-09 | 1984-08-16 | Int Computers Ltd | Hierarchical data storage system |
US4426682A (en) * | 1981-05-22 | 1984-01-17 | Harris Corporation | Fast cache flush mechanism |
US4463420A (en) * | 1982-02-23 | 1984-07-31 | International Business Machines Corporation | Multiprocessor cache replacement under task control |
US4714990A (en) * | 1982-09-18 | 1987-12-22 | International Computers Limited | Data storage apparatus |
US4819154A (en) * | 1982-12-09 | 1989-04-04 | Sequoia Systems, Inc. | Memory back up system with one cache memory and two physically separated main memories |
US4713755A (en) * | 1985-06-28 | 1987-12-15 | Hewlett-Packard Company | Cache memory consistency control with explicit software instructions |
EP0220451B1 (de) * | 1985-10-30 | 1994-08-10 | International Business Machines Corporation | Cache-Speicherübereinstimmungsvorrichtung mit Verriegelung |
US4811209A (en) * | 1986-07-31 | 1989-03-07 | Hewlett-Packard Company | Cache memory with multiple valid bits for each data indication the validity within different contents |
DE3633227A1 (de) * | 1986-09-30 | 1988-04-21 | Siemens Ag | Anordnung zur umwandlung einer virtuellen adresse in eine physikalische adresse fuer einen in seiten organisierten arbeitsspeicher einer datenverarbeitungsanlage |
US5025366A (en) * | 1988-01-20 | 1991-06-18 | Advanced Micro Devices, Inc. | Organization of an integrated cache unit for flexible usage in cache system design |
US4977498A (en) * | 1988-04-01 | 1990-12-11 | Digital Equipment Corporation | Data processing system having a data memory interlock coherency scheme |
-
1988
- 1988-06-14 GB GB888814077A patent/GB8814077D0/en active Pending
-
1989
- 1989-05-12 EP EP89304836A patent/EP0347040B1/de not_active Expired - Lifetime
- 1989-05-12 DE DE8989304836T patent/DE68902193T2/de not_active Expired - Fee Related
- 1989-05-16 US US07/352,393 patent/US5146603A/en not_active Expired - Lifetime
- 1989-05-19 ZA ZA893785A patent/ZA893785B/xx unknown
- 1989-06-13 AU AU36292/89A patent/AU608447B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
AU608447B2 (en) | 1991-03-28 |
US5146603A (en) | 1992-09-08 |
DE68902193T2 (de) | 1993-02-04 |
AU3629289A (en) | 1989-12-21 |
EP0347040B1 (de) | 1992-07-22 |
GB8814077D0 (en) | 1988-07-20 |
ZA893785B (en) | 1990-03-28 |
EP0347040A1 (de) | 1989-12-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |