DE602007004173D1 - Silicium-Wafer und dessen Herstellungsmethode - Google Patents

Silicium-Wafer und dessen Herstellungsmethode

Info

Publication number
DE602007004173D1
DE602007004173D1 DE602007004173T DE602007004173T DE602007004173D1 DE 602007004173 D1 DE602007004173 D1 DE 602007004173D1 DE 602007004173 T DE602007004173 T DE 602007004173T DE 602007004173 T DE602007004173 T DE 602007004173T DE 602007004173 D1 DE602007004173 D1 DE 602007004173D1
Authority
DE
Germany
Prior art keywords
production
silicon wafer
wafer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007004173T
Other languages
English (en)
Inventor
Katsuhiko Dr Nakai
Sei Dr Fukushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
Original Assignee
Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Publication of DE602007004173D1 publication Critical patent/DE602007004173D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
    • Y10T428/24992—Density or compression of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE602007004173T 2006-12-01 2007-11-07 Silicium-Wafer und dessen Herstellungsmethode Active DE602007004173D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006326225 2006-12-01
JP2006330914 2006-12-07

Publications (1)

Publication Number Publication Date
DE602007004173D1 true DE602007004173D1 (de) 2010-02-25

Family

ID=39047553

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007004173T Active DE602007004173D1 (de) 2006-12-01 2007-11-07 Silicium-Wafer und dessen Herstellungsmethode

Country Status (6)

Country Link
US (1) US8142885B2 (de)
EP (1) EP1928016B1 (de)
KR (1) KR100945767B1 (de)
DE (1) DE602007004173D1 (de)
SG (1) SG143214A1 (de)
TW (1) TWI390636B (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7928534B2 (en) * 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US8736050B2 (en) * 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
JP2010147248A (ja) * 2008-12-18 2010-07-01 Siltronic Ag アニールウェハおよびアニールウェハの製造方法
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8158489B2 (en) * 2009-06-26 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of TSV backside interconnects by modifying carrier wafers
JP2011138955A (ja) * 2009-12-28 2011-07-14 Siltronic Japan Corp シリコンウェハ及びシリコンウェハの製造方法
US8357939B2 (en) * 2009-12-29 2013-01-22 Siltronic Ag Silicon wafer and production method therefor
US8174124B2 (en) 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing
KR101829676B1 (ko) * 2011-12-29 2018-02-20 삼성전자주식회사 웨이퍼 열 처리 방법
US9245768B2 (en) * 2013-12-17 2016-01-26 Applied Materials, Inc. Method of improving substrate uniformity during rapid thermal processing
KR102089954B1 (ko) * 2014-04-01 2020-03-17 엘지전자 주식회사 코일을 구비하는 mems 스캐너 및 mems 스캐너의 코일 제조 방법
JP6100226B2 (ja) * 2014-11-26 2017-03-22 信越半導体株式会社 シリコン単結晶ウェーハの熱処理方法
TWI759237B (zh) * 2021-07-21 2022-03-21 環球晶圓股份有限公司 晶錠評估方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3007848A (en) * 1958-03-12 1961-11-07 Vol Pak Inc Method of forming an edible medicinal wafer strip package
US4437922A (en) * 1982-03-26 1984-03-20 International Business Machines Corporation Method for tailoring oxygen precipitate particle density and distribution silicon wafers
JPH08213403A (ja) * 1995-02-07 1996-08-20 Sumitomo Metal Ind Ltd 半導体基板及びその製造方法
DE19637182A1 (de) * 1996-09-12 1998-03-19 Wacker Siltronic Halbleitermat Verfahren zur Herstellung von Halbleiterscheiben aus Silicium mit geringer Defektdichte
WO2002002852A1 (fr) * 2000-06-30 2002-01-10 Shin-Etsu Handotai Co., Ltd. Plaquette en silicium monocristallin et procede de fabrication
JP2002043318A (ja) * 2000-07-28 2002-02-08 Shin Etsu Handotai Co Ltd シリコン単結晶ウエーハの製造方法
KR100850333B1 (ko) * 2001-06-28 2008-08-04 신에쯔 한도타이 가부시키가이샤 아닐 웨이퍼의 제조방법 및 아닐 웨이퍼
JP4615161B2 (ja) * 2001-08-23 2011-01-19 信越半導体株式会社 エピタキシャルウエーハの製造方法
JP2003318181A (ja) * 2002-04-25 2003-11-07 Sumitomo Mitsubishi Silicon Corp 半導体シリコン基板におけるｉｇ能の評価方法
EP1780781B1 (de) * 2004-06-30 2019-08-07 SUMCO Corporation Prozess zur herstellung eines siliziumwafers
JP2006040980A (ja) * 2004-07-22 2006-02-09 Sumco Corp シリコンウェーハおよびその製造方法

Also Published As

Publication number Publication date
TW200826200A (en) 2008-06-16
EP1928016A1 (de) 2008-06-04
KR20080050327A (ko) 2008-06-05
TWI390636B (zh) 2013-03-21
EP1928016B1 (de) 2010-01-06
US8142885B2 (en) 2012-03-27
KR100945767B1 (ko) 2010-03-08
SG143214A1 (en) 2008-06-27
US20080131679A1 (en) 2008-06-05

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