DE602006018369D1 - Halbleiterspeicher und testsystem - Google Patents

Halbleiterspeicher und testsystem

Info

Publication number
DE602006018369D1
DE602006018369D1 DE602006018369T DE602006018369T DE602006018369D1 DE 602006018369 D1 DE602006018369 D1 DE 602006018369D1 DE 602006018369 T DE602006018369 T DE 602006018369T DE 602006018369 T DE602006018369 T DE 602006018369T DE 602006018369 D1 DE602006018369 D1 DE 602006018369D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
test system
test
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006018369T
Other languages
English (en)
Inventor
Hiroyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602006018369D1 publication Critical patent/DE602006018369D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
DE602006018369T 2006-03-28 2006-03-28 Halbleiterspeicher und testsystem Active DE602006018369D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/306266 WO2007110926A1 (ja) 2006-03-28 2006-03-28 半導体メモリおよびテストシステム

Publications (1)

Publication Number Publication Date
DE602006018369D1 true DE602006018369D1 (de) 2010-12-30

Family

ID=38540866

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006018369T Active DE602006018369D1 (de) 2006-03-28 2006-03-28 Halbleiterspeicher und testsystem

Country Status (7)

Country Link
US (1) US7719914B2 (de)
EP (1) EP2003652B1 (de)
JP (1) JP4777417B2 (de)
KR (1) KR100959848B1 (de)
CN (1) CN101405818B (de)
DE (1) DE602006018369D1 (de)
WO (1) WO2007110926A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI406290B (zh) * 2009-06-26 2013-08-21 Etron Technology Inc 一種字元線缺陷之偵測裝置與方法
CN102376348B (zh) * 2010-08-20 2013-11-27 中国科学院微电子研究所 一种低功耗的动态随机存储器
KR20130072086A (ko) * 2011-12-21 2013-07-01 에스케이하이닉스 주식회사 퓨즈 회로 및 이의 검증 방법
KR102003894B1 (ko) * 2012-09-20 2019-07-25 에스케이하이닉스 주식회사 셀 어레이, 메모리 및 이를 포함하는 메모리 시스템
KR20170033593A (ko) 2015-09-17 2017-03-27 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
KR102650154B1 (ko) 2016-12-08 2024-03-22 삼성전자주식회사 가상 페일 생성기를 포함하는 메모리 장치 및 그것의 메모리 셀 리페어 방법
WO2020153054A1 (ja) * 2019-01-22 2020-07-30 ソニーセミコンダクタソリューションズ株式会社 撮像装置及び電子機器
JP6994649B2 (ja) * 2019-07-09 2022-01-14 パナソニックIpマネジメント株式会社 半導体メモリデバイス、エラー通知方法
US11960759B2 (en) * 2022-06-28 2024-04-16 Macronix International Co., Ltd. Memory device and data searching method thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182893A (ja) * 1993-12-24 1995-07-21 Mitsubishi Electric Corp 半導体記憶装置
KR19980052127A (ko) * 1996-12-24 1998-09-25 구자홍 메모리 검사기의 비교 장치
JPH11102598A (ja) 1997-09-29 1999-04-13 Toshiba Corp メモリ不良救済解析装置
US6282145B1 (en) * 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
JP2001035187A (ja) * 1999-07-21 2001-02-09 Hitachi Ltd 半導体装置およびその冗長救済方法
WO2001020614A1 (en) * 1999-09-15 2001-03-22 Koninklijke Philips Electronics N.V. Method of testing a memory
JP2001273788A (ja) * 2000-03-29 2001-10-05 Hitachi Ltd 半導体記憶装置
US6563743B2 (en) * 2000-11-27 2003-05-13 Hitachi, Ltd. Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy
JP2003007091A (ja) 2001-06-21 2003-01-10 Mitsubishi Electric Corp 半導体記憶装置の不良ビット救済装置および方法
JP2004220722A (ja) * 2003-01-16 2004-08-05 Renesas Technology Corp 半導体記憶装置
JP2005063529A (ja) 2003-08-08 2005-03-10 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR100716660B1 (ko) * 2004-05-06 2007-05-09 주식회사 하이닉스반도체 반도체 메모리 소자

Also Published As

Publication number Publication date
US7719914B2 (en) 2010-05-18
CN101405818B (zh) 2012-10-03
KR100959848B1 (ko) 2010-05-27
JPWO2007110926A1 (ja) 2009-08-06
WO2007110926A1 (ja) 2007-10-04
EP2003652A9 (de) 2009-04-08
CN101405818A (zh) 2009-04-08
JP4777417B2 (ja) 2011-09-21
US20090027982A1 (en) 2009-01-29
EP2003652A2 (de) 2008-12-17
EP2003652B1 (de) 2010-11-17
KR20080098080A (ko) 2008-11-06
EP2003652A4 (de) 2009-07-01

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