DE602005023598D1 - Halbleiterspeicheranordnung und Informationsverarbeitungssystem - Google Patents

Halbleiterspeicheranordnung und Informationsverarbeitungssystem

Info

Publication number
DE602005023598D1
DE602005023598D1 DE602005023598T DE602005023598T DE602005023598D1 DE 602005023598 D1 DE602005023598 D1 DE 602005023598D1 DE 602005023598 T DE602005023598 T DE 602005023598T DE 602005023598 T DE602005023598 T DE 602005023598T DE 602005023598 D1 DE602005023598 D1 DE 602005023598D1
Authority
DE
Germany
Prior art keywords
information processing
memory device
processing system
semiconductor memory
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005023598T
Other languages
English (en)
Inventor
Shinya Fujioka
Yasuyuki Eguchi
Atsushi Sukeno
Koutoku Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602005023598D1 publication Critical patent/DE602005023598D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE602005023598T 2005-06-07 2005-09-29 Halbleiterspeicheranordnung und Informationsverarbeitungssystem Active DE602005023598D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005166782A JP4516483B2 (ja) 2005-06-07 2005-06-07 半導体記憶装置及び情報処理システム

Publications (1)

Publication Number Publication Date
DE602005023598D1 true DE602005023598D1 (de) 2010-10-28

Family

ID=37335831

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005023598T Active DE602005023598D1 (de) 2005-06-07 2005-09-29 Halbleiterspeicheranordnung und Informationsverarbeitungssystem

Country Status (7)

Country Link
US (1) US7242631B2 (de)
EP (1) EP1744321B1 (de)
JP (1) JP4516483B2 (de)
KR (1) KR100648546B1 (de)
CN (1) CN100524515C (de)
DE (1) DE602005023598D1 (de)
TW (1) TWI271742B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7908516B2 (en) * 2007-03-27 2011-03-15 Microchip Technology Incorporated Low power mode fault recovery method, system and apparatus
JP5098391B2 (ja) * 2007-03-28 2012-12-12 富士通セミコンダクター株式会社 半導体メモリ、システムおよび半導体メモリの動作方法
US8169810B2 (en) 2008-10-08 2012-05-01 Seagate Technology Llc Magnetic memory with asymmetric energy barrier
US8089132B2 (en) 2008-10-09 2012-01-03 Seagate Technology Llc Magnetic memory with phonon glass electron crystal material
US7940600B2 (en) 2008-12-02 2011-05-10 Seagate Technology Llc Non-volatile memory with stray magnetic field compensation
US7859892B2 (en) 2008-12-03 2010-12-28 Seagate Technology Llc Magnetic random access memory with dual spin torque reference layers
US7826259B2 (en) 2009-01-29 2010-11-02 Seagate Technology Llc Staggered STRAM cell
US8053255B2 (en) 2009-03-03 2011-11-08 Seagate Technology Llc STRAM with compensation element and method of making the same
US9007862B2 (en) * 2012-07-12 2015-04-14 Rambus Inc. Reducing memory refresh exit time
US9053811B2 (en) * 2012-09-11 2015-06-09 International Business Machines Corporation Memory device refresh
JP6047033B2 (ja) * 2013-02-25 2016-12-21 ルネサスエレクトロニクス株式会社 Ｌｓｉおよび情報処理システム
TWI559453B (zh) * 2014-03-25 2016-11-21 修平學校財團法人修平科技大學 單埠靜態隨機存取記憶體（四）
US9875785B2 (en) * 2015-10-01 2018-01-23 Qualcomm Incorporated Refresh timer synchronization between memory controller and memory
DE102017106713A1 (de) 2016-04-20 2017-10-26 Samsung Electronics Co., Ltd. Rechensystem, nichtflüchtiges Speichermodul und Verfahren zum Betreiben einer Speichervorrichtung
US9824742B1 (en) * 2016-04-28 2017-11-21 Qualcomm Incorporated DRAM access in self-refresh state
TWI740581B (zh) * 2020-07-20 2021-09-21 華邦電子股份有限公司 虛擬靜態隨機存取記憶體裝置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0778991B2 (ja) * 1988-07-26 1995-08-23 株式会社東芝 半導体メモリ
JPH08138374A (ja) * 1994-11-10 1996-05-31 Nec Corp 半導体メモリ装置およびそのリフレッシュ方法
JPH09306164A (ja) * 1996-05-13 1997-11-28 Internatl Business Mach Corp <Ibm> メモリ・リフレッシュ・システム
TW378330B (en) * 1997-06-03 2000-01-01 Fujitsu Ltd Semiconductor memory device
JP3695902B2 (ja) * 1997-06-24 2005-09-14 富士通株式会社 半導体記憶装置
US6195303B1 (en) * 1999-10-25 2001-02-27 Winbond Electronics Corporation Clock-based transparent refresh mechanisms for DRAMS
JP2002304885A (ja) * 2001-04-05 2002-10-18 Fujitsu Ltd 半導体集積回路
JP3967559B2 (ja) * 2001-04-06 2007-08-29 富士通株式会社 制御回路及び半導体記憶装置
KR100431303B1 (ko) * 2002-06-28 2004-05-12 주식회사 하이닉스반도체 페이지 기록 모드를 수행할 수 있는 슈도 스태틱램
US6999368B2 (en) * 2003-05-27 2006-02-14 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device and semiconductor integrated circuit device
US7345940B2 (en) * 2003-11-18 2008-03-18 Infineon Technologies Ag Method and circuit configuration for refreshing data in a semiconductor memory

Also Published As

Publication number Publication date
CN1877736A (zh) 2006-12-13
EP1744321A1 (de) 2007-01-17
TW200643955A (en) 2006-12-16
JP4516483B2 (ja) 2010-08-04
JP2006344257A (ja) 2006-12-21
CN100524515C (zh) 2009-08-05
TWI271742B (en) 2007-01-21
KR100648546B1 (ko) 2006-11-27
US20060274591A1 (en) 2006-12-07
EP1744321B1 (de) 2010-09-15
US7242631B2 (en) 2007-07-10

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