DE3780387D1 - Herstellungsverfahren einer integrierten schaltung. - Google Patents

Herstellungsverfahren einer integrierten schaltung.

Info

Publication number
DE3780387D1
DE3780387D1 DE8787308303T DE3780387T DE3780387D1 DE 3780387 D1 DE3780387 D1 DE 3780387D1 DE 8787308303 T DE8787308303 T DE 8787308303T DE 3780387 T DE3780387 T DE 3780387T DE 3780387 D1 DE3780387 D1 DE 3780387D1
Authority
DE
Germany
Prior art keywords
manufacturing
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787308303T
Other languages
English (en)
Other versions
DE3780387T2 (de
Inventor
Chozo Okuda
Hiroshi Oka
Takao Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JSR Corp
Original Assignee
Japan Synthetic Rubber Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62134370A external-priority patent/JP2507936B2/ja
Application filed by Japan Synthetic Rubber Co Ltd filed Critical Japan Synthetic Rubber Co Ltd
Publication of DE3780387D1 publication Critical patent/DE3780387D1/de
Application granted granted Critical
Publication of DE3780387T2 publication Critical patent/DE3780387T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Paints Or Removers (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE8787308303T 1986-09-18 1987-09-18 Herstellungsverfahren einer integrierten schaltung. Expired - Lifetime DE3780387T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP21994586 1986-09-18
JP62134370A JP2507936B2 (ja) 1986-09-18 1987-05-29 集積回路の製造方法

Publications (2)

Publication Number Publication Date
DE3780387D1 true DE3780387D1 (de) 1992-08-20
DE3780387T2 DE3780387T2 (de) 1993-01-28

Family

ID=26468499

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787308303T Expired - Lifetime DE3780387T2 (de) 1986-09-18 1987-09-18 Herstellungsverfahren einer integrierten schaltung.

Country Status (2)

Country Link
EP (1) EP0260994B1 (de)
DE (1) DE3780387T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03135048A (ja) * 1989-10-20 1991-06-10 Fujitsu Ltd 半導体装置の製造方法
US5858547A (en) * 1994-07-06 1999-01-12 Alliedsignal, Inc. Novolac polymer planarization films for microelectronic structures
US5853947A (en) * 1995-12-21 1998-12-29 Clariant Finance (Bvi) Limited Quinonediazide positive photoresist utilizing mixed solvent consisting essentially of 3-methyl-3-methoxy butanol and propylene glycol alkyl ether acetate
FR2770685B1 (fr) * 1997-10-31 2000-01-14 Sgs Thomson Microelectronics Procede d'amincissement d'une plaquette de semiconducteur
CN103149800A (zh) * 2011-12-06 2013-06-12 东京应化工业株式会社 蚀刻掩模用组合物及图案形成方法
JP6045920B2 (ja) * 2013-01-17 2016-12-14 東京応化工業株式会社 エッチングマスク用組成物およびパターン形成方法
DE102015118991A1 (de) * 2015-11-05 2017-05-11 Ev Group E. Thallner Gmbh Verfahren zur Behandlung von Millimeter- und/oder Mikrometer- und/oder Nanometerstrukturen an einer Oberfläche eines Substrats
CN110113866B (zh) * 2019-05-27 2021-06-22 深圳市三德冠精密电路科技有限公司 一种防止柔性电路板十字Mark变形的保护方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2424367A1 (de) * 1974-05-20 1975-12-04 Siemens Ag Verfahren zum umhuellen von elektrischen baugruppen mit temperaturempfindlichen elektrischen bauelementen
CA1184321A (en) * 1981-06-30 1985-03-19 John C. Marinace Adhesion of a photoresist to a substrate
DD214636A1 (de) * 1983-04-20 1984-10-17 Freiberg Spurenmetalle Veb Verfahren zur befestigung von halbleiterscheiben fuer die einseitige oberflaechenbearbeitung
JPS6024545A (ja) * 1983-07-21 1985-02-07 Japan Synthetic Rubber Co Ltd ポジ型感光性樹脂組成物
JPS6057339A (ja) * 1983-09-08 1985-04-03 Sumitomo Chem Co Ltd ポジ型フォトレジスト組成物
DE3415817A1 (de) * 1984-04-27 1985-10-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zum abdecken der vorderseite eines mit bauelementstrukturen versehenen substrates
JPS62123444A (ja) * 1985-08-07 1987-06-04 Japan Synthetic Rubber Co Ltd ポジ型感放射線性樹脂組成物

Also Published As

Publication number Publication date
EP0260994A3 (en) 1990-01-10
EP0260994A2 (de) 1988-03-23
EP0260994B1 (de) 1992-07-15
DE3780387T2 (de) 1993-01-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: JSR CORP., TOKIO/TOKYO, JP